JPH0555367A - シリコン基板の埋め込み選択酸化方法およびこの方法による集積回路 - Google Patents

シリコン基板の埋め込み選択酸化方法およびこの方法による集積回路

Info

Publication number
JPH0555367A
JPH0555367A JP4020246A JP2024692A JPH0555367A JP H0555367 A JPH0555367 A JP H0555367A JP 4020246 A JP4020246 A JP 4020246A JP 2024692 A JP2024692 A JP 2024692A JP H0555367 A JPH0555367 A JP H0555367A
Authority
JP
Japan
Prior art keywords
trench
silicon
etching
nitriding
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4020246A
Other languages
English (en)
Japanese (ja)
Inventor
Alain Straboni
アラン・ストラボニ
Kathy Barla
キヤツシー・バーラ
Bernard Vuillermoz
ベルナール・ヴイユルモズ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orange SA
France Telecom R&D SA
Original Assignee
France Telecom SA
Centre National dEtudes des Telecommunications CNET
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by France Telecom SA, Centre National dEtudes des Telecommunications CNET filed Critical France Telecom SA
Publication of JPH0555367A publication Critical patent/JPH0555367A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H10W10/13—
    • H10P14/61—
    • H10W10/0128—
    • H10P14/6309—
    • H10P14/6316—
    • H10P14/6319—
    • H10P14/69215—
    • H10P14/69433—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill

Landscapes

  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
JP4020246A 1991-02-07 1992-02-05 シリコン基板の埋め込み選択酸化方法およびこの方法による集積回路 Withdrawn JPH0555367A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9101381A FR2672731A1 (fr) 1991-02-07 1991-02-07 Procede d'oxydation localisee enterree d'un substrat de silicium et circuit integre correspondant.
FR9101381 1991-02-07

Publications (1)

Publication Number Publication Date
JPH0555367A true JPH0555367A (ja) 1993-03-05

Family

ID=9409445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4020246A Withdrawn JPH0555367A (ja) 1991-02-07 1992-02-05 シリコン基板の埋め込み選択酸化方法およびこの方法による集積回路

Country Status (4)

Country Link
US (1) US5229318A (enExample)
EP (1) EP0498717A1 (enExample)
JP (1) JPH0555367A (enExample)
FR (1) FR2672731A1 (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920022380A (ko) * 1991-05-18 1992-12-19 김광호 반도체장치의 소자분리방법
KR960005553B1 (ko) * 1993-03-31 1996-04-26 현대전자산업주식회사 필드산화막 형성 방법
US5494857A (en) * 1993-07-28 1996-02-27 Digital Equipment Corporation Chemical mechanical planarization of shallow trenches in semiconductor substrates
KR970003731B1 (ko) * 1993-10-14 1997-03-21 엘지반도체 주식회사 반도체 장치의 소자 격리막 제조방법
KR0136518B1 (en) * 1994-04-01 1998-04-24 Hyundai Electroncis Ind Co Ltd Method for forming a field oxide layer
US5470783A (en) * 1994-06-06 1995-11-28 At&T Ipm Corp. Method for integrated circuit device isolation
DE19525072C2 (de) * 1995-07-10 2002-06-27 Infineon Technologies Ag Integrierte Schaltungsanordnung, bei der ein erstes Bauelement an einer Hauptfläche eines Halbleitersubstrats und ein zweites Bauelement am Grabenboden angeordnet sind, und Verfahren zu deren Herstellung
US5661073A (en) * 1995-08-11 1997-08-26 Micron Technology, Inc. Method for forming field oxide having uniform thickness
CZ293360B6 (cs) * 1995-10-26 2004-04-14 Sanofi-Synthelabo Léčivo pro léčení amyotrofické laterální sklerózy
US5672538A (en) * 1995-12-04 1997-09-30 Taiwan Semiconductor Manufacturing Company, Ltd Modified locus isolation process in which surface topology of the locos oxide is smoothed
US5726093A (en) * 1995-12-06 1998-03-10 Taiwan Semiconductor Manufacturing Company Ltd. Two-step planer field oxidation method
US5789305A (en) * 1997-01-27 1998-08-04 Chartered Semiconductor Manufacturing Ltd. Locos with bird's beak suppression by a nitrogen implantation
US5721174A (en) * 1997-02-03 1998-02-24 Chartered Semiconductor Manufacturing Pte Ltd Narrow deep trench isolation process with trench filling by oxidation
US6080665A (en) * 1997-04-11 2000-06-27 Applied Materials, Inc. Integrated nitrogen-treated titanium layer to prevent interaction of titanium and aluminum
US6033997A (en) * 1997-12-29 2000-03-07 Siemens Aktiengesellschaft Reduction of black silicon in semiconductor fabrication
US5940718A (en) * 1998-07-20 1999-08-17 Advanced Micro Devices Nitridation assisted polysilicon sidewall protection in self-aligned shallow trench isolation
US6521959B2 (en) * 1999-10-25 2003-02-18 Samsung Electronics Co., Ltd. SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same
US6613651B1 (en) * 2000-09-05 2003-09-02 Lsi Logic Corporation Integrated circuit isolation system
JP2005183783A (ja) * 2003-12-22 2005-07-07 Seiko Epson Corp 半導体装置の製造方法
DE102004044222A1 (de) * 2004-09-14 2006-03-16 Robert Bosch Gmbh Mikromechanisches Bauelement und entsprechendes Herstellungsverfahren
US8772902B2 (en) 2012-04-19 2014-07-08 International Business Machines Corporation Fabrication of a localized thick box with planar oxide/SOI interface on bulk silicon substrate for silicon photonics integration
US9105686B2 (en) 2012-11-02 2015-08-11 International Business Machines Corporation Fabrication of localized SOI on localized thick box using selective epitaxy on bulk semiconductor substrates for photonics device integration
EP3207553B1 (en) * 2014-10-17 2019-12-04 Teknologian Tutkimuskeskus VTT OY A blank suitable for use as a body of supercapacitor and a supercapacitor
US12020940B2 (en) * 2021-07-15 2024-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing thereof

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1437112A (en) * 1973-09-07 1976-05-26 Mullard Ltd Semiconductor device manufacture
EP0052948A1 (en) * 1980-11-24 1982-06-02 Motorola, Inc. Oxide isolation process
US4563227A (en) * 1981-12-08 1986-01-07 Matsushita Electric Industrial Co., Ltd. Method for manufacturing a semiconductor device
JPS58169935A (ja) * 1982-03-30 1983-10-06 Matsushita Electronics Corp 半導体装置の製造方法
NL187373C (nl) * 1982-10-08 1991-09-02 Philips Nv Werkwijze voor vervaardiging van een halfgeleiderinrichting.
JPS59214237A (ja) * 1983-05-20 1984-12-04 Toshiba Corp 半導体装置の製造方法
WO1988010510A1 (en) * 1987-06-15 1988-12-29 Ncr Corporation Semiconductor field oxide formation process
US4986879A (en) * 1987-06-15 1991-01-22 Ncr Corporation Structure and process for forming semiconductor field oxide using a sealing sidewall of consumable nitride
FR2648956A1 (fr) * 1989-06-23 1990-12-28 Commissariat Energie Atomique Procede de fabrication de l'oxyde de champ d'un circuit integre sur du silicium

Also Published As

Publication number Publication date
FR2672731A1 (fr) 1992-08-14
FR2672731B1 (enExample) 1997-03-07
US5229318A (en) 1993-07-20
EP0498717A1 (fr) 1992-08-12

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Legal Events

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A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990518