JPH0543477Y2 - - Google Patents

Info

Publication number
JPH0543477Y2
JPH0543477Y2 JP1987131195U JP13119587U JPH0543477Y2 JP H0543477 Y2 JPH0543477 Y2 JP H0543477Y2 JP 1987131195 U JP1987131195 U JP 1987131195U JP 13119587 U JP13119587 U JP 13119587U JP H0543477 Y2 JPH0543477 Y2 JP H0543477Y2
Authority
JP
Japan
Prior art keywords
semiconductor device
lead
semiconductor chip
base portion
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1987131195U
Other languages
English (en)
Japanese (ja)
Other versions
JPS6435744U (enExample
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987131195U priority Critical patent/JPH0543477Y2/ja
Publication of JPS6435744U publication Critical patent/JPS6435744U/ja
Application granted granted Critical
Publication of JPH0543477Y2 publication Critical patent/JPH0543477Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP1987131195U 1987-08-28 1987-08-28 Expired - Lifetime JPH0543477Y2 (enExample)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987131195U JPH0543477Y2 (enExample) 1987-08-28 1987-08-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987131195U JPH0543477Y2 (enExample) 1987-08-28 1987-08-28

Publications (2)

Publication Number Publication Date
JPS6435744U JPS6435744U (enExample) 1989-03-03
JPH0543477Y2 true JPH0543477Y2 (enExample) 1993-11-02

Family

ID=31387034

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987131195U Expired - Lifetime JPH0543477Y2 (enExample) 1987-08-28 1987-08-28

Country Status (1)

Country Link
JP (1) JPH0543477Y2 (enExample)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5396969U (enExample) * 1978-01-10 1978-08-07

Also Published As

Publication number Publication date
JPS6435744U (enExample) 1989-03-03

Similar Documents

Publication Publication Date Title
JPS6332223B2 (enExample)
JPS63258050A (ja) 半導体装置
JPH0543477Y2 (enExample)
JPS6238863B2 (enExample)
JPH038113B2 (enExample)
JP2536568B2 (ja) リ―ドフレ―ム
JPS607750A (ja) 絶縁型半導体装置
JPH08186217A (ja) 半導体装置
JPH0351977Y2 (enExample)
JPH0383952U (enExample)
JP2597768Y2 (ja) 電力半導体装置
JPS6244815B2 (enExample)
JPH0582586A (ja) 半導体装置及びその製造方法
JP2771567B2 (ja) 混成集積回路
JPS6236299Y2 (enExample)
JPH056666Y2 (enExample)
JPH07101726B2 (ja) リ−ドフレ−ム
JPS5910759Y2 (ja) 樹脂封止型集積回路装置
JPH07249708A (ja) 半導体装置及びその実装構造
JPS63160262A (ja) リ−ドフレ−ムおよびそれを用いた半導体装置
JPH0438526Y2 (enExample)
JPH02268459A (ja) 半導体パッケージ
JPH04146659A (ja) 半導体装置およびその製造方法
JPH02246143A (ja) リードフレーム
JPH1012782A (ja) 混成集積回路装置およびその製造方法