JPH0530087B2 - - Google Patents

Info

Publication number
JPH0530087B2
JPH0530087B2 JP62246751A JP24675187A JPH0530087B2 JP H0530087 B2 JPH0530087 B2 JP H0530087B2 JP 62246751 A JP62246751 A JP 62246751A JP 24675187 A JP24675187 A JP 24675187A JP H0530087 B2 JPH0530087 B2 JP H0530087B2
Authority
JP
Japan
Prior art keywords
fet
output
signal
clock signal
conduction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62246751A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6489811A (en
Inventor
Shoji Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP62246751A priority Critical patent/JPS6489811A/ja
Publication of JPS6489811A publication Critical patent/JPS6489811A/ja
Publication of JPH0530087B2 publication Critical patent/JPH0530087B2/ja
Granted legal-status Critical Current

Links

JP62246751A 1987-09-30 1987-09-30 Logic circuit Granted JPS6489811A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62246751A JPS6489811A (en) 1987-09-30 1987-09-30 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62246751A JPS6489811A (en) 1987-09-30 1987-09-30 Logic circuit

Publications (2)

Publication Number Publication Date
JPS6489811A JPS6489811A (en) 1989-04-05
JPH0530087B2 true JPH0530087B2 (cs) 1993-05-07

Family

ID=17153113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62246751A Granted JPS6489811A (en) 1987-09-30 1987-09-30 Logic circuit

Country Status (1)

Country Link
JP (1) JPS6489811A (cs)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04239810A (ja) * 1991-01-23 1992-08-27 Nec Ic Microcomput Syst Ltd 単相スタティックラッチ回路

Also Published As

Publication number Publication date
JPS6489811A (en) 1989-04-05

Similar Documents

Publication Publication Date Title
JPS5925421A (ja) 同期式論理回路
JPH0693608B2 (ja) Ｃｍｏｓ ｄ形フリツプフロツプ回路
US11726141B2 (en) Flip-flop circuitry
US4160173A (en) Logic circuit with two pairs of cross-coupled nand/nor gates
JPH0212691A (ja) 集積回路
US5391935A (en) Assertive latching flip-flop
JPH0736507B2 (ja) 半導体論理回路
US4056736A (en) Injection logic arrangements
JPH02268515A (ja) Ｂｉｃｍｏｓロジツク回路
JPH0530087B2 (cs)
US5172010A (en) Clock chopper/stretcher for high end machines
JP2786463B2 (ja) フリップフロップ回路
US4201927A (en) Circuit for producing sequentially spaced pulses
JPH07131302A (ja) レジスタ回路
JPS61270916A (ja) ３ステ−ト・ドライバ回路
JP2786464B2 (ja) フリップフロップ回路
US6661257B2 (en) Method for clocking charge recycling differential logic
JP2569750B2 (ja) 同期型ドライバ回路
JP2808783B2 (ja) 電流切り替え型差動論理回路
JPH05110386A (ja) 半導体装置
US20030117178A1 (en) Modified charge recycling differential logic
KR890005160B1 (ko) D-플립플롭과 버퍼 겸용 집적회로
JP2564300B2 (ja) ダイナミツク型フリツプフロツプ
JPH0197008A (ja) 半導体集積回路装置
JPS596629A (ja) プログラマブルロジツクアレイ

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080507

Year of fee payment: 15