JPS6489811A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS6489811A
JPS6489811A JP62246751A JP24675187A JPS6489811A JP S6489811 A JPS6489811 A JP S6489811A JP 62246751 A JP62246751 A JP 62246751A JP 24675187 A JP24675187 A JP 24675187A JP S6489811 A JPS6489811 A JP S6489811A
Authority
JP
Japan
Prior art keywords
output
signal
input signal
resistor
clamped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62246751A
Other languages
Japanese (ja)
Other versions
JPH0530087B2 (en
Inventor
Shoji Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62246751A priority Critical patent/JPS6489811A/en
Publication of JPS6489811A publication Critical patent/JPS6489811A/en
Publication of JPH0530087B2 publication Critical patent/JPH0530087B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To attain high speed output signal by constituting the output section by a bipolar transistor(TR) and giving an output signal with an opposite polarity to the input signal according to the 1st and 2nd clock signals and holding the output state. CONSTITUTION:An input section I consists of N-channel MOS TRs N1-N4, an inverter I11 and a resistor R1. An output section II consists of NPN bipolar TRs Q1, Q2 clamped by a Schottky barrier diode, an NPN bipolar TR Q3 not clamped, a resistor R2 and a pull-down circuit P.D. In applying the 1st and 2nd clock signals phi, the inverse of phi, the level inverted to the level of the input signal D before the clock signal is applied is given as the output signal and in stopping the application of the clock signal, the output stage is held regardless of the change in the input signal D. Thus, the high operating speed and high load drive capability are attained.
JP62246751A 1987-09-30 1987-09-30 Logic circuit Granted JPS6489811A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62246751A JPS6489811A (en) 1987-09-30 1987-09-30 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62246751A JPS6489811A (en) 1987-09-30 1987-09-30 Logic circuit

Publications (2)

Publication Number Publication Date
JPS6489811A true JPS6489811A (en) 1989-04-05
JPH0530087B2 JPH0530087B2 (en) 1993-05-07

Family

ID=17153113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62246751A Granted JPS6489811A (en) 1987-09-30 1987-09-30 Logic circuit

Country Status (1)

Country Link
JP (1) JPS6489811A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04239810A (en) * 1991-01-23 1992-08-27 Nec Ic Microcomput Syst Ltd Single phase static latch circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04239810A (en) * 1991-01-23 1992-08-27 Nec Ic Microcomput Syst Ltd Single phase static latch circuit

Also Published As

Publication number Publication date
JPH0530087B2 (en) 1993-05-07

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