JPS6489811A - Logic circuit - Google Patents
Logic circuitInfo
- Publication number
- JPS6489811A JPS6489811A JP62246751A JP24675187A JPS6489811A JP S6489811 A JPS6489811 A JP S6489811A JP 62246751 A JP62246751 A JP 62246751A JP 24675187 A JP24675187 A JP 24675187A JP S6489811 A JPS6489811 A JP S6489811A
- Authority
- JP
- Japan
- Prior art keywords
- output
- signal
- input signal
- resistor
- clamped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE:To attain high speed output signal by constituting the output section by a bipolar transistor(TR) and giving an output signal with an opposite polarity to the input signal according to the 1st and 2nd clock signals and holding the output state. CONSTITUTION:An input section I consists of N-channel MOS TRs N1-N4, an inverter I11 and a resistor R1. An output section II consists of NPN bipolar TRs Q1, Q2 clamped by a Schottky barrier diode, an NPN bipolar TR Q3 not clamped, a resistor R2 and a pull-down circuit P.D. In applying the 1st and 2nd clock signals phi, the inverse of phi, the level inverted to the level of the input signal D before the clock signal is applied is given as the output signal and in stopping the application of the clock signal, the output stage is held regardless of the change in the input signal D. Thus, the high operating speed and high load drive capability are attained.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62246751A JPS6489811A (en) | 1987-09-30 | 1987-09-30 | Logic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62246751A JPS6489811A (en) | 1987-09-30 | 1987-09-30 | Logic circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6489811A true JPS6489811A (en) | 1989-04-05 |
JPH0530087B2 JPH0530087B2 (en) | 1993-05-07 |
Family
ID=17153113
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62246751A Granted JPS6489811A (en) | 1987-09-30 | 1987-09-30 | Logic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6489811A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04239810A (en) * | 1991-01-23 | 1992-08-27 | Nec Ic Microcomput Syst Ltd | Single phase static latch circuit |
-
1987
- 1987-09-30 JP JP62246751A patent/JPS6489811A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04239810A (en) * | 1991-01-23 | 1992-08-27 | Nec Ic Microcomput Syst Ltd | Single phase static latch circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0530087B2 (en) | 1993-05-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term | ||
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080507 Year of fee payment: 15 |