JPS6377218A - Semiconductor logic circuit - Google Patents

Abstract

PURPOSE:To attain high speed operation by providing a level shift circuit com prising plural transistors (TRs) of Darlington connection between an input of an off-buffer circuit and an off-buffer circuit so as to shift an H level output voltage to a proper value. CONSTITUTION:The level shift circuit 5 comprising NPN TRs Q5, Q6 of Darling ton connection or the like is provided between a power supply VCC and a base input of an NPN TR Q3 of the off-buffer circuit. Then with an input voltage at H level, a PNP TR Q1 is turned off, an NPN TR Q2 is turned on, the TR Q3 is turned off and an NPN TR Q4 is tuned on, then an L output voltage of the circuit is nearly 0.4V. With the input voltage at an L level, the TR Q1 is turned on, the TR Q2 is turned off, the TR Q3 is turned on and the TR Q4 is turned off, and also the TRs Q5, Q6 of the circuit 5 are turned on, then the H level output voltage of the circuit is nearly 2V. Thus, the voltage deference with the input threshold value voltage of the next stage circuit is decreased, then the switching speed is quickened and the power consumption is reduced.

Description

[Detailed Description of the Invention] [Required by JI] The semiconductor logic circuit of the present invention provides a level shift circuit in which a plurality of transistors are connected in Darlington between the input of an off-buffer circuit and a high voltage TrLW terminal. Reduces the high potential output level of semiconductor logic circuits,
This makes the logic amplitude of the output voltage appropriate and speeds up the logic operation.

[Industrial application field]

The unissued I is related to semiconductor logic circuits, and furthermore,
In Western terms, gate array, standard cell s, Ls
The present invention relates to a bipolar semiconductor logic circuit equipped with an off-buffer circuit used for internal gates in industrial equipment.

[Conventional technology]

Fig. 2 is a circuit diagram of a conventional inverter function. In Fig. 0, l is an input circuit consisting of a PNP transistor Q1;
2 is a phase split transistor consisting of an NPN) transistor Q2. 3 is an NPN transistor Q3. An off-buffer circuit includes a resistor R3 and a diode Di, and 4 is an output transistor consisting of an NPN transistor Q4. Note that R1 and R2 are pull-up resistors.

R4 is a pull-down resistor.

Next, the operation of the circuit shown in FIG. 2 will be explained. When the input voltage is “H” level, Ql is off.

Q2 turns on. Therefore, Q3 is turned off and Q4 is turned on, so that the output of the circuit becomes "L" level.

Next, when the input voltage changes to "L" level, Ql is turned on and Q2 is turned off. Therefore, since Q3 is turned on and Q4 is turned off, the output of the circuit becomes "H" level. in this way,
The circuit shown in FIG. 2 operates as an inverter.

Next, assuming tVcc=5V and GND=OV, the output voltage of the output of the circuit shown in FIG. 2 is approximately estimated. Q4 when the output is L''
is on, the output voltage is approximately 0.4v.

On the other hand, since Q3 is on when the output is at a high level,
VBE (base-emitter voltage) of Q3 and V of Dl
Considering r (diode forward voltage), the output voltage will be approximately 3.5v.

[+Xt a point that the invention seeks to solve] By the way, the second point
The input threshold voltage of the logic circuit in the figure is VBE (Q2) + V
et (Q4)-VBE (Ql)=V[l[, so it is approximately 0.7V.

In other words, when constructing an integrated circuit by connecting two logic circuits as shown in Fig. 2 in multiple stages, the input threshold voltage (0°7V) and '
The difference with the "L" level input voltage (0.4V) is small at 0.3V, but the difference with the "H" level input voltage (3.5V) is 2.
．． Since the voltage is extremely large at 8V, the switching speed becomes slow.

The present invention was created in view of such conventional problems, and an object of the present invention is to provide a semiconductor logic circuit that shifts the "H" level output voltage to an appropriate value and enables high-speed operation.

[Means for solving problems]

An off-buffer circuit whose input is the collector output of the 7A split transistor of the present invention, and an output transistor whose base input is the emitter output of the phase-split transistor and which is connected in series with the off-buffer circuit between its power supply terminals. The semiconductor logic circuit is characterized in that a level shift circuit including a plurality of transistors connected in a Darlington manner is provided between the input of the off-buffer circuit and a high voltage power supply terminal.

[Effect]

The high level shift output voltage of the semiconductor logic circuit is reduced to a proper value by the level shift circuit.

Therefore, the difference between the input threshold voltage of the next stage logic circuit to be driven is reduced, and the switching speed is improved.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a semiconductor logic circuit according to an embodiment of the present invention. In FIG. 0, the same reference numerals as in FIG. 2 indicate the same components.

What is different from Fig. 2 is the power supply Wee and the off-buff circuit 3.
between the base input of Q3 and the NP of Darlington connection.
N transistor Q5. The point is that a level shift circuit 5 consisting of C10 and 7'A/up resistors R5 and R5 is provided. Note that R7 is a pull-down resistor.

Next, the operation of the embodiment circuit shown in FIG. 1 will be explained. When the input voltage is at "H" level, Ql is turned off and Q2 is turned on. Therefore, Q3 is off and Q4 is on, so the L of the circuit
``The output voltage will be approximately 0°4V.

Next, when the input voltage becomes “L” level, Ql turns on and Q2
turns off. Therefore, Q3 is turned off, Q4 is turned off, and Q5 and Q6 of level shift circuit 5 are also turned on.
The H'' level output voltage is approximately 2V.

As described above, according to the embodiment circuit of the present invention, the "H" level output voltage (2V) and the input threshold voltage of the next stage circuit (0.7V
), it is possible to increase the switching speed and reduce power consumption.

In the example circuit, two transistors Q5 and Q6
Although the level shift circuit is configured by connecting the transistors in a Darlington manner, the number of transistors in the Darlington connection can be increased depending on the required "H" level output voltage.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to reduce the "H'" level output voltage to an appropriate value, so that driving the primary stage circuit at high speed becomes a circuit and reduces power consumption. The less you use, the more you can use it.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor logic circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a semiconductor logic circuit according to a conventional example. (Explanation of symbols) 1...Input circuit, 2...Level shift transistor, 3...Off buffer circuit. 4... Output transistor, 5... Level shift circuit.

Claims (1)

[Claims] An off-buffer circuit that takes the collector output of a phase-split transistor as an input, and an output that takes the emitter output of the phase-split transistor as a base input and is connected in series with the off-buffer circuit between power supply terminals. A semiconductor logic circuit comprising: a level shift circuit in which a plurality of transistors are connected in a Darlington manner between an input of the off-buffer circuit and a high voltage power supply terminal.