KR930006087Y1 - 3 state buffer - Google Patents

3 state buffer Download PDF

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KR930006087Y1
KR930006087Y1 KR2019890005019U KR890005019U KR930006087Y1 KR 930006087 Y1 KR930006087 Y1 KR 930006087Y1 KR 2019890005019 U KR2019890005019 U KR 2019890005019U KR 890005019 U KR890005019 U KR 890005019U KR 930006087 Y1 KR930006087 Y1 KR 930006087Y1
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transistor
collector
transistors
base
turned
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KR2019890005019U
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KR900019444U (en
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박승우
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/001—Arrangements for reducing power consumption in bipolar transistor circuits

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

내용 없음.No content.

Description

3진논리 버퍼Ternary logic buffer

제1도는 일반적인 2진논리 버퍼 회로도.1 is a general binary logic buffer circuit.

제2도는 본 고안의 3진논리 변환회로도.2 is a ternary logic conversion circuit diagram of the present invention.

제3a도,제3b는 제1도 및 제2도의 입출력 관계도.3A and 3B are input / output relationship diagrams of FIGS. 1 and 2.

본 고안은 논리회로에 관한 것으로, 특히 전위, 저전위 뿐아니라 오픈상태도 하나의 논리상태로 취급하며, 전력소모가 적은 3진논리 버퍼에 관한 것이다.The present invention relates to a logic circuit, and more particularly, to a ternary logic buffer that treats an open state as well as a potential and a low potential as one logic state, and has low power consumption.

2진논리 버퍼는 제1도에 도시한 바와같이 저항(R1),(R2)으로 바이어스된 트랜지스터(Q1)의 베이스에 입력단자(Vi)를 역방향 접속된 다이오드(D1)를 통해 접속하고, 그 트랜지스터(Q1)의 콜렉터를 트랜지스터(Q2)의 베이스에, 에미터는 다이오드(D2)를 통해 접지에 접속하며, 상기 트랜지스터(Q2)의 콜렉터는 트랜지스터(Q4)의 베이스에, 에미터는 트랜지스터(Q3)의 베이스측 및 콜렉터측, 트랜지스터(Q6)의 베이스에 공통접속하고, 상기 트랜지스터(Q4)와 달링톤 접속되는 트랜지스터(Q5)의 콜렉터에 공통접속하여 이 접속점이 출력단이 되게 구성하는 것이다.As shown in FIG. 1, the binary logic buffer connects the input terminal Vi to the base of the transistor Q1 biased by the resistors R1 and R2 through the diode D1 connected in the reverse direction. The collector of transistor Q1 is connected to the base of transistor Q2, the emitter is connected to ground via diode D2, the collector of transistor Q2 is at the base of transistor Q4, and the emitter is transistor Q3. The common side is connected to the base side, the collector side of the transistor, and the base of the transistor Q6, and is commonly connected to the collector of the transistor Q5 which is connected to the transistor Q4 and Darlington, so that this connection point becomes an output terminal.

따라서 고전위신호가 입력되면 다이오드(D1)가 오프되며, 전원(Vcc)이 트랜지스터(Q1)의 베이스에 가해져 트랜지스터(Q1)가 온된다. 이때 트랜지스터(Q1)의 베이스전류는 (Vcc-2VBE)/R1 180㎂이고, 콜렉터전류는 최대로 (Vcc-VBE)/R2 430㎂이므로 트랜지스터(Q1)가 포화영역에서 동작하며 콜렉터로부터 약 0.8V정도의 저전위신호가 출력되어 트랜지스터(Q2)가 오프되고, 이에 의해 트랜지스터(Q3),(Q6)도 오프된다.Therefore, when the high potential signal is input, the diode D1 is turned off, and the power supply Vcc is applied to the base of the transistor Q1, so that the transistor Q1 is turned on. At this time, the base current of transistor Q1 is (Vcc-2V BE ) / R1 180mA, and the collector current is (Vcc-V BE ) / R2 430㎂ max. The low potential signal of about 0.8V is outputted to turn off the transistor Q2, thereby turning off the transistors Q3 and Q6.

그리고 달링톤 접속된 트랜지스터(Q4, Q5)가 온되어 출력단자(V0)로 고전위신호가 출력된다.The Darlington connected transistors Q4 and Q5 are turned on to output a high potential signal to the output terminal V 0 .

한편 저전위신호가 입력되면 다이오드(D1)가 온되어 트랜지스터(Q1)의 베이스에 저전위신호가 가해져 그는 오프되고, 이때 트랜지스터(Q2)가 온되어 트랜지스터(Q4, Q5)가 각각 오프, 온된다. 따라서 출력단자(V0)로 저전위신호가 출력된다.On the other hand, when the low potential signal is input, the diode D1 is turned on to apply the low potential signal to the base of the transistor Q1, which is turned off. At this time, the transistor Q2 is turned on so that the transistors Q4 and Q5 are turned off and on, respectively. . Therefore, a low potential signal is output to the output terminal V 0 .

그런데 입력상태가 오픈상태가 되면 다이오드(D1)가 오프되므로 상기 고전위신호 입력시와 같이 출력단자(V0)로 저전위신호가 출력된다.However, since the diode D1 is turned off when the input state is open, the low potential signal is output to the output terminal V 0 as in the high potential signal input.

이의 입출력관계를 표로 나타내면 제3a도와 같고, 입력이 오픈상태일 때도 고전위신호가 출력되므로 3진논리 시스템에 적용할 수 없어 3진논리로 동작되는 버퍼가 필요하다.Its input / output relationship is shown in Table 3a, and since the high potential signal is output even when the input is open, it is not applicable to the ternary logic system, so a buffer operated in ternary logic is needed.

따라서 본 고안은 3진논리 시스템에 적용할 수 있게 안출한 버퍼로서,이를 첨부한 도면에 의하여 상세히 설명하면 다음과 같다.Therefore, the present invention is a buffer designed to be applied to a ternary logic system, which will be described in detail with reference to the accompanying drawings.

본 고안의 3진논리 버퍼는 제2도에 도시한 바와같이 저항(R1),(R2)으로 트랜지스터(Q11)의 베이스-에미터 및 콜렉터-베이스간 바이어스를 설정하고, 입력단자(Vi)를 트랜지스터(Q13, Q14)의 베이스에 공통접속하며, 상기 트랜지스터(Q11)의 콜렉터를 상기 트랜지스터(Q13)의 에미터측에 접속함과 아울러 저항(R5),(R6)으로 트랜지스터(Q15)의 콜렉터-베이스, 에미터-베이스간에 바이어스를 설정하여 이의 콜렉터측에 상기 트랜지스터(Q14)의 에미터를 접속함, 각기 전류미러로 동작하는 트랜지스터(Q11, Q12), (Q15, Q16)의 출력측을 트랜지스터(Q18),(Q17)의 베이스에 접속하고 상기 트랜지스터(Q17, Q18)의 콜렉터에서 출력신호를 인출한 것으로, 이의 작용 및 효과는 다음과 같다.As shown in FIG. 2, the ternary logic buffer of the present invention sets the bias between the base-emitter and the collector-base of the transistor Q11 with resistors R1 and R2, and sets the input terminal Vi. Commonly connected to the bases of the transistors Q13 and Q14, the collector of the transistor Q11 is connected to the emitter side of the transistor Q13, and the collectors of the transistor Q15 are connected to the resistors R5 and R6. A bias is set between the base and the emitter-base, and the emitter of the transistor Q14 is connected to the collector side thereof, and the output side of the transistors Q11, Q12 and Q15, Q16 operating as current mirrors are connected to the transistor ( Connected to the bases of Q18) and Q17 and outputting the output signal from the collectors of the transistors Q17 and Q18, its effects and effects are as follows.

트랜지스터(Q11)가 온될때 베이스-에미터간 전압이 0.7V이어야 하므로 저항(R1)에 흐르는 전류는70(㎂)이다.When transistor Q11 is on, the base-emitter voltage should be 0.7V, so the current flowing through resistor R1 70 (㎂).

이 전류는 저항(R2)을 통해서도 흐르므로 저항(R2) 양단에 가해지는 전압은 70(㎂)×R2=2.8V이다.Since this current also flows through the resistor R2, the voltage applied across the resistor R2 is 70 占 RR2 = 2.8V.

따라서, 트랜지스터(Q11)가 온되었을때 콜렉터-에미터간 전압은 3.5V로 고정된다.Thus, the collector-emitter voltage is fixed at 3.5V when transistor Q11 is on.

한편, 트랜지스터(Q11)의 오프시 베이스-에미터간 전압을 0.5V라 하면 콜렉터-에미터간 전압[VBE(Q11)]은,이므로 트랜지스터(Q11)의 콜렉터-에미터간 전압이 2.5V이하가 되면 트랜지스터(Q13)는 오프상태이다.On the other hand, if the base-emitter voltage is 0.5V when the transistor Q11 is off, the collector-emitter voltage [V BE (Q11)] is Therefore, when the collector-emitter voltage of the transistor Q11 becomes 2.5 V or less, the transistor Q13 is turned off.

그리고 트랜지스터(Q15)의 콜렉터-에미터간 전압이다.And the collector-emitter voltage of transistor Q15 to be.

따라서 고전위신호가 입력될때 Vcc-Vi≤2V이므로 트랜지스터(Q11, Q13)가 오프되고, 트랜지스터(Q12)가 오프되며, 이에 의해 트랜지스터(Q18)가 오프된다.Therefore, when the high potential signal is input, the transistors Q11 and Q13 are turned off and the transistors Q12 are turned off because the Vcc-Vi≤2V, whereby the transistor Q18 is turned off.

한편, 트랜지스터(Q14)의 콜렉터 전류는(Ic)는,On the other hand, the collector current of the transistor Q14 is (Ic),

인데, 저항(R5,R6)에 70㎂의 전류가 흘러 트랜지스터(Q15,Q16)의 콜렉터에 30㎂의 전류가 흐른다. In this case, 70 mA of current flows through the resistors R5 and R6, and 30 mA of current flows through the collectors of the transistors Q15 and Q16.

그러므로 저항(R7)에 의해 트랜지스터(Q17)의 에미터-베이스간 전압을 0.7V이상이 되어 트랜지스터(Q17)가 온되고, 이에 따라 출력단자(V0)로 고전위신호가 출력된다.Therefore, by a resistor (R7) to the emitter of the transistor (Q17) - it is more than 0.7V the voltage between the base and the transistor (Q17) turned on, so that a high potential signal is outputted to the output terminal (V 0).

그리고 저전위신호가 입력될때 Vcc-Vi≤2.5V이므로 트랜지스터(Q11, Q13)가 온되고, 이에 따라 트랜지스터(Q12)가 온되며 트랜지스터(Q18)가 온된다.When the low potential signal is input, the transistors Q11 and Q13 are turned on because Vcc-Vi≤2.5V. Accordingly, the transistors Q12 are turned on and the transistors Q18 are turned on.

이 때 트랜지스터(Q13)의 콜렉터전류(Ic')는,At this time, the collector current Ic 'of the transistor Q13 is

인데, 70㎂의 전류는 저항(R1,R2)을 통해 바이어스 전류도 흐르고, 트랜지스터(Q11)의 콜렉터에 30㎂의 전류가 흐른다. In this case, a 70 mA current flows through the resistors R1 and R2 as well as a bias current, and a current of 30 mA flows through the collector of the transistor Q11.

이에 의해 트랜지스터(Q12)의 콜렉터에도 30㎂의 전류가 흐르게 되므로 트랜지스터(Q18)가 온됨과 아울러, 저전위 입력신호에 의해 트랜지스터(Q14)가 오프되어 트랜지스터(Q15, Q16)가 오프되고, 이에따라 트랜지스터(Q17)가 오프되므로 출력단자(V0)로 저전위신호가 출력된다.As a result, a current of 30 mA flows through the collector of the transistor Q12, which turns on the transistor Q18 and turns off the transistor Q14 by the low potential input signal, thereby turning off the transistors Q15 and Q16. Since Q17 is turned off, a low potential signal is output to the output terminal V 0 .

입력상태가 오픈상태인 때를 살펴보면, 트랜지스터(Q11, Q15)가 동시에 온되려면When the input state is open, the transistors Q11 and Q15 are simultaneously turned on

이어야 한다. Should be

그런데, Vcc=5V이면 VBE=0.46V이므로 트랜지스터(Q11, Q15)가 오프상태이며, 따라서 트랜지스터(Q17, Q18) 도 오프되므로 출력신호는 오프상태가 된다.By the way, when Vcc = 5V, the transistors Q11 and Q15 are off because V BE = 0.46V, so the transistors Q17 and Q18 are also off, so the output signal is off.

이상의 입출력관계는 제3b도에 보인 바와 같다. 상기의 상세한 설명과 같이 본 고안은 오픈상태를 하나의 논리상태로 처리하므로 3진논리 시스템의구성이 가능케 하며, 입력상태가 오프상태일 때 전력소모를 줄이는 효과가 있다.The above input / output relationship is as shown in FIG. 3B. As described above, the present invention processes the open state into one logic state, thereby enabling the construction of a ternary logic system, and reducing power consumption when the input state is off.

Claims (1)

저항(R1),(R2)으로 트랜지스터(Q11)의 베이스-에미터, 콜렉터-베이스간 바이어스를 설정하고, 입력단자(Vi)를 트랜지스터(Q13, Q14)의 베이스에 공통접속하며, 상기 트랜지스터(Q11)의 콜렉터-베이스, 에미터-베이스간 바이어스를 설정하여 이의 콜렉터측에 상기 트랜지스터(Q14)의 에미터를 접속하며, 상기 트랜지스터(Q11,Q15,)와 전류미를 형성하는 트랜지스터(Q12),(Q16)의 콜렉터를 출력단 트랜지스터(Q18),(Q17)의 베이스에 각기 접속하여 그들 콜렉터의 접속점에 출력신호가 가해지게 구성한 것을 특징으로 하는 3진논리버퍼.The resistors R1 and R2 set the base-emitter and collector-base biases of the transistor Q11, and the input terminal Vi is commonly connected to the bases of the transistors Q13 and Q14. Transistor Q12 which sets the collector-base and emitter-base biases of Q11), connects the emitters of the transistor Q14 to the collector side thereof, and forms currents with the transistors Q11, Q15, And a collector of (Q16) connected to the bases of the output transistors (Q18) and (Q17), respectively, so that an output signal is applied to the connection point of those collectors.
KR2019890005019U 1989-04-24 1989-04-24 3 state buffer KR930006087Y1 (en)

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