KR930006086Y1 - 3 stae logic conversion circuit - Google Patents

Abstract

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Description

Ternary logic conversion circuit

1 is a general binary logic buffer circuit.

2 is a ternary logic conversion circuit diagram of the present invention.

3A and 3B are input / output relationship diagrams of FIGS. 1 and 2.

The present invention relates to a logic circuit, and more particularly, to a ternary logic conversion circuit that treats an open state as well as a high potential and a low potential as one logic state, and converts and outputs an input signal.

In general, a binary logic buffer, which is one of the logic circuits applied to a binary logic system, has an input terminal Vi at the base of a transistor Q1 biased by resistors R1 and R2 as shown in FIG. Is connected through a diode D1 connected in the reverse direction, the collector of the transistor Q1 is connected to the base of the transistor Q2, the emitter is connected to ground through the diode D2, and the collector of the transistor Q2 is In the base of transistor Q4, the emitter is commonly connected to the base side of the transistor Q3, the collector side, and the base of the transistor Q6, and the base of the transistor Q5 connected to the transistor Q4 is darlingly connected to the base of the transistor Q4. Is connected to the collector and the collector of the transistor Q6 so that this connection point becomes an output terminal.

Therefore, when the high potential signal is input, the diode D1 is turned off, and the power supply Vcc is applied to the base of the transistor Q1, so that the transistor Q1 is turned on. At this time, the base current of transistor Q1 is (Vcc-2V _BE ) / R1 180mA, and the selector current is (Vcc-V _BE ) / R2 430mA, so transistor Q1 operates in the saturation region. A low potential signal of about 0.8 V is output so that the transistor Q2 is turned off, thereby turning off the transistors Q3 and Q6.

The Darlington connected transistors Q4 and Q5 are turned on to output a high potential signal to the output terminal V ₀ .

On the other hand, when the low potential signal is inputted, the diode D1 is turned on to apply the low potential signal to the base of the transistor Q1, which is turned off. At this time, the transistor Q2 is turned on so that the transistors Q4, Q5, and Q3 and Q6 Are off and on respectively. Therefore, a low potential signal is output to the output terminal V ₀ .

However, when the input state is open, the diode D1 is turned off, and thus the high potential signal is output to the output terminal V ₀ as in the high potential signal input.

The input / output relationship thereof is shown in Table 3a, and since the high potential signal is output even when the input is open, it is not applicable to the ternary logic system, so a buffer that operates in ternary logic is needed.

Therefore, the present invention is a buffer designed to be applied to a ternary logic system, which will be described in detail with reference to the accompanying drawings.

In the ternary logic conversion circuit of the present invention, as shown in FIG. 2, the transistor Q1 biased to the resistors R1 and R2 by commonly connecting the input terminal Vi to the bases of the transistors Q2 and Q3. Is connected to the emitter side of transistor Q2 and the collector of transistor Q5, and the emitter of transistor Q3 is connected to the collector of transistor Q4 biased by resistors R5 and R6. On the other hand, the transistors Q5 and Q6 form a current mirror with the transistor Q4, and the collectors of transistors Q7 and Q8 which are current mirrors are connected to the collectors of the transistors Q6 and Q11. The bases are connected to each other, and are commonly connected to the current source I of the transistor Q9 and the base of the transistor Q10, which form a current mirror with the transistor Q1, to the collector connection points of the transistors Q10 and Q11. It is configured to apply output signal, its action and effect Is shown below.

When the input is at high potential, the collector current [I (Q3)] of transistor Q3 is

Since 70 mA of current flows to the bias current through the resistors R5 and R6, and 110 mA of current flows to the collector of the transistor Q4, the transistor Q4 and the current mirror transistors Q5 and Q6. 110 mA of current also flows through the collector of N, and the same is true of the transistors Q7 and Q8.

At this time, 70 mA of current flows through the bias resistors R1 and R2, and 40 mA of current flows through the collector of the transistor Q1, and 40 is also collected in the collector of the transistor Q9 forming the current mirror with the transistor Q1. Current of I must flow but transistor Q9 is saturated because current source I is 20 mA, and transistor Q10 is turned off.

And the transistor (Q11) by the collector current of the transistor (Q8) on the low potential signal is outputted to the output terminal (V _0).

When the input is open, the transistors Q2 and Q53 of the collector current Ic are

Therefore, the voltages across the resistors R1 and R6 are only about 0.4V by this current, and the transistors Q1 and Q4 are turned off. Accordingly, the transistors Q9, Q5, Q6, and ( Q7-Q8) and Q11 are turned off.

The transistor Q10 is turned on by the current source I, and a high potential signal is output to the output terminal V ₀ .

In addition, when the input is at low potential, transistor Q3 is turned off, and transistors Q4-Q6, Q7-Q8, and Q11 are turned off, and collector current Ic (Q2) of transistor Q2 is

In this case, since 30 mA of current flows to the collector of transistor Q1, the current must also flow to the collector of transistor Q9 forming the current mirror.

However, since the current source I is only 20 mA, the transistor Q9 is saturated, and as the transistor Q10 is turned off, the output becomes open.

That is, as shown in FIG. 3B, the high potential, the open state, and the low potential input are converted into the low potential, the high potential, and the open state and output.

As described in detail above, the present invention operates in ternary logic, and can be used in ternary logic system configuration because the input of one state is converted into another state and output.

Claims (1)

The input terminal Vi is commonly connected to the transistors Q2 and Q3 at the base, and the collector of the transistor Q1 biased to the resistors R1 and R2 is connected to the emitter side of the transistor Q2 and the transistor Q5. A common mirror is connected to the collector, and the transistor Q4 is biased by the resistors R5 and R6 to emitters of the transistor Q3 to form a current mirror with the transistor Q4, which is a current mirror transistor Q7. The collector of (Q8) is connected to the collector of the transistor (Q6) and the base of the transistor (Q11), respectively, and the collector of the transistor (Q9) forming a current mirror with the transistor (Q1) is connected to the current source (I) and the transistor ( And a common signal connected to the base of Q10 so that an output signal is applied to the collector connection points of the transistors Q10 and Q11.