JPH05291486A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPH05291486A
JPH05291486A JP8526992A JP8526992A JPH05291486A JP H05291486 A JPH05291486 A JP H05291486A JP 8526992 A JP8526992 A JP 8526992A JP 8526992 A JP8526992 A JP 8526992A JP H05291486 A JPH05291486 A JP H05291486A
Authority
JP
Japan
Prior art keywords
lead frame
resin
semiconductor device
package
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8526992A
Other languages
Japanese (ja)
Inventor
Akihiro Yaguchi
昭弘 矢口
Asao Nishimura
朝雄 西村
Makoto Kitano
誠 北野
Maya Obata
まや 小幡
Ryuji Kono
竜治 河野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8526992A priority Critical patent/JPH05291486A/en
Publication of JPH05291486A publication Critical patent/JPH05291486A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors

Abstract

PURPOSE:To prevent an external apparatus from being large-sized even upon mounting a plurality of semiconductor devices by electrically interconnecting electrodes of at least two LOC-structured semiconductor devices with a first lead frame, and joinning the first lead frame with a second lead frame. CONSTITUTION:Semiconductor devices 1, 1' are disposed oppositely in their circuit formation surfaces 1a, 1a'. Electrodes 2, 2' provided at the center of the circuit formation surfaces 1a, 1a' of the semiconductor devices 1, 1', and first lead frames 4, 4' are electrically interconnected through metal fine wires 5, 5'. The first lead frames 4, 4' are joinned with a second lead frame 6 at the ends of a package on the long sides of the same. Hereby, there can be mounted on a package two LOC semiconductor devices where an electrode is provided at the center thereof using a prior art technique. Further, there can be reduced the length of a portion of the semiconductor device where leads around the semiconductor device are fixed to resin.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、高集積化に適した樹脂
封止型半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device suitable for high integration.

【0002】[0002]

【従来の技術】従来より樹脂封止型半導体装置では、半
導体素子を素子搭載部であるタブの上に固定するととも
に、タブの周囲に複数のリードを配設し、半導体素子と
リードを金属細線によって電気的に接続して、その周囲
を樹脂で封止する構造が採用されている。
2. Description of the Related Art Conventionally, in a resin-encapsulated semiconductor device, a semiconductor element is fixed on a tab which is an element mounting portion, a plurality of leads are arranged around the tab, and the semiconductor element and the leads are formed of a fine metal wire. A structure is adopted in which the electrical connection is made and the periphery is sealed with resin.

【0003】近年、半導体装置の高集積化を達成するた
め、2個以上の半導体素子を搭載した半導体装置に対す
る要求が強くなっている。従来のようにタブ上に半導体
素子を固定した構造で、複数の半導体素子を搭載した構
造は、特開昭62−8529号公報,特開昭62−131555号公
報,特開昭62−119952号公報および特開昭63−124450号
公報に開示されたものがある。
In recent years, in order to achieve high integration of semiconductor devices, there is an increasing demand for semiconductor devices having two or more semiconductor elements mounted thereon. A conventional structure in which a semiconductor element is fixed on a tab and a plurality of semiconductor elements are mounted is disclosed in JP-A-62-8529, JP-A-62-131555, and JP-A-62-119952. JP-A-63-124450 and JP-A-63-124450.

【0004】[0004]

【発明が解決しようとする課題】上記従来技術は、それ
ぞれ以下に示すような課題があるため実用化には至って
いない。すなわち、特開昭62−8529号公報および特開昭
62−131555号公報に開示されているようなタブの両側に
半導体素子を搭載する構造では、片面の素子上の電極と
リードフレームを金属細線で接続した後に、反対面の金
属細線接続を行う必要がある。この構造では、最初に接
続した金属細線にダメージを与えないで反対側の金属細
線の接続を行うことが困難である。
The above-mentioned conventional techniques have not been put into practical use because they have the following problems, respectively. That is, JP-A-62-8529 and JP-A-
In the structure in which the semiconductor elements are mounted on both sides of the tab as disclosed in Japanese Patent Publication No. 62-131555, it is necessary to connect the electrodes on the element on one surface and the lead frame with the thin metal wires, and then connect the thin metal wires on the opposite surface. There is. In this structure, it is difficult to connect the metal thin wires on the opposite side without damaging the metal thin wires connected first.

【0005】特開昭63−124450号公報に開示されている
ような2段のリードフレームを樹脂封止する構造では、
通常用いられているトランスファモールドで量産的にこ
れを製造することが困難である。
In a structure in which a two-stage lead frame is resin-sealed as disclosed in Japanese Patent Laid-Open No. 63-124450,
It is difficult to mass-produce this with a commonly used transfer mold.

【0006】特開昭62−119952号公報に開示されている
ようなパッケージ内部でリードフレームどうしを接合し
て一つのパッケージを構成する構造では、樹脂封止の前
にリードフレームを成型することが困難であり、パッケ
ージが厚くなるため、高集積化の観点からはあまり意味
がない。
In the structure disclosed in JP-A-62-119952 in which the lead frames are joined together inside the package to form one package, the lead frame may be molded before the resin sealing. Since it is difficult and the package becomes thick, it is meaningless from the viewpoint of high integration.

【0007】さらに、従来技術で開示されているような
タブ上に半導体素子を固定する構造では、半導体装置の
外形寸法を一定のままで半導体素子の寸法を大形化して
いくと、リードを樹脂に固定する部分の長さが不足し、
リードに充分な固定強度を与えられないという問題が生
じる。
Further, in the structure in which the semiconductor element is fixed on the tab as disclosed in the prior art, when the size of the semiconductor element is increased while keeping the external dimension of the semiconductor device constant, the leads are made of resin. The length of the part fixed to is insufficient,
There is a problem that the leads cannot be given sufficient fixing strength.

【0008】また従来構造では、半導体素子側面の近傍
に配置されたリードと素子上の電極を金属細線により接
続するため、電極の位置が素子の周端部に限定される。
このため、特開昭61−241959号公報に開示されているよ
うなリードが半導体素子の回路形成面上まで延長された
パッケージ(以下、リード・オン・チップ構造、略して
LOC構造と称する。)で用いられる素子、すなわち、
電極が素子の中央付近に設けられた素子二個を一つのパ
ッケージに搭載する場合には用いることができない。
Further, in the conventional structure, the leads arranged in the vicinity of the side surface of the semiconductor element and the electrodes on the element are connected by the fine metal wires, so that the position of the electrode is limited to the peripheral end portion of the element.
For this reason, a package in which the leads as disclosed in JP-A-61-241959 are extended to the circuit forming surface of the semiconductor element (hereinafter referred to as a lead-on-chip structure, abbreviated as LOC structure). Elements used in
It cannot be used when two elements whose electrodes are provided near the center of the element are mounted in one package.

【0009】本発明の目的は、複数の半導体素子を半導
体装置内に搭載しても、半導体装置の外形寸法が大形化
せず、充分なリード固定強度が得られ、LOC構造の半
導体素子が搭載可能で、さらに量産性の良好なパッケー
ジ構造を提供することにある。
An object of the present invention is to provide a semiconductor element having a LOC structure, in which even when a plurality of semiconductor elements are mounted in a semiconductor device, the external dimensions of the semiconductor device do not become large, a sufficient lead fixing strength is obtained, and a LOC structure is obtained. The object is to provide a package structure that can be mounted and that has good mass productivity.

【0010】[0010]

【課題を解決するための手段】上記目的を達成するた
め、本発明は少なくとも2個のLOC構造の半導体素子
の電極と第一のリードフレームをそれぞれ電気的に接続
し、第一のリードフレームを第二のリードフレームに接
合した。
In order to achieve the above object, the present invention electrically connects at least two electrodes of a semiconductor element having a LOC structure and a first lead frame, and connects the first lead frame to each other. Bonded to the second leadframe.

【0011】本発明の樹脂封止型半導体装置は、少なく
とも二個のLOC構造半導体素子の回路形成面どうしが
対向するように半導体素子を配置し、各半導体素子の電
極を除く回路形成面上に絶縁部材を介して第一のリード
フレームを配設し、第一のリードフレームと半導体素子
の電極をそれぞれ、例えば、金属細線で電気的に接続
し、第一のリードフレームをそれぞれ第二のリードフレ
ームに接合し、これらの周囲を樹脂で封止してパッケー
ジを形成したものであり、以下のいずれかの構成を特徴
とする。
In the resin-encapsulated semiconductor device of the present invention, the semiconductor elements are arranged so that the circuit formation surfaces of at least two LOC structure semiconductor elements face each other, and the semiconductor elements are disposed on the circuit formation surface excluding the electrodes of each semiconductor element. The first lead frame is disposed via an insulating member, the first lead frame and the electrodes of the semiconductor element are electrically connected to each other, for example, by a thin metal wire, and the first lead frame is connected to the second lead. A package is formed by bonding it to a frame and sealing the periphery thereof with a resin, and is characterized by any of the following configurations.

【0012】(1)半導体素子の電極と金属細線などに
よって電気的に接続された第一のリードフレームを第二
のリードフレームに接合する。
(1) The first lead frame electrically connected to the electrode of the semiconductor element by a metal thin wire or the like is joined to the second lead frame.

【0013】(2)(1)において、第一のリードフレー
ムと第二のリードフレームを溶接により接合する。
(2) In (1), the first lead frame and the second lead frame are joined by welding.

【0014】(3)(1)において、第一のリードフレー
ムと第二のリードフレームをはんだにより接合する。
(3) In (1), the first lead frame and the second lead frame are joined by solder.

【0015】(4)(1)において、第一のリードフレー
ムの板厚を第二のリードフレームより薄くする。
(4) In (1), the plate thickness of the first lead frame is made thinner than that of the second lead frame.

【0016】(5)(1)において、第一のリードフレー
ムの板幅を第二のリードフレームより小さくする。
(5) In (1), the plate width of the first lead frame is made smaller than that of the second lead frame.

【0017】(6)(1)において、第一のリードフレー
ムと第二のリードフレームに使用する材料を変える。
(6) In (1), the materials used for the first lead frame and the second lead frame are changed.

【0018】[0018]

【作用】本発明による半導体装置のパッケージでは、半
導体素子の中央付近に電極が配置されたLOC構造の半
導体素子を用いても、一つのパッケージ内に2個以上の
半導体素子を搭載することができる。
In the package of the semiconductor device according to the present invention, two or more semiconductor elements can be mounted in one package even if the semiconductor element having the LOC structure in which the electrodes are arranged near the center of the semiconductor element is used. ..

【0019】また、LOC構造の半導体素子を用いるこ
とによって、半導体素子を半導体装置の外形近傍まで大
きくすることができ、高集積化が達成される。
Further, by using the semiconductor element having the LOC structure, the semiconductor element can be enlarged to the vicinity of the outer shape of the semiconductor device, and high integration can be achieved.

【0020】さらに、本発明によるパッケージは、LO
C構造パッケージの製造技術、レーザ溶接または抵抗溶
接による接合技術などの従来技術をそのまま適用できる
ため、量産性が良好である。
Further, the package according to the present invention has a LO
Since the conventional technology such as the manufacturing technology of the C structure package and the joining technology by laser welding or resistance welding can be applied as it is, mass productivity is good.

【0021】[0021]

【実施例】以下、本発明の一実施例を図1および図2に
よって説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

【0022】図1は本発明の一実施例である樹脂封止型
半導体装置の断面図である。図2は図1に示した樹脂封
止型半導体装置の第二リードフレームから下の部分を取
り除いた平面図である。本実施例では、半導体素子1,
1´は、その回路形成面1a,1a´どうしが対向する
ように配置されている。半導体素子1,1´の回路形成
面1a,1a´の電極2,2´を除く面に接着剤によっ
て絶縁部材3,3´が接合されており、同じく接着剤に
より、第一リードフレーム4,4´が絶縁部材3,3´
にそれぞれ接合されている。半導体素子1,1´の回路
形成面1a,1a´の中央部に設けられた電極2,2´
と第一リードフレーム4,4´は、金属細線5,5´に
よって電気的に接続されている。第一リードフレーム
4,4´は、それぞれ第二リードフレーム6にパッケー
ジの長辺側の端部で接合されている。これらの部材は封
止樹脂7により封止されている。
FIG. 1 is a sectional view of a resin-sealed semiconductor device which is an embodiment of the present invention. FIG. 2 is a plan view of the resin-encapsulated semiconductor device shown in FIG. 1 with the lower part removed from the second lead frame. In this embodiment, the semiconductor element 1,
1'is arranged so that the circuit forming surfaces 1a and 1a 'thereof face each other. The insulating members 3 and 3'are bonded to the surfaces of the semiconductor elements 1 and 1'excluding the electrodes 2 and 2'of the circuit forming surfaces 1a and 1a 'by an adhesive, and the first lead frame 4, 4'is an insulating member 3, 3 '
Are joined to each. Electrodes 2, 2'provided in the central portions of the circuit forming surfaces 1a, 1a 'of the semiconductor elements 1, 1'
The first lead frames 4 and 4'are electrically connected to each other by thin metal wires 5 and 5 '. The first lead frames 4 and 4'are joined to the second lead frame 6 at the ends of the long side of the package. These members are sealed with a sealing resin 7.

【0023】次に、本実施例に示した樹脂封止型半導体
装置の製造方法を説明する。半導体素子1,1´の回路
形成面1a,1´aに、両面に接着剤が塗布されている
絶縁部材3,3´を介して第一リードフレーム4,4´
を接着する。次に半導体素子1,1´の電極2,2´と
第一リードフレーム4,4´を金属細線5,5´によっ
てそれぞれ電気的に接続する。このように構成した二組
の部材をその回路形成面1a,1a´どうしを対向さ
せ、第一リードフレーム4,4´をそれぞれ第二リード
フレーム6に接合する。第一リードフレーム4,4´と
第二リードフレーム6の接合は、レーザ溶接,抵抗溶接
あるいははんだなどによって行う。第一リードフレーム
4,4´と第二リードフレーム6の接合後、第一リード
フレーム4,4´の接合部8,8´から外側の部分を切
断し、その後、これらを樹脂7で封止する。第二リード
フレーム6の一端は、パッケージの外側で所定の形状に
成型され、図1に示した半導体装置が得られる。
Next, a method of manufacturing the resin-sealed semiconductor device shown in this embodiment will be described. First lead frames 4, 4'via circuit-forming surfaces 1a, 1'a of semiconductor elements 1, 1'through insulating members 3, 3'having adhesives applied on both sides.
Glue. Next, the electrodes 2, 2'of the semiconductor elements 1, 1'and the first lead frames 4, 4'are electrically connected by the thin metal wires 5, 5 ', respectively. The two lead members 4 and 4 ′ are bonded to the second lead frame 6 with the circuit forming surfaces 1 a and 1 a ′ of the two sets of members thus configured facing each other. The first lead frame 4, 4'and the second lead frame 6 are joined by laser welding, resistance welding, soldering or the like. After joining the first lead frames 4, 4'and the second lead frame 6, the outer portions are cut off from the joining portions 8, 8'of the first lead frames 4, 4 ', and then these are sealed with a resin 7. To do. One end of the second lead frame 6 is molded into a predetermined shape outside the package, and the semiconductor device shown in FIG. 1 is obtained.

【0024】本実施例によれば、従来の技術を用いて中
央部に電極が設けられたLOC構造の半導体素子2個を
一つのパッケージに搭載することができる。また、半導
体素子周辺のリードを樹脂に固定する部分の長さを小さ
くすることができるので、限られた外形寸法のパッケー
ジの中により大きな半導体素子を搭載することができ、
半導体装置の高集積化が図れる。
According to the present embodiment, it is possible to mount two semiconductor elements having the LOC structure in which the electrodes are provided in the central portion in one package by using the conventional technique. In addition, since the length of the portion where the leads around the semiconductor element are fixed to the resin can be reduced, a larger semiconductor element can be mounted in a package with limited external dimensions,
High integration of a semiconductor device can be achieved.

【0025】絶縁部材3,3´は、エポキシ系樹脂,フ
ェノール樹脂,ポリイミド樹脂などから選択された一種
または複数の樹脂を主成分とし、これに必要に応じて無
機質フィラー、各種添加剤などを加えた材料を使用す
る。
The insulating members 3 and 3'mainly consist of one or a plurality of resins selected from epoxy resins, phenol resins, polyimide resins, etc., and inorganic fillers, various additives, etc. are added to them as necessary. Use the material.

【0026】第一リードフレーム4,4´および第二リ
ードフレーム6は、例えば、Fe−Ni合金(Fe−4
2Niなど)、Cu合金などで形成されている。
The first lead frames 4, 4'and the second lead frame 6 are made of, for example, Fe-Ni alloy (Fe-4).
2Ni, etc.), Cu alloy or the like.

【0027】金属細線5,5´にはアルミニウム(A
l)、金(Au)あるいは銅(Cu)などの細線を使用
する。
Aluminum (A
l), gold (Au) or copper (Cu) thin wires are used.

【0028】樹脂7には、フェノール系硬化剤,シリコ
ーンゴムおよびフィラーが添加されたエポキシ樹脂を使
用し、この他に難燃化剤,カップリング剤,着色剤など
が若干量添加されている。
The resin 7 is an epoxy resin to which a phenolic curing agent, silicone rubber and a filler are added, and a flame retardant, a coupling agent, a coloring agent and the like are added in a small amount.

【0029】第二リードフレーム6がパッケージの外部
に引き出されている方向は、図1および図2に示したよ
うな2方向に限定するものではなく、1方向あるいは3
方向以上であっても良い。さらに図では第二リードフレ
ーム6をパッケージの外部で下方に折り曲げ、その先端
をパッケージの下面まで曲げたJベンド型を例にとって
示してあるが、第二リードフレーム6は任意の方向,形
状に折り曲げても良いし、また折り曲げなくとも良い。
The direction in which the second lead frame 6 is pulled out of the package is not limited to the two directions shown in FIGS. 1 and 2, but may be one direction or three directions.
It may be more than the direction. Further, in the drawing, the J-bend type in which the second lead frame 6 is bent downward outside the package and the tip is bent to the lower surface of the package is shown as an example, but the second lead frame 6 is bent in an arbitrary direction and shape. It may or may not be bent.

【0030】図1に示した実施例では、第一リードフレ
ーム4,4´と第二リードフレーム6をパッケージの内
部で接合する例を示したが、図3に示すように、パッケ
ージの外側で第一リードフレーム4,4´と第二リード
フレーム6を接合したものでもよい。
In the embodiment shown in FIG. 1, the first lead frame 4, 4'and the second lead frame 6 are joined inside the package. However, as shown in FIG. The first lead frame 4, 4 ′ and the second lead frame 6 may be joined together.

【0031】また、図1および図3に示した実施例で
は、第一リードフレーム4,4´を、接合部8,8´か
ら外側部分で切断する例を示したが、図4に示すように
第一リードフレーム4,4´を切断せず、パッケージの
外側で第二リードフレーム6とともに成型してもよい。
In the embodiment shown in FIGS. 1 and 3, the first lead frames 4 and 4'are cut from the joint portions 8 and 8'at the outer portion, but as shown in FIG. Alternatively, the first lead frames 4 and 4'may be molded together with the second lead frame 6 outside the package without cutting.

【0032】また、図1に示した実施例では、第一リー
ドフレーム4,4´と第二リードフレーム6の板厚およ
び板幅を同一にした例を示したが、図5に示すように第
一リードフレーム4,4´の板厚を第二リードフレーム
6より薄くしてもよい。また、図6に示すように第一リ
ードフレーム4,4´の板幅を第二リードフレーム6よ
り小さくしたものでも良い。このように第一リードフレ
ーム4,4´の板厚あるいは板幅を第二リードフレーム
6より小さくすることによって、第一リードフレーム
4,4´と第二リードフレーム6の接合が容易に行な
え、接合と同時に第一リードフレーム4,4´を切断で
きる。
In the embodiment shown in FIG. 1, the first lead frame 4, 4'and the second lead frame 6 have the same plate thickness and plate width, but as shown in FIG. The plate thickness of the first lead frames 4 and 4 ′ may be thinner than that of the second lead frame 6. Further, as shown in FIG. 6, the plate width of the first lead frames 4 and 4'may be smaller than that of the second lead frame 6. By making the plate thickness or the plate width of the first lead frames 4 and 4 ′ smaller than that of the second lead frame 6 as described above, the first lead frames 4 and 4 ′ and the second lead frame 6 can be easily joined, The first lead frames 4, 4'can be cut at the same time as the joining.

【0033】さらに、第一リードフレーム4,4´と第
二リードフレーム6は同一の材料で構成しても、異なる
材料で構成してもよい。
Furthermore, the first lead frames 4, 4'and the second lead frame 6 may be made of the same material or different materials.

【0034】図7は本発明の他の実施例を示す樹脂封止
型半導体装置の断面図、図8は図7に示した樹脂封止型
半導体装置の第二リードフレーム6から下の部分を取り
除いた平面図である。本実施例では、半導体素子1,1
´は、その回路形成面1a,1a´どうしが対向するよ
うに配置されている。半導体素子1,1´の回路形成面
1a,1a´の電極2,2´を除く面に接着剤によって
絶縁部材3,3´が接合されており、同じく接着剤によ
り、第一リードフレーム4,4´が絶縁部材3,3´に
それぞれ接合されている。半導体素子1,1´の回路形
成面1a,1a´の短辺側端部に設けられた電極2,2
´と第一リードフレーム4,4´は、金属細線5,5´
によって電気的に接続されている。第一リードフレーム
4,4´は、それぞれ第二リードフレーム6にパッケー
ジの長辺側端部で接合されている。これらの部材は封止
樹脂7により封止される。
FIG. 7 is a sectional view of a resin-encapsulated semiconductor device showing another embodiment of the present invention, and FIG. 8 shows a portion below the second lead frame 6 of the resin-encapsulated semiconductor device shown in FIG. It is the removed top view. In this embodiment, the semiconductor elements 1, 1
′ Is arranged such that the circuit forming surfaces 1 a and 1 a ′ face each other. The insulating members 3 and 3'are bonded to the surfaces of the semiconductor elements 1 and 1'excluding the electrodes 2 and 2'of the circuit forming surfaces 1a and 1a 'by an adhesive, and the first lead frame 4, 4'is joined to the insulating members 3 and 3 ', respectively. Electrodes 2 and 2 provided on the short side edges of the circuit forming surfaces 1a and 1a 'of the semiconductor elements 1 and 1'
′ And the first lead frames 4, 4 ′ are thin metal wires 5, 5 ′
Are electrically connected by. The first lead frames 4 and 4'are respectively joined to the second lead frame 6 at the long side end portions of the package. These members are sealed with the sealing resin 7.

【0035】本実施例によれば、端部に電極が設けられ
たLOC構造の半導体素子2個を用いても、一つのパッ
ケージに搭載することができる。また、半導体素子周辺
のリードを樹脂に固定する部分の長さを小さくすること
ができるので、限られた外形寸法のパッケージの中によ
り大きな半導体素子を搭載することができ、半導体装置
の高集積化が図れる。
According to the present embodiment, even if two semiconductor elements having the LOC structure with electrodes provided at the ends are used, they can be mounted in one package. In addition, since the length of the portion where the leads around the semiconductor element are fixed to the resin can be reduced, it is possible to mount a larger semiconductor element in a package with limited external dimensions, and to increase the integration of the semiconductor device. Can be achieved.

【0036】[0036]

【発明の効果】本発明によれば、LOC構造の半導体素
子を用いることができるので、複数の半導体素子を半導
体装置内に搭載しても、半導体装置の外形寸法が大形化
せず、充分なリード固定強度が得られ、半導体装置の高
集積化が達成できる。
According to the present invention, since a semiconductor element having a LOC structure can be used, even if a plurality of semiconductor elements are mounted in a semiconductor device, the external dimensions of the semiconductor device do not become large and the semiconductor device is sufficiently large. It is possible to obtain various lead fixing strengths and achieve high integration of semiconductor devices.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す樹脂封止型半導体装置
の断面図。
FIG. 1 is a sectional view of a resin-encapsulated semiconductor device showing an embodiment of the present invention.

【図2】図1の電極の位置を示す平面図。FIG. 2 is a plan view showing the positions of electrodes in FIG.

【図3】図1の第一リードフレームと第二リードフレー
ムの他の接合方法を示す断面図。
FIG. 3 is a sectional view showing another joining method of the first lead frame and the second lead frame of FIG.

【図4】本発明の第二の実施例を示す樹脂封止型半導体
装置の断面図。
FIG. 4 is a sectional view of a resin-sealed semiconductor device showing a second embodiment of the present invention.

【図5】図1の第一リードフレームの板厚を、第二リー
ドフレームより薄くした例を示す断面図。
5 is a cross-sectional view showing an example in which the plate thickness of the first lead frame of FIG. 1 is thinner than that of the second lead frame.

【図6】図1の第一リードフレームの板幅を、第二リー
ドフレームより小さくした例を示す断面図。
6 is a cross-sectional view showing an example in which the plate width of the first lead frame of FIG. 1 is smaller than that of the second lead frame.

【図7】本発明の第三の実施例を示す樹脂封止型半導体
装置の断面図。
FIG. 7 is a sectional view of a resin-encapsulated semiconductor device showing a third embodiment of the present invention.

【図8】図7の電極の位置を示す平面図。FIG. 8 is a plan view showing the positions of the electrodes in FIG.

【符号の説明】[Explanation of symbols]

1,1´…半導体素子、1a,1a´…回路形成面、
2,2´…電極、3,3´…絶縁部材、4,4´…第一
リードフレーム、5,5´…金属細線、6…第二リード
フレーム、7…樹脂、8,8´…接合部。
1, 1 '... semiconductor element, 1a, 1a' ... circuit forming surface,
2, 2 '... electrode, 3, 3' ... insulating member, 4, 4 '... first lead frame, 5, 5' ... fine metal wire, 6 ... second lead frame, 7 ... resin, 8, 8 '... bonding Department.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 25/18 (72)発明者 小幡 まや 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内 (72)発明者 河野 竜治 茨城県土浦市神立町502番地 株式会社日 立製作所機械研究所内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical indication location H01L 25/18 (72) Inventor Maya Obata 502 Jinmachi-cho, Tsuchiura-shi, Ibaraki Hiritsu Seisakusho Co., Ltd. Inside the laboratory (72) Inventor Ryuji Kono 502 Kandamachi, Tsuchiura City, Ibaraki Prefecture

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】半導体素子と、リードの集合体から成るリ
ードフレームと前記半導体素子と前記リードフレームと
を電気的に接続する手段を設け、これらの周囲を樹脂で
封止してパッケージを形成した樹脂封止型半導体装置に
おいて、複数の前記半導体素子を用い、前記半導体素子
の回路形成面どうしが対向しており、それぞれの前記半
導体素子の回路形成面上の電極を除く部分の少なくとも
一部分に絶縁部材を接着し、前記絶縁部材上に第一のリ
ードフレームをそれぞれ配設し、前記第一のリードフレ
ームと前記半導体素子上の前記電極とをそれぞれ電気的
に接続し、前記第一のリードフレームをそれぞれ第二の
リードフレームに接合したことを特徴とする樹脂封止型
半導体装置。
1. A semiconductor element, a lead frame composed of an assembly of leads, means for electrically connecting the semiconductor element and the lead frame are provided, and the periphery thereof is sealed with a resin to form a package. In a resin-sealed semiconductor device, a plurality of semiconductor elements are used, circuit formation surfaces of the semiconductor elements are opposed to each other, and insulation is provided on at least a part of a portion of the respective semiconductor elements excluding electrodes on the circuit formation surface. A member is adhered, a first lead frame is arranged on the insulating member, and the first lead frame and the electrode on the semiconductor element are electrically connected to each other, and the first lead frame is formed. A resin-sealed semiconductor device, characterized in that each is bonded to a second lead frame.
【請求項2】請求項1において、前記半導体素子上の前
記電極と前記第一のリードフレームとを金属細線により
電気的に接続した樹脂封止型半導体装置。
2. The resin-encapsulated semiconductor device according to claim 1, wherein the electrode on the semiconductor element and the first lead frame are electrically connected by a thin metal wire.
【請求項3】請求項1において、前記第一のリードフレ
ームと前記第二のリードフレームを溶接により接合した
樹脂封止型半導体装置。
3. The resin-sealed semiconductor device according to claim 1, wherein the first lead frame and the second lead frame are joined by welding.
【請求項4】請求項1において、前記第一のリードフレ
ームと前記第二のリードフレームをはんだにより接合し
た樹脂封止型半導体装置。
4. The resin-sealed semiconductor device according to claim 1, wherein the first lead frame and the second lead frame are joined by solder.
【請求項5】請求項1において、前記第一のリードフレ
ームの板厚を前記第二のリードフレームより薄くした樹
脂封止型半導体装置。
5. The resin-sealed semiconductor device according to claim 1, wherein the first lead frame is thinner than the second lead frame.
【請求項6】請求項1において、前記第一のリードフレ
ームの板幅を前記第二のリードフレームより小さくした
樹脂封止型半導体装置。
6. The resin-sealed semiconductor device according to claim 1, wherein the plate width of the first lead frame is smaller than that of the second lead frame.
【請求項7】請求項1において、前記第一のリードフレ
ームと前記第二のリードフレームを異なる材料で構成し
た樹脂封止型半導体装置。
7. The resin-sealed semiconductor device according to claim 1, wherein the first lead frame and the second lead frame are made of different materials.
JP8526992A 1992-04-07 1992-04-07 Resin-sealed semiconductor device Pending JPH05291486A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8526992A JPH05291486A (en) 1992-04-07 1992-04-07 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8526992A JPH05291486A (en) 1992-04-07 1992-04-07 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH05291486A true JPH05291486A (en) 1993-11-05

Family

ID=13853854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8526992A Pending JPH05291486A (en) 1992-04-07 1992-04-07 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPH05291486A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6864566B2 (en) 2001-08-21 2005-03-08 Samsung Electronics Co., Ltd. Duel die package
DE19747105B4 (en) * 1996-12-27 2005-05-12 Lg Semicon Co. Ltd., Cheongju Component with stacked semiconductor chips

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19747105B4 (en) * 1996-12-27 2005-05-12 Lg Semicon Co. Ltd., Cheongju Component with stacked semiconductor chips
US6864566B2 (en) 2001-08-21 2005-03-08 Samsung Electronics Co., Ltd. Duel die package

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