JP2000049275A - Lead frame, semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance moldability of LOC. SOLUTION: The lead frame has two bus bar leads 2a for power supply or ground each provided with a plurality of protrusions 2e projecting oppositely to the inner lead 2b thereof. A semiconductor chip 1 is buried and sealed in a package body 3 of epoxy resin molded by transfer molding along with the plurality of inner leads 2b. Furthermore, outer leads 2c projecting from the package body 3 is bent into gull-wing shape.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technique, and more particularly to a technique effective when applied to improvement of moldability in a semiconductor device having a LOC (Lead On Chip) structure.

[0002]

2. Description of the Related Art The technology described below studies the present invention,
Upon completion, they were examined by the inventor, and the outline is as follows.

[0003] One of the surface mount semiconductor devices is a semiconductor device having a LOC structure (hereinafter simply referred to as LOC). In this LOC, an inner lead is arranged on a main surface of a semiconductor chip, that is, a circuit forming surface side via an insulating tape (joining material), and the inner lead and a bonding pad (surface electrode) of the semiconductor chip are connected to each other with an Au wire or the like. It is structured to be electrically connected by bonding wires.

The LOC has a structure that is effective when mounting a relatively large semiconductor chip while keeping the external size small.

[0005] Therefore, due to the unbalanced structure, the resin (resin) filling balance at the time of molding is poor, and it is difficult to ensure the moldability.

A LOC having a structure in which a plurality of inner leads are arranged on a main surface of a semiconductor chip on a circuit forming surface side via an insulating sheet is disclosed in, for example, Japanese Patent Application Laid-Open No. 61-218.
No. 139.

[0007]

However, in the LOC of the above-described technology, the semiconductor chip is reduced in size by the chip shrink while the external size is increased by increasing the number of pins. The problem is that the balance is poor, and as a result, it is becoming difficult to ensure moldability.

An object of the present invention is to provide a lead frame for LOC which improves moldability, a semiconductor device using the same, and a method of manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the lead frame of the present invention is used for a semiconductor device in which a plurality of inner leads are arranged on a circuit forming surface side of a semiconductor chip, and when the semiconductor device is assembled, bonding is performed on the inner leads. The inner lead is formed such that an end connected to a wire for use is arranged on an outer peripheral portion of the circuit forming surface of the semiconductor chip.

Further, in the semiconductor device according to the present invention, a plurality of inner leads are arranged on a circuit forming surface side of a semiconductor chip sealed in a package body, and the inner leads are connected to bonding wires in the inner leads. The end to be formed is arranged on an outer peripheral portion of the circuit forming surface of the semiconductor chip.

Accordingly, the wires connected to the ends of the inner leads by wire bonding are arranged on the outer peripheral portion of the circuit forming surface of the semiconductor chip.

Accordingly, obstacles to the resin flow at the time of molding at the central portion in the width direction of the circuit forming surface of the semiconductor chip are reduced, and the speed of the resin flow at the central portion on the circuit forming surface can be increased.

As a result, it is possible to reduce the difference in the resin filling time between the outer peripheral portion and the central portion on the circuit formation surface of the semiconductor chip, thereby improving the filling balance. In other words, the difference in the time of filling the resin at the time of molding between the outer peripheral portion and the central portion of the circuit forming surface can be reduced, thereby suppressing the appearance voids.

As a result, moldability in LOC can be improved.

Further, a method of manufacturing a semiconductor device according to the present invention
A step of preparing a lead frame having a plurality of inner leads having ends to which bonding wires are connected at the time of wire bonding, and a plurality of outer leads connected to the respective inner leads; A step of preparing a semiconductor chip on which a circuit is formed, and the inner lead and the circuit forming surface are opposed to each other, and the end of the inner lead is arranged on an outer peripheral portion of the circuit forming surface of the semiconductor chip. Bonding the end of the inner lead and the semiconductor chip via a bonding material, and electrically connecting a surface electrode of the semiconductor chip and the end of the inner lead by wire bonding, Molding the package body by resin sealing the semiconductor chip, and projecting from the package body. The serial outer leads and a step of separating from the lead frame.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a partial plan view showing an example of the structure of a lead frame according to Embodiment 1 of the present invention.
2 is an external perspective view showing an example of the structure of the semiconductor device according to the first embodiment of the present invention, FIG. 3 is a cross-sectional view showing an example of the structure of the semiconductor device shown in FIG. 2, and FIG. 4 is a semiconductor device shown in FIG. It is a partial perspective view which shows an example of the state of the resin flow in the molding process of the manufacturing method of FIG.

The semiconductor device according to the first embodiment is a kind of a surface mount type LSI (Large Scale Integration) package. As shown in FIG. 3, a main surface of a semiconductor chip 1 sealed in a package body 3 is provided. A resin-sealed LO in which a plurality of inner leads 2b are arranged on the circuit forming surface 1a side
It has the C structure and the external structure is shown in FIG.
As shown in the figure, the SOP is the same as the SOP (Small Outline Package).

The lead frame 2 of the first embodiment shown in FIG. 1 is a semiconductor device in which a plurality of inner leads 2b are arranged on the circuit forming surface 1a side of a semiconductor chip 1, that is, FIG.
A plurality of inner leads 2b extending in two opposing directions and a plurality of outer leads 2 connected to the respective inner leads 2b are used in the LOC 10 shown in FIG.
c, a power or ground bus bar lead 2a,
A dam bar 2f that supports each outer lead 2c and prevents the molding resin 6 (see FIG. 4) from flowing out of the mold during molding, and a frame 2d that supports each outer lead 2c. The bus bar lead 2a is formed with a protruding portion 2e protruding on the side opposite to the inner lead 2b side.

In the first embodiment, as shown in FIG. 1 or FIG. 4, a plurality of busbar leads 2a are provided at a position near the center on the opposite side of each inner lead 2b. Is provided.

However, it is sufficient that at least one protruding portion 2e is provided for each bus bar lead 2a at a position near the center opposite to the side of each inner lead 2b.

Further, the protrusion 2 according to the first embodiment
The shape of e is a quadrangle, but the shape is not limited to a quadrangle, and may be any shape as long as it protrudes from the bus bar lead 2a.

The lead frame 2 shown in FIG. 1 is made of, for example, Cu or an Fe-based alloy.
The frame area (the area surrounded by the frame portion 2d) shown in FIG. 1 is an area for one LOC 10 shown in FIG. 2, and is a multiple area where a plurality of the frame areas are connected.

Next, the structure of the LOC 10 (semiconductor device) according to the first embodiment shown in FIGS. 2 and 3 will be described.

The LOC 10 is manufactured using the lead frame 2 shown in FIG. 1, and a plurality of inner leads 2b are arranged on the circuit forming surface 1a side of the semiconductor chip 1 sealed in the package body 3. It was done. That is, the semiconductor chip 1 is embedded and sealed in a package body 3 made of epoxy resin molded by a transfer molding method or the like together with a plurality of inner leads 2b. It is bent into a shape.

Therefore, the LOC 10 according to the first embodiment
As shown in FIG. 4, has two busbar leads 2a for power supply or ground, and the busbar lead 2a is formed with a plurality of protruding portions 2e protruding on the side opposite to the inner leads 2b. .

That is, in the two bus bar leads 2a, a plurality of protruding portions are provided at positions near the center opposite to the respective inner leads 2b (the center 1c of the circuit forming surface 1a in the width direction of the semiconductor chip 1). 2e is provided.

In the case where the semiconductor chip 1 is square, the width direction is a direction parallel to two sides of the semiconductor chip 1 that are perpendicular to the two opposite sides of the semiconductor chip 1 traversed by the opposed inner leads 2b.

Therefore, by providing a plurality of protrusions 2e, the LOC 10 of the first embodiment has a reduced mold area near the central portion 1c on the circuit forming surface 1a in the width direction of the semiconductor chip 1. Of structure.

As shown in FIG. 3, the plurality of inner leads 2b extend on the main surface of the semiconductor chip 1 on which the semiconductor integrated circuit is formed, that is, on the circuit forming surface 1a. The semiconductor chip 1 is attached via an insulating tape 4 (joining material) made of a polyimide resin or the like adhered to an end.

That is, the semiconductor chip 1 is fixed to the inner lead 2b via the insulating tape 4.

The semiconductor chip 1 and the inner leads 2b
Is electrically connected to the bonding pads 1b (surface electrodes), which are connection terminals of the semiconductor chip 1, and the corresponding inner leads 2b by bonding wires 5 such as gold wires.

As shown in FIG. 4, the package body 3 is formed of a sealing resin 6 such as a thermosetting epoxy resin.

Next, the LOC 10 according to the first embodiment
A method for manufacturing a (semiconductor device) will be described.

First, a plurality of inner leads 2b and a plurality of outer leads 2c connected to the respective inner leads 2b.
FIG. 1 has a plurality of bus bar leads 2a for power supply or ground, and a plurality of protruding portions 2e protruding toward the center opposite to the inner leads 2b with respect to the two bus bar leads 2a. A lead frame 2 shown is prepared.

On the other hand, a semiconductor chip 1 having a semiconductor integrated circuit formed on a circuit forming surface 1a as a main surface is prepared.

Thereafter, the inner lead 2b and the circuit forming surface 1
a, and the protruding portion 2e of the bus bar lead 2a is arranged at the central portion 1c in the width direction (the inner lead extending direction 7) of the circuit forming surface 1a of the semiconductor chip 1 and further attached to the inner lead 2b. The inner lead 2b and the semiconductor chip 1 are joined via the insulating tape 4 as the joining material.

That is, the semiconductor chip 1 is fixed to the lead frame 2 via the insulating tape 4 shown in FIG. 3 attached to the inner lead 2b of the lead frame 2.

Thereafter, the circuit forming surface 1a of the semiconductor chip 1
The bonding pad 1e, which is a surface electrode provided on the semiconductor chip 1, is wire-bonded to the corresponding inner lead 2b using a wire 5 such as a gold wire, thereby forming the bonding pad 1e of the semiconductor chip 1 and the inner lead 2b. Are electrically connected.

Subsequently, the semiconductor chip 1 and the wires 5 are sealed with a sealing resin 6 such as an epoxy resin to form the package body 3.

At this time, the LOC 10 of the first embodiment is
As shown in FIG. 4, the bus bar leads 2a are provided with the protruding portions 2e, so that the circuit forming surface 1 of the semiconductor chip 1
a reduced mold area in the vicinity of the center 1c in the width direction of FIG.
The filling time of the resin 6 of c can be shortened.

Therefore, as shown in FIG. 4, when the resin 6 is supplied into a molding die (not shown) during molding,
On the circuit forming surface 1a of the semiconductor chip 1, the outer peripheral portion 1
The difference in filling time of the resin 6 between d and the central portion 1c can be reduced, and as a result, the filling balance can be improved.

That is, as shown in FIG. 4, the difference in the filling time when the resin 6 is supplied between the region A (the outer peripheral portion 1d) and the region B (the central portion 1c) can be reduced.

After the completion of the molding, the outer leads 2c protruding from the package body 3 are cut using a cutting mold (not shown) to separate the outer leads 2c including the package body 3 from the lead frame 2 and to cut the outer leads 2c. Is bent into a desired shape (gull wing shape in the first embodiment).

As a result, the LOC10 shown in FIGS.
Can be manufactured.

According to the lead frame 2 and the semiconductor device (LOC10) of Embodiment 1 and the method of manufacturing the same, the following operational effects can be obtained.

That is, the bus bar lead 2a has a plurality of protruding portions 2e protruding on the side opposite to the inner lead 2b side.
Is formed, it is possible to reduce the mold area near the central portion 1c in the width direction (the inner lead extending direction 7) on the circuit forming surface 1a of the semiconductor chip 1.

Thus, the central portion 1 on the circuit forming surface 1a is formed.
c, the filling time of the resin 6 can be shortened. As a result, the difference in the filling time of the resin 6 between the outer peripheral portion 1d and the central portion 1c in the width direction on the circuit forming surface 1a of the semiconductor chip 1 is reduced. And the filling balance can be improved.

Therefore, the outer peripheral portion 1d of the circuit forming surface 1a
The difference between the filling time of the resin 6 at the time of molding can be reduced between the central portion 1c and the center portion 1c, whereby the occurrence of appearance voids can be suppressed.

As a result, the moldability of the LOC 10 can be improved.

(Embodiment 2) FIG. 5 is a partial plan view showing an example of the structure of a lead frame according to Embodiment 2 of the present invention.
6 is an external perspective view showing an example of the structure of the semiconductor device according to the second embodiment of the present invention, FIG. 7 is a sectional view showing an example of the structure of the semiconductor device shown in FIG. 6, and FIG. 8 is a semiconductor device shown in FIG. It is a partial perspective view which shows an example of the state of the resin flow in the molding process of the manufacturing method of FIG.

The lead frame 2 shown in FIG. 5 is used for the LOC 20 shown in FIG. 6, which is a semiconductor device having a LOC structure, as in the first embodiment.
1 is different from the lead frame 2 (see FIG. 1) used in the LOC 10 in that it does not have the bus bar lead 2a shown in FIG.
20 is that the inner lead 2b is formed so that the end 2g of the inner lead 2b is arranged on the outer peripheral portion 1d of the circuit forming surface 1a of the semiconductor chip 1.

That is, the inner lead 2b of the lead frame 2 of the second embodiment shown in FIG. 5 is different from the inner lead 2b of the lead frame 2 of the first embodiment shown in FIG.
The inner lead 2b is shorter in length than the
The distance between the end portions 2g is formed long.

Thus, the lead frame 2 shown in FIG.
When assembling the LOC 20 by using the same, as shown in FIG. 7 or FIG. 8, each end 2 g of the plurality of inner leads 2 b is connected to the outer peripheral portion 1 of the circuit forming surface 1 a of the semiconductor chip 1.
d.

The lead frame 2 according to the second embodiment
Since other structures in are the same as those described in the first embodiment, the description thereof will not be repeated.

Next, the structure of LOC 20 (semiconductor device) according to the second embodiment shown in FIGS. 6 and 7 will be described.

The LOC 20 is manufactured using the lead frame 2 shown in FIG.
10 (see FIGS. 2 and 3), a plurality of inner leads 2b are arranged on the circuit forming surface 1a side of the semiconductor chip 1 sealed in the package body 3.

Since the LOC 20 according to the second embodiment is manufactured using the lead frame 2 shown in FIG. 5, as shown in FIG. 7 or FIG. The portion 2g is arranged on the outer peripheral portion 1d of the circuit forming surface 1a of the semiconductor chip 1.

Thus, the LOC 20 according to the second embodiment is
The wires 5 connected to the ends 2g of the inner leads 2b by wire bonding are arranged on the outer peripheral portion 1d of the circuit forming surface 1a of the semiconductor chip 1.

Therefore, the resin flow during molding (FIG. 8)
Of the semiconductor chip 1 in the width direction (the inner lead extending direction 7) of the semiconductor chip 1 with respect to the flow of the resin 6 shown in FIG.
The speed of the resin flow can be increased.

The other structure of the LOC 20 according to the second embodiment is the same as that of the LOC 20 according to the first embodiment.
Since it is the same as OC10, the overlapping description is omitted.

Next, a method of manufacturing the semiconductor device (LOC20) according to the second embodiment will be described.

First, a plurality of inner leads 2b and a plurality of outer leads 2c connected to the respective inner leads 2b are provided.
A lead frame 2 as shown in FIG. 5 is prepared, which has a length of each inner lead 2b and a long distance between the ends 2g of the opposed inner leads 2b.

On the other hand, a semiconductor chip 1 having a semiconductor integrated circuit formed on a circuit forming surface 1a as a main surface is prepared.

Thereafter, the inner leads 2b and the circuit forming surface 1a of the semiconductor chip 1 are opposed to each other, and the end 2g of each inner lead 2b is arranged on the outer peripheral portion 1d of the circuit forming surface 1a of the semiconductor chip 1. Further, as shown in FIG. 7, the inner lead 2b and the semiconductor chip 1 are joined via an insulating tape 4 which is a joining material attached to the inner lead 2b.

That is, the semiconductor chip 1 is fixed to the lead frame 2 via the insulating tape 4 shown in FIG. 7 attached to the inner lead 2b of the lead frame 2.

Thereafter, in the same manner as in the method of manufacturing the LOC 10 of the first embodiment, wire bonding is performed with the wire 5, and subsequently, the package is sealed with the resin 6 to form the package body 3.

At this time, the LOC 20 of the second embodiment
As shown in FIG. 8, the wires 5 connected to the ends 2g of the respective inner leads 2b are arranged on the outer peripheral portion 1d of the circuit forming surface 1a of the semiconductor chip 1.

Accordingly, obstacles at the central portion 1c in the width direction (inner lead extending direction 7) on the circuit forming surface 1a of the semiconductor chip 1 due to resin flow during molding are reduced, and the central portion 1c on the circuit forming surface 1a is reduced. The speed of the resin flow can be increased.

Thus, the outer peripheral portion 1d and the central portion 1c at the time of molding are formed on the circuit forming surface 1a of the semiconductor chip 1.
And the difference in the filling time of the resin 6 can be reduced.

That is, as shown in FIG. 8, the difference in the filling time when the resin 6 is supplied between the region A (the outer peripheral portion 1d) and the region B (the central portion 1c) can be reduced.

After completion of the molding, the outer leads 2c protruding from the package body 3 are cut using a cutting mold (not shown) to separate the outer leads 2c including the package body 3 from the lead frame 2 and to cut the outer leads 2c. Is bent into a desired shape (gull wing shape in the first embodiment).

The other manufacturing method of the LOC 20 according to the second embodiment is the same as that of the LOC 10 described in the second embodiment, and therefore, the description thereof will not be repeated.

According to the lead frame 2 and the semiconductor device (LOC20) of Embodiment 2 and the method of manufacturing the same, the following operation and effect can be obtained.

That is, since the end 2g of the inner lead 2b is arranged on the outer peripheral portion 1d of the circuit forming surface 1a of the semiconductor chip 1 in the LOC 20, the wire connected to the end 2g of the inner lead 2b by wire bonding. 5 are arranged on the outer peripheral portion 1d of the circuit forming surface 1a of the semiconductor chip 1.

Therefore, obstacles at the central portion 1c in the width direction (the inner lead extending direction 7) of the circuit forming surface 1a of the semiconductor chip 1 with respect to resin flow during molding are reduced, and the central portion 1c on the circuit forming surface 1a is reduced. The speed of resin flow can be increased.

As a result, the circuit forming surface 1 of the semiconductor chip 1
On a, the difference in the filling time of the resin 6 between the outer peripheral portion 1d and the central portion 1c can be reduced, whereby the filling balance can be improved.

That is, the difference between the filling time of the resin 6 at the time of molding can be reduced between the outer peripheral portion 1d and the central portion 1c of the circuit forming surface 1a, whereby the appearance void can be reduced as in the case of the first embodiment. Can be suppressed.

As a result, the moldability of the LOC 20 can be improved.

Although the invention made by the inventor has been specifically described based on the first and second embodiments of the present invention, the present invention is not limited to the first and second embodiments of the invention. It goes without saying that various changes can be made without departing from the gist of the invention.

For example, in the first and second embodiments, the case where the above-described means is applied to the structure of the lead frame 2 has been described as means for improving the moldability of the semiconductor device (LOC). As a modification of the means for improving the performance, a single LOC may be formed with a plurality of types of loop heights and loop shapes of the wire 5 at the time of wire bonding.

That is, when performing wire bonding in one semiconductor device (LOC), instead of one type of loop height or loop shape, a plurality of types of loop heights or types of loop shapes (for example, low loop Or a trapezoidal loop) or a combination of both to perform wire bonding.

At this time, it is desirable to change the loop height or loop shape of the wire 5 near the gate side or near the air vent side of the mold (not shown).

Therefore, in the semiconductor device (LOC), since the bonding wire 5 is wire-bonded with a plurality of types of loop heights and / or a plurality of types of loop shapes, a plurality of wire loop heights and wire loop shapes are provided. Therefore, on the circuit forming surface 1a of the semiconductor chip 1, it is possible to reduce obstacles in the height direction to the resin flow existing on the flow path of the resin 6.

As a result, the central portion 1 on the circuit forming surface 1a is
The speed of the resin flow of c can be increased.

As a result, the circuit forming surface 1 of the semiconductor chip 1
On a, the difference in the filling time of the resin 6 between the outer peripheral portion 1d and the central portion 1c can be reduced, and the filling balance can be improved.

That is, the difference between the filling time of the resin 6 at the time of molding can be reduced between the outer peripheral portion 1d and the central portion 1c of the circuit forming surface 1a, whereby the appearance void can be suppressed.

As a result, as in the first and second embodiments, the moldability of the semiconductor device (LOC) can be improved.

Further, in the first and second embodiments, the case where the external structure of the semiconductor device is the SOP has been described. Is SOJ (Small Ou
tline J-leaded Package) or TSOP (Thin Small Out)
line Package).

[0092]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). In the LOC, since the bus bar lead is formed with the protruding portion protruding on the side opposite to the inner lead side, it is possible to reduce the molding area at the center in the width direction on the circuit forming surface of the semiconductor chip. Thereby, the difference in the resin filling time between the outer peripheral portion and the central portion during molding on the circuit forming surface of the semiconductor chip can be reduced, and the filling balance can be improved. as a result,
The appearance void can be suppressed. This allows
The moldability of the LOC can be improved.

(2). Since the ends of the inner leads are arranged on the outer peripheral portion of the circuit forming surface of the semiconductor chip in the LOC, the wires on the inner lead side by wire bonding are arranged on the outer peripheral portion of the circuit forming surface of the semiconductor chip. Accordingly, obstacles to the resin flow at the time of molding at the central portion in the width direction on the circuit forming surface of the semiconductor chip are reduced, and the speed of the resin flow at the central portion on the circuit forming surface can be increased. As a result, it is possible to reduce the difference in the resin filling time between the outer peripheral portion and the central portion on the circuit forming surface of the semiconductor chip, thereby improving the filling balance. Therefore, occurrence of appearance voids can be suppressed. As a result, the moldability in LOC can be improved.

[Brief description of the drawings]

FIG. 1 is a partial plan view showing an example of a structure of a lead frame according to a first embodiment of the present invention.

FIG. 2 is an external perspective view illustrating an example of the structure of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a cross-sectional view illustrating an example of the structure of the semiconductor device illustrated in FIG.

FIG. 4 is a partial perspective view showing an example of a resin flow state in a molding step of the method for manufacturing the semiconductor device shown in FIG. 2;

FIG. 5 is a partial plan view showing one example of a structure of a lead frame according to a second embodiment of the present invention.

FIG. 6 is an external perspective view illustrating an example of a structure of a semiconductor device according to a second embodiment of the present invention;

7 is a cross-sectional view illustrating an example of the structure of the semiconductor device illustrated in FIG.

8 is a partial perspective view showing an example of a resin flow state in a molding step of the method for manufacturing the semiconductor device shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1a Circuit formation surface 1b Bonding pad (surface electrode) 1c Central part 1d Outer part 2 Lead frame 2a Bus bar lead 2b Inner lead 2c Outer lead 2d Frame part 2e Projection part 2f Dam bar 2g End part 3 Package body 4 Insulating tape ( Joining material) 5 wire 6 resin 7 inner lead extending direction 10 LOC (semiconductor device) 20 LOC (semiconductor device)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Atsushi Nakamura 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. 5-20-1 F-term in the Semiconductor Division, Hitachi, Ltd. (Reference) 4M109 AA01 BA01 CA21 FA01 5F044 AA01 AA19 AA20 JJ03 5F067 AA01 AB02 BA03 BB08 BE10 CC02 CC08 CD03 DE01 DF02

Claims (9)

[Claims] 1. A lead frame for use in a semiconductor device in which a plurality of inner leads are arranged on a circuit forming surface side of a semiconductor chip, wherein when the semiconductor device is assembled, an end of the inner lead is the semiconductor chip. Wherein the inner lead is formed so as to be arranged on an outer peripheral portion of the circuit forming surface. 2. A lead frame for use in a semiconductor device in which a plurality of inner leads are arranged on a circuit forming surface side of a semiconductor chip, the lead frame having a power or ground bus bar lead, wherein the bus bar lead is provided with the inner lead. A lead frame, wherein a protruding portion protruding on a side opposite to a lead side is formed. 3. A semiconductor device having a plurality of inner leads arranged on a circuit forming surface side of a semiconductor chip sealed in a package body, wherein an end of the inner lead is formed on the circuit forming surface of the semiconductor chip. A semiconductor device, wherein the semiconductor device is arranged on an outer peripheral portion of the semiconductor device. 4. A semiconductor device having a plurality of inner leads arranged on a circuit forming surface side of a semiconductor chip sealed in a package body, the semiconductor device having a bus bar lead for power supply or ground, wherein the bus bar lead is A semiconductor device, wherein a protruding portion protruding on a side opposite to the inner lead side is formed. 5. A semiconductor device having a plurality of inner leads arranged on a circuit forming surface side of a semiconductor chip sealed in a package body, wherein a surface electrode of the semiconductor chip and the inner leads are electrically connected. A semiconductor device having a bonding wire to be connected, wherein the wire is wire-bonded with a plurality of types of loop heights. 6. A semiconductor device having a plurality of inner leads arranged on a circuit forming surface side of a semiconductor chip sealed in a package body, wherein a surface electrode of the semiconductor chip and the inner leads are electrically connected. A semiconductor device having a bonding wire to be connected, wherein the wire is wire-bonded in a plurality of types of loop shapes. 7. A step of preparing a lead frame having a plurality of inner leads and a plurality of outer leads connected to the respective inner leads, and a step of preparing a semiconductor chip having a semiconductor integrated circuit formed on a circuit forming surface. The inner lead and the circuit forming surface are opposed to each other, and the end of the inner lead is arranged on the outer peripheral portion of the circuit forming surface of the semiconductor chip, and the inner lead and the semiconductor chip are connected via a bonding material. Bonding the surface electrodes of the semiconductor chip and the inner leads by wire bonding, forming the package body by resin-sealing the semiconductor chip, Separating the projecting outer lead from the lead frame. Method of manufacturing a conductor arrangement. 8. A plurality of inner leads, a plurality of outer leads connected to each of the inner leads, and a bus bar lead for power supply or ground, and the bus bar leads protrude to a side opposite to the inner lead side. A step of preparing a lead frame having a protrusion formed thereon; a step of preparing a semiconductor chip having a semiconductor integrated circuit formed on a circuit forming surface; and making the inner leads face the circuit forming surface and the bus bar leads. Disposing the protruding portion at a central portion in the width direction of the circuit forming surface of the semiconductor chip, and joining the inner lead and the semiconductor chip via a joining material; and Electrically connecting the inner lead to the inner lead by wire bonding; and encapsulating the semiconductor chip with a resin. The method of manufacturing a semiconductor device comprising the steps of forming a di-body, the said outer leads protruding from the package body to a step of separating from the lead frame. 9. A step of preparing a lead frame having a plurality of inner leads and a plurality of outer leads connected to the respective inner leads, and a step of preparing a semiconductor chip having a semiconductor integrated circuit formed on a circuit forming surface. A step of bonding the inner lead and the semiconductor chip via a bonding material with the inner lead and the circuit forming surface facing each other; and setting a plurality of types of loop heights with the surface electrode of the semiconductor chip and the inner lead. Forming a plurality of types of loop shapes or a plurality of types thereof and electrically connecting them by wire bonding; molding the semiconductor chip with a resin to form a package body; and forming the outer leads projecting from the package body. Separating the lead frame from the lead frame. Method.