JP2004087998A - Surface mounting semiconductor device and its fabricating process - Google Patents

Surface mounting semiconductor device and its fabricating process Download PDF

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Publication number
JP2004087998A
JP2004087998A JP2002249870A JP2002249870A JP2004087998A JP 2004087998 A JP2004087998 A JP 2004087998A JP 2002249870 A JP2002249870 A JP 2002249870A JP 2002249870 A JP2002249870 A JP 2002249870A JP 2004087998 A JP2004087998 A JP 2004087998A
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Prior art keywords
lead
package
semiconductor device
cut
exposed
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Wakichi Shiobara
塩原　　和吉
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Fuji Electric Co Ltd
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Fuji Electric Holdings Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To enhance a solder bonding strength in a mounted state on a board through improving a lead cut surface exposed in a peripheral side surface of a package targeting a surface mounting semiconductor device to be made into a QFN, a SON or the like. <P>SOLUTION: There is provided the surface mounting semiconductor device in which a semiconductor chip 1 is mounted on a tab 2 of a lead frame and is sealed with a resin after a wire 4 is bonded between the leads 3 arranged in a periphery of the chip. In the surface mounting semiconductor device, an undersurface of an outer lead 3a is exposed in a mounting side of the package and then in leads whose apical ends have been cut along an outer circumference of the resin-sealed portion 5, the apical ends exposed in the peripheral side surface of the package are cut slantwise at an inclination angle &theta; (90&deg;&gt;&theta;&gt;30&deg;), so that solder bonding areas of lead cut surfaces 3a are enlarged to enhance the solder bonding strength between the substrate 6 and the leads and concurrently thermal stress applied to a fillet 7a is reduced, improving reliability of lead junctions. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、ＱＦＮ（Ｑｕａｄ　Ｆｌａｔ　Ｎｏｎ−ｌｅａｄｅｄ　Ｐａｃｋａｇｅ），ＳＯＮ　（Ｓｍａｌｌ　Ｏｕｔｌｉｎｅ　Ｎｏｎ−ｌｅａｄｅｄ　Ｐａｃｋａｇｅ）　などのパッケージタイプを対象に、リードフレームを用いて組立てた表面実装型半導体装置，　およびその製造方法に関する。
【０００２】
【従来の技術】
リードフレームを使用して組立てた従来の表面実装型半導体装置では、ガルウイング形と呼ばれる端子形状が一般的であったが、近年ではパッケージの小型化，　実装面積の縮小化を目的に頭記したＱＦＮ，　ＳＯＮのパッケージ構造が多く採用される傾向にある。
【０００３】
ここで、ＱＦＮは、モールド成形により樹脂封止したパッケージの裏面側周域に外部接続端子となるリードを露出させた構成になり、前記リードを実装面に重ね合わせて回路基板にはんだ接合するようにしており、その従来例の構造を図７〜図９に示す。
各図において、１はＩＣなどの半導体チップ、２は半導体チップ１をマウントしたリードフレームのタブ、２ａはタブ２の四隅から外方に引出した吊りリード、３はタブ２の周囲に分散して配列したリード、４は半導体チップ１の表面電極１ａとリード４との間に配線したボンディングワイヤ、５はパッケージの樹脂封止部である。
【０００４】
ここで、リードフレーム３は、そのアウターリード部３ａの底面を樹脂封止部５の底面側に露出させ、かつそのリード先端はパッケージの外郭に合わせてリードカットしてその先端面をパッケージの外周側面に露出させている。なお、このリードカットは、半導体チップをタブにマウントしたリードフレームをトランスファー成形により樹脂封止した状態で、ダイシング装置によりパッケージの外形に合わせて樹脂封止部と一緒にリードを切断するようにしている。なお、前記のリードフレームは、例えば厚み０．１〜０．２ｍｍ程度の銅系，あるいはその合金系材料で作られ、また封止樹脂にはエポキシ樹脂などのの熱硬化性樹脂を用いている。
【０００５】
そして、この半導体装置の製品を回路基板に実装する際には、図９で示すように回路基板６に形成した導体パターンのはんだ付けランド６ａの上に前記リード３のアウターリード部３ａの露出面を重ね合わせ、この状態でフローないしリフロー法によりはんだ接合する。なお、図９において、７ははんだ接合部，７ａははんだフィレットを表している。
【０００６】
【発明が解決しようとする課題】
ところで、前記したＱＦＮ，　ＳＯＮなどのノンリード・パッケージ構造になる表面実装型半導体装置は、パッケージの小型化および実装面積の縮小化が図れる利点がある反面、回路基板に実装する際に、リードのはんだ付け面積がガルウイング形リードと比べて小さく、このためにはんだ接合強度が小さくなる。
【０００７】
さらに、図９に示したはんだ接合部７のはんだフィレット７ａに着目すると、次記のような問題点がある。すなわち、従来構造では樹脂封止部５の周側面に露出しているリード３の先端は垂直にリードカットされていることから、この部分に形成されたはんだフィレット７ａとリード３との境界面がエッジ状を呈することになる。このために、はんだフィレット７ａの前記エッジ部分には温度サイクルにより熱応力が繰り返し加わり、これによる疲労が原因ではんだ接合部７にはんだの亀裂，剥がれなどが発生し易くなって寿命，信頼性が低下する。
【０００８】
本発明は上記の点に鑑みなされたものであり、ＱＦＮ，　ＳＯＮなどのパッケージタイプを対象に、パッケージの周側面に露出したリードのカット面を変えることにより、はんだ接合面積の増加と併せて、そのはんだフィレットに加わる熱応力の集中を緩和させて高いはんだ接合強度と信頼性が確保できるように改良した表面実装型半導体装置、およびその製造方法を提供することを目的とする。
【０００９】
【課題を解決するための手段】
上記目的を達成するために、本発明によれば、タブの周域にリードを分散配列したリードフレームを用い、前記タブに半導体チップをマウントし、半導体チップとリードとの間をワイヤボンディングした上でその周域を樹脂封止したパッケージ構造になる表面実装型半導体装置であって、前記リードはそのアウターリード部の底面をパッケージの実装面側に露出させ、かつリード先端をパッケージの外郭に沿わせてカットしたものにおいて、
パッケージの周側面に露出した前記リードの先端を底面に対して鋭角に斜めカットするものとする（請求項１）。
【００１０】
上記構成によれば、パッケージの周面に露出したリード先端の切断面は、リード先端を垂直にリードカットした従来構造と比べて斜めカットした分だけ面積が広がってはんだの接合面積が拡大するとともに、このリード先端の傾斜面に沿って形成されるはんだフィレットの接合面角度が鈍角になる。これにより、はんだ接合面積が拡大した分だけはんだ接合強度が増すほか、熱サイクルに伴ってはんだフィレットに加わる熱応力の集中が緩和されて亀裂の発生を抑えることができて信頼性の向上化が図れる。
【００１１】
また、前記したリード先端のカット面は、本発明により次記の製造方法によって形成することができる。すなわち、リードフレームに半導体チップをマウントして樹脂封止した状態で行うリードカット工程で、パッケージの外形に合わせてリードを樹脂封止部と共に斜めカットする（請求項２）。
【００１２】
【発明の実施の形態】
以下、本発明の実施の形態を図１〜図６に示す実施例に基づいて説明する。なお、実施例の図中で図７〜９に対応する部材には同じ符号を付してその説明は省略する。
すなわち、図示実施例の表面実装型半導体装置は、図７に示した従来構造と基本的に同じであるが、パッケージの周縁に配列して引出したリード３について、樹脂封止部５の周側面に露出したアウターリード部３ａの先端（リードカット面）を図示のようにパッケージの底面に対して角度θ（９０°＞θ＞３０°）に斜めにカットしてリードカット面３ａ−１を形成している。
【００１３】
ここで、図１（ａ），（ｂ）　および図２（ａ）　〜（ｃ）　に示す実施例では、前記したリードカット面３ａ−１の傾斜角度θに合わせて樹脂封止部５の外周側面が傾斜している。また、図３（ａ）　〜（ｃ）　および図４に示す実施例では、リード３のアウターリード部３ａが樹脂封止部５の周面から側方に若干突き出して露出しており、このアウターリード部３ａの先端を前記と同様に傾斜角度θにカットしてリードカット面３ａ−１を形成している。
【００１４】
上記の構成によれば、樹脂封止部５の外周側面に露出しているアウターリード部３ａの先端が斜めカットされているので、そのリードカット面３ａ−１は図９に示した従来の垂直カット面と比べてパッケージの外周面に露出する面積が拡大する。したがって、当該半導体装置を回路基板６に実装するに際して、アウターリード部３ａと回路基板６のランド６ａとの間をはんだ接合すると、図１（ｂ）　で表すようにはんだフィレット７ａが前記のリードカット面３ａ−１を覆って容易に形成されることになる。しかも、このはんだフィレット７ａは図９の従来例と比べると判るようにカット面が傾斜している分だけはんだ接合面積が拡大しており、これにより接合強度が増す。また、リードカット面３ａ−１に沿って形成されたはんだフィレット７ａはリードとの境界面が図９のようにエッジ状を呈することがないので、温度サイクルに伴う熱応力の集中が緩和されてこの部分に亀裂が発生するのを効果的に抑制できる。
【００１５】
次に、図１の半導体装置を対象に、その樹脂パッケージおよびその周面に配列したリードの先端を斜めカットする製造方法を図５，図６で説明する。図は帯状に連なったリードフレームのタブ２に半導体チップ１をマウントし、この半導体チップ１とタブ２の周囲に配列したリード３との間にワイヤ４をボンディングした上で、その周域をトランスファー成形法により樹脂封止した状態で、ダイシング装置のダイシングブレード８を使って半導体装置を個別に切断する製造工程を表している。なお、切断前の状態では、図示のように隣り合う半導体装置のリード３（リードフレームの長手方向に並ぶリード）の間が連なっていて、タイバー（図示せず）を介してリードフレームのサイドレールに連結されており、さらに樹脂封止部５が隣り合う半導体装置の領域の間を連ねるよう一体にモールド成形されている。
【００１６】
ここで、半導体装置の切断に使用するダイシング装置のダイシングブレード８は、図示のようにその刃先の断面形状がＶ字形（角度α）である。そして、このダイシングブレード８を半導体装置のパッケージ外形に沿って移動操作しながら、樹脂封止部５およびリード３を一緒に切断する。これにより、図１（ｂ）　で示すようにパッケージの外周側面およびリード３が傾斜角θに切断される。
【００１７】
また、この場合に図５に示す方法では、ダイシングブレード８を垂直姿勢に立てて切断するようにしており、この場合にはダイシングブレード８の刃先角度αを前記の切断角度θに対応して設定している。一方、図６の方法では、ダイシングブレード８自身を傾けて切断するようにしている。この方法によれば、ダイシングブレード８の刃先角度αの制約を受けずに樹脂封止部５およびリード３を任意の傾斜角度θで切断できる。
【００１８】
なお、図３，図４の実施例では、連続したリードフレーム上で組立てた各半導体装置の領域ごとにそのパッケージ外形に合わせて個別に樹脂封止した後、続くリードカット工程でパッケージの外周側面に突き出しているリード３を例えば図５に示したダイシングブレード８を用いて斜め角度θにリードカットする。
【００１９】
【発明の効果】
以上述べたように、本発明によれば、タブの周域にリードを配列したリードフレームを用い、前記タブに半導体チップをマウントし、半導体チップとリードとの間をワイヤボンディングした上でその周域を樹脂封止したパッケージ構造になる表面実装型半導体装置であって、前記リードはそのアウターリード部の底面をパッケージの実装面側に露出させ、かつリード先端をパッケージの輪郭に沿わせてカットしたものにおいて、パッケージの周側面に露出した前記リードの先端を底面に対して鋭角に斜めカットしたことにより、
当該半導体装置を回路基板にはだ付けして実装する際に、そのはんだ接合部にはんだフィレットが容易に形成されるとともに、リード先端を斜めカットしたことではんだ接合面積が拡大してはんだ接合強度が向上する。さらに加えて、半導体装置の実使用時の熱サイクルに伴っけはんだフィレットに加わる熱応力が緩和されるなど、半導体装置の実装性，リード接合部の信頼性向上が図れる。
【図面の簡単な説明】
【図１】本発明の実施例による表面実装型半導体装置を回路基板に実装した状態図で、（ａ）　は半導体装置の内部構造を表す断面図、（ｂ）　は（ａ）　の要部拡大図
【図２】図１の半導体装置のパッケージ外形図で、（ａ），（ｂ），（ｃ）　はそれぞれ上面図，裏面図，および側面図
【図３】図２と異なる実施例のパッケージ外形図で、（ａ），（ｂ），（ｃ）　はそれぞれ上面図，裏面図，および側面図
【図４】図３の半導体装置を回路基板に実装した状態を表す断面図
【図５】図１の半導体装置に適用してパッケージおよびリードを切断する製造方法の説明図
【図６】図５と異なる製造方法の説明図
【図７】本発明の実施対象となる半導体装置の内部構造を表す平面図
【図８】図７の半導体装置に対する従来のパッケージ外形図で、（ａ），（ｂ），（ｃ）　はそれぞれ上面図，裏面図，および側面図
【図９】図８の半導体装置を回路基板に実装した状態を表す要部の拡大断面図
【符号の説明】
１　　半導体チップ
２　　リードフレームのタブ
３　　リード
３ａ　アウターリード部
３ａ−１　リードカット面
４　　ボンディングワイヤ
５　　樹脂封止部
６　　回路基板
６ａ　はんだ付けランド
７　　はんだ接合部
７ａ　はんだフィレット
８　　ダイシングブレード
θ　　リードカット面の傾斜角度[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a surface mount type semiconductor device assembled using a lead frame for a package type such as QFN (Quad Flat Non-Leaded Package) and SON (Small Outline Non-Leaded Package), and a manufacturing method thereof.
[0002]
[Prior art]
In a conventional surface mount type semiconductor device assembled using a lead frame, a terminal shape called a gull wing type is generally used. In recent years, however, QFNs have been mentioned for the purpose of downsizing a package and reducing a mounting area. , SON package structures tend to be adopted more often.
[0003]
Here, the QFN has a configuration in which a lead serving as an external connection terminal is exposed in a peripheral area on the back surface side of a package sealed with resin by molding, and the lead is overlapped on a mounting surface and soldered to a circuit board. FIGS. 7 to 9 show the structure of the conventional example.
In each of the figures, 1 is a semiconductor chip such as an IC, 2 is a tab of a lead frame on which the semiconductor chip 1 is mounted, 2a is a suspension lead extending outward from four corners of the tab 2, and 3 is dispersed around the tab 2. The arranged leads 4 are bonding wires arranged between the surface electrodes 1a of the semiconductor chip 1 and the leads 4, and 5 is a resin sealing portion of the package.
[0004]
Here, in the lead frame 3, the bottom surface of the outer lead portion 3a is exposed to the bottom surface side of the resin sealing portion 5, and the leading end of the lead is cut in accordance with the outer periphery of the package, and the leading end surface is formed on the outer periphery of the package. It is exposed on the side. In this lead cut, the lead frame with the semiconductor chip mounted on the tab is resin-sealed by transfer molding, and the dicing device is used to cut the leads together with the resin sealing part according to the outer shape of the package. I have. The lead frame is made of, for example, a copper-based material or an alloy-based material having a thickness of about 0.1 to 0.2 mm, and a thermosetting resin such as an epoxy resin is used as a sealing resin. .
[0005]
When this semiconductor device product is mounted on a circuit board, the exposed surface of the outer lead portion 3a of the lead 3 is placed on the soldering land 6a of the conductor pattern formed on the circuit board 6 as shown in FIG. Are superimposed and soldered by a flow or reflow method in this state. In FIG. 9, reference numeral 7 denotes a solder joint, and 7a denotes a solder fillet.
[0006]
[Problems to be solved by the invention]
By the way, the surface mount type semiconductor device having a non-leaded package structure such as the above-mentioned QFN and SON has an advantage that the package can be reduced in size and the mounting area can be reduced. The mounting area is smaller than that of the gull-wing type lead, and therefore the solder joint strength is reduced.
[0007]
Further, when attention is paid to the solder fillet 7a of the solder joint portion 7 shown in FIG. 9, there are the following problems. That is, in the conventional structure, since the tip of the lead 3 exposed on the peripheral side surface of the resin sealing portion 5 is vertically cut, the boundary surface between the solder fillet 7a formed at this portion and the lead 3 is formed. It will have an edge shape. For this reason, thermal stress is repeatedly applied to the edge portion of the solder fillet 7a by a temperature cycle, and due to the fatigue, solder cracks and peeling are likely to occur in the solder joint portion 7, so that the life and reliability are reduced. descend.
[0008]
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is intended for package types such as QFN and SON, and by changing a cut surface of a lead exposed on a peripheral side surface of a package, together with an increase in a solder joint area, It is an object of the present invention to provide a surface-mounted semiconductor device improved so that the concentration of thermal stress applied to the solder fillet is reduced to ensure high solder joint strength and reliability, and a method of manufacturing the same.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, a semiconductor device is mounted on a tab using a lead frame in which leads are dispersed and arranged around a tab, and wire bonding is performed between the semiconductor chip and the lead. A surface mounting type semiconductor device having a package structure in which a peripheral area thereof is sealed with a resin, wherein the leads expose a bottom surface of an outer lead portion to a package mounting surface side, and a tip of the lead extends along an outer periphery of the package. In what was cut
The tip of the lead exposed on the peripheral side surface of the package is obliquely cut at an acute angle with respect to the bottom surface.
[0010]
According to the above configuration, the cut surface of the tip of the lead exposed on the peripheral surface of the package is enlarged by an amount corresponding to the oblique cut as compared with the conventional structure in which the tip of the lead is vertically cut, so that the solder bonding area is increased. Then, the joining surface angle of the solder fillet formed along the inclined surface of the lead tip becomes obtuse. As a result, the solder joint strength is increased by the increased solder joint area, and the concentration of thermal stress applied to the solder fillet due to thermal cycling is reduced, cracks can be suppressed and reliability is improved. I can do it.
[0011]
Further, the cut surface of the lead tip described above can be formed by the following manufacturing method according to the present invention. That is, in a lead cutting step performed in a state where the semiconductor chip is mounted on the lead frame and sealed with resin, the leads are cut obliquely together with the resin sealing portion in accordance with the outer shape of the package.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the examples shown in FIGS. In the drawings of the embodiment, members corresponding to FIGS. 7 to 9 are denoted by the same reference numerals, and description thereof will be omitted.
That is, the surface-mount type semiconductor device of the illustrated embodiment is basically the same as the conventional structure shown in FIG. As shown, the tip (lead cut surface) of the outer lead portion 3a that is exposed at an angle is cut obliquely to the bottom surface of the package at an angle θ (90 °>θ> 30 °) to form a lead cut surface 3a-1. are doing.
[0013]
Here, in the embodiment shown in FIGS. 1 (a) and 1 (b) and FIGS. 2 (a) to 2 (c), the outer periphery of the resin sealing portion 5 is adjusted to the inclination angle θ of the lead cut surface 3a-1. The sides are inclined. Further, in the embodiment shown in FIGS. 3A to 3C and FIG. 4, the outer lead portion 3a of the lead 3 slightly projects laterally from the peripheral surface of the resin sealing portion 5 and is exposed. The leading end of the lead portion 3a is cut at an inclination angle θ in the same manner as described above to form a lead cut surface 3a-1.
[0014]
According to the above configuration, the tip of the outer lead portion 3a exposed on the outer peripheral side surface of the resin sealing portion 5 is obliquely cut, so that the lead cut surface 3a-1 has the conventional vertical cut surface shown in FIG. The area exposed on the outer peripheral surface of the package is larger than the cut surface. Therefore, when the semiconductor device is mounted on the circuit board 6, when the outer lead portion 3a and the land 6a of the circuit board 6 are joined by solder, the solder fillet 7a is cut by the lead cut as shown in FIG. It will be easily formed covering the surface 3a-1. Moreover, as can be seen from the conventional example in FIG. 9, the solder fillet 7a has an increased solder joint area by the slant cut surface, thereby increasing the joint strength. Further, since the solder fillet 7a formed along the lead cut surface 3a-1 does not exhibit an edge shape at the boundary surface with the lead as shown in FIG. 9, the concentration of thermal stress due to the temperature cycle is reduced. The generation of cracks in this portion can be effectively suppressed.
[0015]
Next, with reference to FIGS. 5 and 6, a description will be given of a method of manufacturing the semiconductor device of FIG. In the figure, a semiconductor chip 1 is mounted on a tab 2 of a lead frame connected in a strip shape, a wire 4 is bonded between the semiconductor chip 1 and a lead 3 arranged around the tab 2, and the peripheral area is transferred. A manufacturing process is shown in which semiconductor devices are individually cut using a dicing blade 8 of a dicing device in a state where the resin is sealed by a molding method. In the state before cutting, the leads 3 of adjacent semiconductor devices (leads arranged in the longitudinal direction of the lead frame) are continuous as shown in the figure, and the side rails of the lead frame are connected via tie bars (not shown). , And the resin sealing portion 5 is integrally molded so as to connect between adjacent regions of the semiconductor device.
[0016]
Here, the dicing blade 8 of the dicing apparatus used for cutting the semiconductor device has a V-shaped cross section (angle α) as shown in the figure. Then, while moving the dicing blade 8 along the outer shape of the package of the semiconductor device, the resin sealing portion 5 and the lead 3 are cut together. Thereby, as shown in FIG. 1B, the outer peripheral side surface of the package and the leads 3 are cut at an inclination angle θ.
[0017]
Further, in this case, in the method shown in FIG. 5, the dicing blade 8 is cut in a vertical posture, and in this case, the cutting edge angle α of the dicing blade 8 is set in accordance with the cutting angle θ. are doing. On the other hand, in the method shown in FIG. 6, the dicing blade 8 itself is inclined and cut. According to this method, the resin sealing portion 5 and the lead 3 can be cut at an arbitrary inclination angle θ without being restricted by the cutting edge angle α of the dicing blade 8.
[0018]
In the embodiment shown in FIGS. 3 and 4, each of the regions of each semiconductor device assembled on a continuous lead frame is individually resin-sealed in accordance with the outer shape of the package, and then the outer peripheral side surface of the package is subjected to a lead cutting step. The lead 3 projecting at a slant angle θ is cut at an oblique angle θ by using, for example, a dicing blade 8 shown in FIG.
[0019]
【The invention's effect】
As described above, according to the present invention, a semiconductor chip is mounted on the tab using a lead frame in which leads are arranged around the tab, and the semiconductor chip and the lead are wire-bonded to each other. A surface-mount type semiconductor device having a package structure in which a region is sealed with a resin, wherein the lead has a bottom surface of an outer lead portion exposed to a package mounting surface side, and a tip of the lead is cut along a contour of the package. By cutting the tip of the lead exposed on the peripheral side surface of the package at an acute angle with respect to the bottom surface,
When the semiconductor device is soldered to a circuit board and mounted, solder fillets are easily formed at the solder joints, and the diagonal cut of the tip of the lead increases the solder joint area and increases the solder joint strength. Is improved. In addition, it is possible to improve the mountability of the semiconductor device and the reliability of the lead joint, for example, by reducing the thermal stress applied to the solder fillet due to the thermal cycle during actual use of the semiconductor device.
[Brief description of the drawings]
FIGS. 1A and 1B are diagrams showing a state in which a surface-mount type semiconductor device according to an embodiment of the present invention is mounted on a circuit board, wherein FIG. 1A is a sectional view showing the internal structure of the semiconductor device, and FIG. FIG. 2 is an external view of the package of the semiconductor device of FIG. 1, wherein (a), (b), and (c) are a top view, a back view, and a side view, respectively. FIG. In the external view, (a), (b), and (c) are a top view, a back view, and a side view, respectively. FIG. 4 is a cross-sectional view showing a state where the semiconductor device of FIG. 3 is mounted on a circuit board. FIG. 6 is an explanatory view of a manufacturing method applied to the semiconductor device of FIG. 1 for cutting a package and a lead. FIG. 6 is an explanatory view of a manufacturing method different from FIG. 5. FIG. 7 is an internal structure of a semiconductor device to which the present invention is applied. FIG. 8 is an outline view of a conventional package for the semiconductor device of FIG. , (B), (c), respectively top view, rear view and a side view and FIG. 9 is an enlarged sectional view of a main portion indicating a condition mounted on the circuit board of the semiconductor device in FIG. 8 [REFERENCE NUMERALS]
DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Lead frame tab 3 Lead 3a Outer lead part 3a-1 Lead cut surface 4 Bonding wire 5 Resin sealing part 6 Circuit board 6a Soldering land 7 Solder joint part 7a Solder fillet 8 Dicing blade θ Lead cut surface Tilt angle

Claims (2)

タブの周域にリードを配列したリードフレームを用い、前記タブに半導体チップをマウントし、半導体チップとリードとの間をワイヤボンディングした上でその周域を樹脂封止したパッケージ構造になる表面実装型半導体装置であって、前記リードはそのアウターリード部の底面をパッケージの実装面側に露出させ、かつリード先端をパッケージの外郭に沿わせてカットしたものにおいて、
パッケージの周側面に露出した前記リードの先端を底面に対して鋭角に斜めカットしたことを特徴とする表面実装型半導体装置。A semiconductor chip is mounted on the tab using a lead frame in which leads are arranged in the peripheral area of the tab, and wire bonding is performed between the semiconductor chip and the lead. A semiconductor device, wherein the lead has a bottom surface of an outer lead portion exposed on a mounting surface side of a package, and a tip of the lead is cut along a contour of the package,
A surface-mounted semiconductor device, wherein a tip of the lead exposed on a peripheral side surface of the package is obliquely cut at an acute angle with respect to a bottom surface. リードフレームに半導体チップをマウントして樹脂封止した状態で行うリードカット工程で、パッケージの外形に合わせてリードを樹脂封止部と共に斜めカットすることを特徴とする請求項１記載の表面実装型半導体装置の製造方法。2. The surface mounting die according to claim 1, wherein in a lead cutting step performed in a state where the semiconductor chip is mounted on the lead frame and sealed with a resin, the lead is cut obliquely together with the resin sealing portion in accordance with the outer shape of the package. A method for manufacturing a semiconductor device.
JP2002249870A 2002-08-29 2002-08-29 Surface mounting semiconductor device and its fabricating process Withdrawn JP2004087998A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008186891A (en) * 2007-01-29 2008-08-14 Denso Corp Mold package and its manufacturing method, and mounting structure of the mold package
US9508639B2 (en) 2014-08-06 2016-11-29 Rohm Co., Ltd. Package-in-substrate, semiconductor device and module
US9515013B2 (en) 2014-09-12 2016-12-06 Kabushiki Kaisha Toshiba Semiconductor device
KR20190004225A (en) * 2017-07-03 2019-01-11 가부시기가이샤 디스코 Substrate processing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008186891A (en) * 2007-01-29 2008-08-14 Denso Corp Mold package and its manufacturing method, and mounting structure of the mold package
US9508639B2 (en) 2014-08-06 2016-11-29 Rohm Co., Ltd. Package-in-substrate, semiconductor device and module
US9515013B2 (en) 2014-09-12 2016-12-06 Kabushiki Kaisha Toshiba Semiconductor device
US9620442B2 (en) 2014-09-12 2017-04-11 Kabushiki Kaisha Toshiba Semiconductor device
KR20190004225A (en) * 2017-07-03 2019-01-11 가부시기가이샤 디스코 Substrate processing method
KR102565133B1 (en) * 2017-07-03 2023-08-08 가부시기가이샤 디스코 Substrate processing method

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