JPH0526136B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an apparatus for extracting defects in an object to be inspected in which portions including repetitive patterns are arranged at a predetermined pitch, and in particular to a device for extracting defects in a semiconductor integrated on a wafer. The present invention relates to a repetitive pattern defect inspection device suitable for visual inspection of memory.

[Background of the invention]

2. Description of the Related Art Conventionally, a semiconductor (silicon or the like) wafer is one of the objects to be inspected for repetitive pattern inspection. A circuit pattern is formed on the wafer through various wafer processing steps such as oxidation, photoresist processing, diffusion, thin film formation, and vapor deposition.

In particular, a wafer on which a semiconductor memory is fabricated is formed with a repeating pattern of chips arranged at a predetermined pitch. Cutting margins for dividing the wafer into individual chips exist at equal intervals between adjacent chips.

Conventionally, this type of inspection apparatus has two imaging devices 1a and 1b as shown in FIG. 1, one of which images a certain repeating pattern 5a, and the other imaging another repeating pattern 5b of the same pattern. The video signals 2a and 2b are compared by a comparison circuit 3, and the defective portion is estimated from the mismatched portion.

However, when inspecting minute patterns with such equipment, as the imaging system becomes more precise and has a high magnification, there may be slight positional deviations or out-of-focus between the two imaging systems, slight differences in lighting conditions, or lens The problem was that differences in system distortion appeared as large differences in the video signals, and as a result, false detections (false alarms) were unavoidable and the system could not be used as an inspection device.

As a conventional example of this type of technology,
It is described in Publication No. 54-19664.

Furthermore, the object to be inspected may have locations other than the repeating pattern. For example, if the object to be inspected is a wafer, this corresponds to the cutting margin for dividing it into individual chips. In this case, there is no need to compare locations other than the repeated patterns and estimate the defective portion from the mismatched portions. This is because repeating patterns are not arranged in locations other than the repeating pattern, so if the non-matching portion at that location is also treated as a defect, an error detection (false alarm) will result.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to match the imaging conditions of two video signals to be compared as completely as possible, and to inspect only the repetitive patterns that should originally be inspected. Therefore, it is an object of the present invention to provide a pattern defect inspection device capable of inspecting fine patterns at a relatively low cost.

[Summary of the invention]

Therefore, in the present invention, the object to be inspected is an object to be inspected that has a repeating pattern in which a portion including a fine repeating pattern is repeatedly arranged at a predetermined pitch, such as a semiconductor memory wafer, and has the following configuration. achieved the above objectives.

The first invention of the present application is a repeating pattern defect inspection for inspecting the appearance of an inspected object in which portions including repeated patterns are arranged at a predetermined pitch, which is equipped with an imaging means that scans the inspected object and obtains a video signal. The apparatus includes: a movable table for fixing and moving an object to be inspected; a converting means for converting a video signal obtained by the imaging means into a multi-value digital signal; and a first multi-value digital signal converted by the converting means. , a comparison means for comparing the second multi-valued digital signal converted by the conversion means at least a predetermined pitch before, a storage means for storing the comparison result by the comparison means, and an inspection start coordinate of the repetitive pattern and the inspection. The end coordinates are memorized, and when the inspected object fixed on the movable stage moves and reaches the inspection start coordinates of the repeated pattern, storage in the storage means is started, and when the inspection end coordinates of the repeated pattern are reached. and an activation control means for terminating the storage in the storage means, and inspects the repeated pattern for defects.

Furthermore, the second invention of the present application is provided with an imaging means for scanning an object to be inspected and obtaining a video signal, and for inspecting the appearance of an object to be inspected in which portions including the repeating pattern are arranged at a predetermined pitch. A defect inspection device includes a movable table for fixing and moving an object to be inspected, a conversion means for converting a video signal obtained by an imaging means into a multi-value digital signal, and a converting means for converting the multi-value digital signal converted by the conversion means into a predetermined value. The comparison means compares the first multi-value digital signal converted by the delay means delayed by a pitch, the first multi-value digital signal converted by the conversion means, and the second multi-value digital signal delayed by a predetermined pitch by the delay means. A storage means for storing the results, and a storage means for storing the inspection start coordinates and inspection end coordinates of the repeated pattern, and when the inspected object fixed to the movable table moves and reaches the inspection start coordinates of the repeated pattern. and an activation control means for starting storage in the storage means and for terminating the storage in the storage means when the inspection end coordinate of the repeated pattern is reached, and the repeated pattern is inspected for defects.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 2 to 8.

FIG. 2 is an overall configuration diagram of this embodiment. 4~
10 is an imaging system for capturing an image of the object to be inspected and converting it into an electrical signal; 4 is the object to be inspected; 5a and 5b are repeating patterns on the object; 6 is a moving table for fixing and moving the object to be inspected; , 7 is a position detector, 8 is a moving table control circuit, 9 is an illuminator, and 10 is a line sensor that one-dimensionally scans the image of the object to be inspected and converts it into an electric signal. That is, the object to be inspected 4 is fixed on the moving table 6, and the moving table is moved at a constant speed in the X direction by the moving table control circuit 8. Repeat pattern 5a
is illuminated by an illuminator 9, and its image is formed on a line sensor 10. Therefore, by repeatedly driving the line sensor, the image of the repetitive pattern 5a is output as the video signal S10. At this time, the same repeating pattern 5 as 5a
If b is arranged in the X direction, the exact same video signal will be output as the video signal S10 with a delay of the difference between the positions of 5a and 5b. Generally, in semiconductor memory, parts containing the same repeating pattern are arranged at a predetermined pitch.
By comparing the video signal delayed by the predetermined pitch with the video signal at that point in time, a pattern defect can be detected as a mismatched portion. Second
The circuit blocks shown in the figure are for realizing such functions.

The output signal S10 of the line sensor 10 is converted into a digital signal S11 by an AD converter 11. This is because the following processing is easier with digital signals than with analog signals. The digital manufacturing signal 11 is electrically delayed by the aforementioned predetermined pitch by the delay circuit 12, and compared with the original signal S11 by the comparator circuit 13. The comparison circuit 13 is a circuit that takes the difference between the signals S11 and S12 and outputs a binary video signal S13 which is "1" when the difference is greater than a certain threshold value and "0" when it is smaller. That is, the video signal S13 is a defective video signal in which only the defective candidate area is "1".

In reality, the defective video signal S13 often contains noise due to minute variations in the shape of the repetitive pattern, alignment errors, and the like. The defect determination circuit 14 detects a defective image S containing such noise.
This circuit extracts only reliable defective parts from 13. This function can be realized, for example, by determining that the area of the defect is greater than or equal to a certain threshold, as will be described in detail later.

Reference numeral 15 denotes a defect data storage circuit, which receives the defect detection signal S14 from the defect determination circuit and inputs the moving table position at that time and the scanning coordinate y within the line sensor from the position detector 7 and the timing circuit 16, respectively. This is a circuit that stores data in a memory circuit. This stored data is read into the computer 19 after the input of the image of the object to be inspected is completed, and is used such as being displayed to the operator as defect position data.

Reference numeral 16 is a timing generation circuit that generates various timing pulses necessary for each circuit of the apparatus, such as a synchronization signal for the line sensor 10, and a signal scanning coordinate y on the line sensor, and supplies them to each circuit.

Reference numeral 17 denotes a start control circuit, which stores the inspection start coordinates and inspection end coordinates set in advance from the computer 19, and outputs "1" when the movable table position X from the position detector 7 matches the start coordinates, and outputs "1" at the end coordinates. It has the function of giving a test activation signal that becomes "0" when a match occurs to the timing generation circuit to notify the test time.

According to the above configuration, the repeated patterns 5a and 5b on the object to be inspected can be inspected as follows. First, the computer 19 calculates the moving position of the moving table and the start and end coordinates of the inspection from the position of the repeating pattern, and operates the moving table by the moving table control circuit 8, and also sends the start control circuit 17 the inspection start coordinates, Set end coordinates. The timing generation circuit 16 always sends necessary timing signals to each circuit to drive the circuits, but when it receives an inspection activation signal S17 from the activation control circuit 17, it causes the defect data storage circuit to start storing defect data. When the startup control circuit 17 detects the end of the test,
An interrupt is issued to the computer 19 to notify that the test has been completed. When the computer 19 detects the completion of the inspection, it reads the defect coordinates from the defect data storage circuit 15, records them or displays them to the operator, and completes one unit of inspection operation. By repeating this series of operations a necessary number of times, it is possible to inspect the entire surface of the object to be inspected.

In the above explanation, the digital video signal S
11 and the signal S12 that has passed through the delay circuit 12 are ideally assumed to be completely coincident in terms of position, but in reality, they may not coincide due to speed fluctuations of the moving platform, inclination of the moving direction, etc. Often not. The positional deviation detection circuit 18 is an effective additional circuit in such a case. In other words, if there is a slight difference in position, it can be corrected by adjusting the delay time of the delay circuit, so the amount of positional deviation between the two images is detected by a positional deviation detection circuit, which will be described in more detail later. What is necessary is to correct the amount of delay of the delay circuit 12.

Below, the delay circuit 12, the positional deviation detection circuit 18,
Detailed embodiments of the activation control circuit 17, the defect determination circuit 14, and the defect data storage circuit 15 will be described to clarify that the present invention can be implemented.

First, a detailed embodiment of the delay circuit 12 will be described using FIGS. 3 and 4.

Digital video signal S11 is sent to shift register 2
Clock signals not shown in 1a to 21d
Data is input one by one using CLK. The output signal of each shift register is a timing pulse S
124, register 22a every four clocks.
~22d, and the subsequent timing signal S122 causes the memory circuit 23 to
written to. The write number at this time is signal S12
3, but S123 is given by the timing signal S
120 and the selection circuit 27, the counter 29
matches the content of The counter 29 is clocked once every four clocks by the timing signal S121.
1 will be given. That is, by these operations, the data of the input signal S11 is grouped into four consecutive data items and sequentially written in parallel to the memory circuit 23.

To read data, the read data from the storage circuit is set in parallel in the shift registers 24a to 24d at the rising edge of the timing signal S124, and is output as a signal S125 while being shifted by a clock signal CLK (not shown). are input to shift registers 25a to 25d.
Since reading from the memory circuit 23 to the shift register is performed once every four clocks by the timing pulse S124, four data are inputted just as the shift register becomes denser. The parallel outputs from the shift registers 25a to 25d are the delay circuit output signal S12 selected by the selection circuit 26.
is output as Address S123 of the storage circuit at the time of reading is external delay amount designation data S1
It is obtained by subtracting the data of the upper bits of 8 excluding the lower 2 bits from the contents of the counter 29. The upper bit data excluding the lower 2 bits is the number obtained by dividing the delay amount by 4 and rounding down the remainder, and by subtracting it from the counter contents, it is written in advance in the memory circuit by the delay time. This indicates the address of the written data. The lower 2 bits are inputted as a selection signal to the selection circuit 26 and used to correct data delay amount of 3 clocks or less. In this way, the input signal S11 becomes the delay amount designation data S1.
8 plus 8 clocks, and is outputted as the output signal S12. The extra delay of 8 clocks will not be a problem at all if the amount of delay of 8 clocks is specified at the time of use. In this embodiment, the data is read and written in parallel in groups of four clocks, but this has the advantage that the speed of the storage circuit is slower than the data clock, and is more practical. .
Of course, if the data clock is faster,
It is clear that this problem can be solved by increasing the number of parallel data.

Next, a more detailed embodiment of the positional deviation detection circuit 18 will be described with reference to FIGS. 5 and 6. In FIG. 5, there are two systems of spatial differentiation circuits on the left side, and a positional deviation detection circuit on the right side. First, the spatial differentiation circuit will be explained. Blocks 31a to 31c represent one line shift registers having the number of pixels for one scan of the line sensor, and blocks 32a to 32c and 33a to 33c each represent shift registers for one pixel. Since the input signal is a multi-value digital signal, the shift register for one pixel is composed of flip-flops as many as the number of bits of the input signal. When the input video signal S11 is input to this circuit and each shift register is driven by a sampling clock of a line sensor (not shown), the nine signals output from each shift register are generated from 3×3 pixels in the image plane. This corresponds to the signal of each pixel of a two-dimensional local image. Moreover, this 3×3 pixel local area scans the previous image plane in synchronization with the input video signal. Therefore, the data of the peripheral eight pixels of this 3×3 pixel are completely added in the adder circuit 34, and the difference between the data of the center pixel and the signal S35 obtained through the 8x circuit 35 and the subtracter circuit 36 is calculated. Differentiation, that is, points of change in brightness and darkness can be emphasized. If this spatially differentiated signal S36 is compared with the threshold value θ by the comparison circuit 37, and the signal S36 is binarized so that it becomes “1” when it is larger than the threshold value θ, the signal S37 will be generated only at the bright and dark boundary portion in the video. It becomes a differential binary signal that becomes "1". On the other hand, the other input video signal S12 is also converted into a differential binary video signal S57 by a completely similar circuit. Positional shift detection is performed by checking the degree of coincidence with one of the differential binarized signals whose position on the screen is slightly shifted, and detecting the amount of shift of the image that most closely matches.

Next, the positional deviation detection circuit on the right side will be explained. In the figure, 38a to 38c, 58a, 58b
is a 1-line shift register, 39a to 39c, 4
0a and 59a are one-pixel shift registers. In addition, 41a to 41f are EOR (exclusive OR) gates, 42a to 42f are AND gates, and 43a to 4
3f is a counter. By doing this, the signal S
39a, S39c, S38b, S40a are S39
It represents pixel signals adjacent in four directions on the image with b as the center. Here, S39b and S59a are delayed by the same amount in time by the shift register, so if the input signals S11 and S12 are exactly the same, they will be the same signal, and S3
9a, S39c, S38a, and S40a are video output signals obtained by spatially shifting S39b by one pixel. Therefore, EOR gates 41a-4
1f, and the number of mismatched pixels, that is, "1", is counted by the counters 43a to 43f for a certain period of time. Since the pattern with the smallest counted value is the most matched pattern, the counted value is the smallest. By checking the position of the counter, it is possible to know the amount of deviation between the signals S11 and S12. Control signal S181,
S182 is a control signal for moving the counter at a constant cycle, such as the one shown in FIG. 6, for example. That is, the counter is reset in S182, and then the EOR gate 41 is opened by opening the gates 42a to 42f for a certain period of time in S181.
Count the number of "1" outputs from a to 41f. S1
83 is a result set signal to the next register 48, which sets the final result of positional deviation detection.

Blocks 44a and 44b are minimum position detection circuits that detect and output the position of the counter that indicates the minimum value among the counters. For example, the minimum position detection circuit 44a outputs "-1" if the value of the counter 43a is the smallest, and "0" if the value of the counter 43b is the smallest.
43c, "+1" is output as the signal S44a, and the result indicates the amount of positional deviation in the vertical direction. Similarly, 44b is "-1" as signal S44b indicating the amount of positional deviation in the horizontal direction;
Output as “0” and “+1”. Blocks 45 and 46
is a circuit that converts the vertical and horizontal two-dimensional positional deviation amount into a one-dimensional positional deviation amount, which multiplies the vertical positional deviation amount by the number of pixels for one raster by a constant multiplier circuit 45, and then converts the vertical and horizontal positional deviation amount into a one-dimensional positional deviation amount. The amount of positional deviation is added by a counter circuit 46. Blocks 47 and 48 are adder circuit registers, which add the newly detected positional deviation amount to the current positional deviation amount stored in the register 48 and set the new positional deviation amount in the register 48. be. The register 48 is set by the control signal S183, and its contents are set as S18 by the delay circuit 12 as described above.
is input to. With the above circuit, the amount of positional deviation between the two images S11 and S12 is detected at regular intervals, and it becomes possible to adjust the amount of delay so that S11 and S12 match.

FIG. 7 shows a more detailed embodiment of the activation control circuit 17. Blocks 63 and 64 are registers,
Prior to the inspection, the computer 19 sends the inspection start coordinate X _S and the inspection stop coordinate X _E as a signal S191.
is written. S7 is an output signal of the position detector, and the current position X of the moving table is always inputted to the matching circuits 61 and 62 as S7. Block 65 is a flip-flop which is set and reset by output signals S61 and S62 of the coincidence circuit. As the inspection begins, the moving unit starts moving in the X direction,
Position X of S7 is the inspection start coordinate of register 63
When it matches X _S , the flip-flop 65 is set and the output signal S17 becomes "1" to inform the timing generation circuit 16 that the test is being performed. When the movable table moves further and matches the inspection stop coordinate _XE of the register 64, the flip-flop 65 is reset and S17 becomes "0", notifying the timing generation circuit that the inspection is being stopped. In this way, activation of the overall inspection circuit is controlled.

FIG. 8 shows a more detailed embodiment of the defect determination circuit 14 and the defect data storage circuit 15. In the figure,
71a to 71e are 1 line shift registers, 71a to 71e are 1 line shift registers,
2a-72e, 73a-73e, 74a-74
e, 75a to 75e are one-pixel shift registers. If this circuit is activated by the line sensor sampling clock, it can input the "defect" video signal S13 and output 5.times.5 local area video signals in parallel. Blocks 76a to 76e and 77 are adders that sum up the number of "1"s from the 5.times.5 pixel local images output in parallel. Input signal S
Since 13 is a "defect" image in which the defective portion is "1", the number of "1"s indicates the defect area within the 5×5 local image. Therefore, the defect area signal S77 is set to the threshold value S7.
81 and the comparator 78, the detection signal S78
is set to "1" only when the defect is larger than a certain level, and becomes "0" otherwise, so that a "defect signal" caused by a slight noise is not mistaken as a defect, and stable defect determination can be performed. When the defect determination circuit outputs "1", the moving platform coordinate signal S7 (X, Y) and the line sensor scanning position signal y at that time are set in the register 79, and the timing is further set by the one shot circuit 80. is taken and stored in the storage circuit 81. One shot circuit 8
By 0, the memory circuit 81 is activated only at the rising edge of S78.
Therefore, the pixel coordinates of large defects are prevented from being continuously written into the storage circuit 81. The contents of the memory circuit are read by the computer 19 as a signal S191.

The above explanation clearly shows that the present invention can be implemented concretely.

It should be noted that various modifications of the present invention are possible in addition to the above-mentioned embodiments. For example, the delay circuit in FIG. 2 may be replaced with a mere memory circuit, and the pattern to be tested may be stored in advance and read out repeatedly during testing. In addition, if another pattern is sandwiched between repeating patterns, a function has been added to temporarily stop the shift register clock based on the moving table coordinates calculated from the design data, allowing the input of another pattern to be added. It is also possible to ignore it and perform the inspection. Alternatively, instead of using a line sensor as an imaging device, the same effect can be obtained by scanning a narrowly focused light or electron beam one-dimensionally over the pattern to be inspected and detecting the amount of reflected light or reflected electrons. It will be done.

〔Effect of the invention〕

According to the present invention, it is possible to compare two images under exactly the same imaging conditions;
By eliminating the need to compare parts other than the repeating patterns, it is possible to compare two repeating patterns much more precisely than with conventional technology.
It becomes possible to extract defects in fine patterns such as VLSI.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the prior art, FIG. 2 is an overall configuration diagram showing an embodiment of the present invention, and FIGS. 3 to 8 are detailed explanatory diagrams of each block in the overall configuration diagram. FIG. 3 is an explanatory diagram of the delay circuit 12, FIG. 4 is a diagram showing the timing of its control signal, FIG. 5 is a detailed diagram of the positional deviation detection circuit 18, and FIG. 6 is a diagram showing the timing of its control signal. , Figure 7 shows the startup control circuit 1.
7 is a detailed explanatory diagram, and FIG. 8 is a detailed explanatory diagram of the defect determination circuit 14 and the defect data storage circuit 15. 1a, 1b...imaging device, 3...comparison circuit, 4
...Object to be inspected, 5a, 5b...Repetitive pattern,
6...Moving table, 7...Position detector, 9...Illuminator, 10...Line sensor, S10...Video signal, 11...AD converter, 12...Delay circuit, 1
3... Comparison circuit, 14... Defect determination circuit, 15...
. . . defect data storage circuit, 16 . . . timing generation circuit, 17 . . . startup control circuit, 18 .

Claims (1)

[Scope of Claims] 1. Defect inspection for repeated patterns, which inspects the appearance of an object to be inspected in which portions including repetitive patterns are arranged at a predetermined pitch, which is equipped with an imaging means that scans the object to obtain a video signal. The apparatus includes a movable table for fixing and moving the object to be inspected, a converting means for converting the video signal obtained by the imaging means into a multi-value digital signal, and a first multi-value digital signal converted by the converting means. Comparing means for comparing the digital signal and a second multi-valued digital signal converted by the converting means at least by the predetermined pitch before the digital signal; storage means for storing the comparison result by the comparing means; and repeating the above. An inspection start coordinate and an inspection end coordinate of the pattern are memorized, and when the inspected object fixed to the movable stage moves and reaches the inspection start coordinate of the repeating pattern, storage in the storage means is started. , and activation control means for terminating storage in the storage means when the inspection end coordinates of the repetitive pattern are reached, and a defect inspection apparatus for a repetitive pattern, characterized in that the defect inspection apparatus inspects for defects in the repetitive pattern. 2. The repeating pattern defect inspection apparatus according to claim 1, wherein the imaging means is a line sensor. 3. In claim 1, the imaging means scans the object to be inspected with an electron beam,
A repetitive pattern defect inspection apparatus characterized in that a video signal of the object to be inspected is obtained by detecting an amount of reflected electrons generated by irradiation with the electron beam. 4. The repeating pattern defect inspection device according to claim 1, wherein the repeating pattern is a regularly arranged semiconductor memory pattern. 5. In claim 1, the comparison means calculates the difference between the first and second multi-value digital signals and determines whether the difference is larger or smaller than a predetermined threshold. A repeating pattern defect inspection device characterized by outputting a binary digital signal. 6. In a repeating pattern defect inspection apparatus that is equipped with an imaging means for scanning the inspected object and obtaining a video signal, and inspects the appearance of the inspected object in which parts including repeated patterns are arranged at a predetermined pitch, a moving table for fixing and moving an object; a converting means for converting the video signal obtained by the imaging means into a multi-value digital signal; and a delay for delaying the multi-value digital signal converted by the converting means by the predetermined pitch. means for comparing the first digital signal converted by the converting means and a second multi-value digital signal delayed by the predetermined pitch by the delaying means; and a comparison result by the comparing means. a storage means for storing an inspection start coordinate and an inspection end coordinate of the repeating pattern, and storing the inspection start coordinate and the inspection end coordinate of the repeating pattern, when the inspected object fixed to the movable table moves and reaches the inspection start coordinate of the repeating pattern; and activation control means for starting the storage in the storage means and for terminating the storage in the storage means when the inspection end coordinates for the repeating pattern are reached, the repeating method characterized in that the repeating pattern is inspected for defects in the repeating pattern. Pattern defect inspection device. 7. The repeating pattern defect inspection apparatus according to claim 6, wherein the imaging means is a line sensor. 8. In claim 6, the imaging means scans the object to be inspected with an electron beam,
A repetitive pattern defect inspection apparatus characterized in that a video signal of the object to be inspected is obtained by detecting an amount of reflected electrons generated by irradiation with the electron beam. 9. The repeating pattern defect inspection apparatus according to claim 6, wherein the repeating pattern is a regularly arranged semiconductor memory pattern. 10. The repetitive pattern defect inspection apparatus according to claim 6, wherein the delay means delays the multi-value digital signal using a shift register. 11. The repetitive pattern defect inspection apparatus according to claim 9, wherein the delay means delays by a pitch of a portion including the pattern of the regularly arranged semiconductor memory.