JPH0795042B2 - Repeat pattern defect inspection system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for extracting a defect in a repetitive pattern formed by repetitive fine and identical patterns, and more particularly to a defect inspection device suitable for visual inspection of a semiconductor memory or the like.

[0002]

2. Description of the Related Art A semiconductor wafer or the like is an object to be inspected for a repeated pattern.

Conventionally, this type of inspection apparatus has two image pickup devices 1a and 1b as shown in FIG. 1, one of which picks up a repetitive pattern 5a and the other of which picks up another repetitive pattern 5b having the same pattern. The comparison circuit 3 compares the video signals 2a and 2b to estimate the defective portion from the mismatched portion.

However, when a fine pattern is inspected by such an apparatus, as the image pickup system becomes precise and high magnification,
A slight difference in position between the two image pickup systems, a difference in focus, a slight difference in the illumination state, and a difference in the distortion state of the lens system appear as a large difference in the video signal, so that error detection (false alarm) cannot be avoided. There was a problem that it could not be used as an inspection device.

To solve this problem, Japanese Patent Laid-Open No. 58-58
There is a 37923 publication. In this conventional example, a marker is provided outside the pattern formation area of the photomask in order to solve the problem of slight positional deviation between the two image pickup systems. Then, the positional deviation is corrected based on this marker. However, this method has a problem that an extra step is added because it is necessary to provide a marker for each inspected object.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a pattern defect inspection apparatus capable of correcting even a slight positional deviation.

[0007]

Therefore, in the present invention,
The above object was achieved by limiting the object to a semiconductor memory or the like in which minute repetitive patterns are periodically arranged and adopting the following configuration.

In a defect inspection apparatus of a repetitive pattern for inspecting the appearance of the inspected object in which the repetitive pattern is arranged at a predetermined pitch, the inspection object is fixed by including an image pickup means for scanning the inspected object to obtain a video signal. A moving base for moving the image signal, a converting means for converting the video signal obtained by the image pickup means into a multi-valued digital signal, a delay means for delaying the multi-valued digital signal converted by the converting means by the pitch of the repeating pattern, and a delaying means. Comparison means for comparing the first multi-valued digital signal delayed by the means with the second multi-valued digital signal converted at that time, and the comparison means should compare.
Delay the first and second multilevel digital signals in time.
The two first and second multi-valued digits
Predetermine the spatially corresponding position of the digital signal with a minute shift amount
Pixels are shifted pixel by pixel, two first and one for each shift amount.
The degree of coincidence of the second multilevel digital signal is measured and
Detect the shift amount with a good degree and set the delay amount with the delay means.
It is characterized in that it is provided with a positional deviation detecting means for adjusting, and inspects for defects in a repetitive pattern.

[0009]

With the above construction, even if the object to be inspected does not have a marker or the like, it is possible to eliminate the positional deviation between the two video signals to be compared.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 2 is an overall configuration diagram of this embodiment. Four
Reference numeral 10 denotes an image pickup system for picking up an image of a pattern to be inspected and converting it into a video signal, 4 is an object to be inspected, 5a and 5b are repetitive patterns on the object to be inspected, and 6 is a movement for fixing and moving the object to be inspected. A platform, 7 is a position detector, 8 is a moving platform control circuit, 9 is an illuminator, and 10 is a line sensor for one-dimensionally scanning an image of an object to be inspected and converting it into a video signal. That is, the inspection object 4 is fixed on the movable table 6, and the movable table is moved at a constant speed in the X direction by the movable table control circuit 8. The repeating pattern 5 a is illuminated by the illuminator 9, and its image is formed on the line sensor 10. Therefore, by repeatedly driving the line sensor, the image of the repeated pattern 5a is output as the video signal S10. At this time, 5a
If the same repetitive pattern 5b is arranged in the X direction, the completely same video signal will be output as the video signal S10 with a delay of the difference between the positions of 5a and 5b. Since the repetitive patterns are regularly arranged in the object to be inspected for the repetitive pattern, a pattern defect can be detected as a mismatched portion by comparing the video signals with a time delay corresponding to the repetitive pattern pitch. .
The circuit block shown in FIG. 2 is for realizing such a function.

The output signal S10 of the line sensor 10 is AD
It is converted into a digital signal S11 by the converter 11. This is because the following processing is easier for digital signals than for analog signals. The digital video signal 11 is electrically delayed by the repetitive pattern pitch by the delay circuit 12, and is compared with the original signal S11 and the comparison circuit 1.
Compared by 3. The comparison circuit 13 outputs signals S11 and S
It is a circuit which takes a difference of 12 and outputs a binary video signal S13 which is "1" when the difference is larger than a threshold value and "0" when the difference is smaller than the threshold value. That is, the video signal S13 is a defect video signal in which only the defect candidate area is "1".

In many cases, the defective video signal S13 actually contains noise due to minute shape variations of the repeated pattern, alignment error, and the like. Defect determination circuit 1
Reference numeral 4 is a circuit for extracting only a defective portion to be trusted from the defective image S13 including such noise. This function can be realized, for example, by determining that the area of the defect is equal to or larger than a certain threshold value as described later in detail.

Denoted at 15 is a defect data storage circuit, which receives the defect detection signal S14 from the defect determination circuit, and detects the position of the moving table and the scanning coordinate y in the line sensor at that time from the position detector 7 and the timing circuit 16, respectively. It is a circuit for inputting and storing it in a memory circuit. The stored data is read into the computer 19 after the input of the image of the repetitive pattern is completed, and is used for displaying it as defect position data to the operator.

Reference numeral 16 denotes a timing generation circuit, which is a circuit for generating various kinds of timing pulses necessary for each circuit of the device such as a synchronizing signal of the line sensor 10 and signal scanning coordinates y on the line sensor and supplying the same to each circuit. is there.

Reference numeral 17 denotes a start control circuit which stores the inspection start coordinates and the inspection end coordinates set by the computer 19 in advance, and outputs "1" when the position X of the movable table from the position detector 7 coincides with the start coordinates. It has a function of giving an inspection start signal which becomes “0” when it coincides with the end coordinate to the timing generation circuit to notify the inspection time.

With the above arrangement, the repetitive patterns 5a and 5b on the object to be inspected can be inspected as follows. First, the computer 19 calculates the moving position of the moving table and the start and end coordinates of the inspection from the position of the repeated pattern, and moves the moving table by the moving table control circuit 8 and causes the start control circuit 17 to start and finish the inspection. Set the coordinates. The timing generation circuit 16 constantly sends a timing signal required for each circuit to drive the circuit, but when the inspection start signal S17 is received from the start control circuit 17, the defective data storage circuit starts storing defective data.
When the activation control circuit 17 detects the end of the inspection, it interrupts the computer 9 and notifies that the inspection is completed. When the inspection end is detected, the computer 19 reads out the defect coordinates from the defect data storage circuit 15 and records or displays them to the operator to end the inspection operation for one unit. By repeating this series of operations a required number of times, it is possible to inspect the entire surface of the inspection object.

In the above description, the digital video signal S11 and the signal S12 passing through the delay circuit 12 are
Although it is ideally assumed that the positions perfectly match, in reality, there are many cases where they do not match due to the speed fluctuation of the moving table and the inclination of the moving direction. The position shift detection circuit 18 is an effective additional circuit in such a case. That is, when there is a slight difference in position, correction can be made by adjusting the delay time of the delay circuit. Therefore, the position shift detection circuit, which will be described in more detail later, detects the amount of position shift between the two images, and the delay circuit The delay amount of 12 should be corrected.

Hereinafter, the delay circuit 12 and the position shift detection circuit 1
8. Detailed examples of the start control circuit 17, the defect determination circuit 14, and the defect data storage circuit 15 will be described to clarify that the present invention can be implemented.

First, a detailed embodiment of the delay circuit 12 will be described with reference to FIGS.

The digital video signal S11 is a clock signal CLK not shown in the shift registers 21a-21b.
The data is input one by one. The output signal of each shift register is set in the registers 22a to 22d every four clocks by the timing pulse S124, and further, by the timing signal S122 which follows.
It is written in the memory circuit 23. The write address at this time is given by the signal S123, which is the same as the content of the counter 29 due to the operation of the timing signal S120 and the selection circuit 27. The counter 29 outputs the timing signal S121.
Therefore, every 4 clocks, the value is incremented by 1 every time. That is, by these operations, the data of the input signal S11 is collected into four continuous data and sequentially written in parallel in the memory circuit 23.

In reading data, the read data from the memory circuit is set in parallel in the shift registers 24a to 24d at the rise of the timing signal S124 and is output as the signal S125 while being shifted by the clock signal CLK (not shown). Another shift register 25a
Is input to ~ 25d. Since the reading from the memory circuit 23 to the shift register is performed once every 4 clocks by the timing pulse S124, the shift register becomes just dense and 4 data are input at the same time. The parallel output from the shift registers 25a to 25d is the selection circuit 26.
Output by the delay circuit output signal S12. The address S123 of the memory circuit at the time of reading is obtained by subtracting the data of the upper bits except the lower 2 bits of the delay amount designation data S18 from the outside from the contents of the counter 29. The upper bit data excluding the lower 2 bits is a number obtained by dividing the delay amount by 4 and discarding the remainder, and is written just ahead by the delay time in the memory circuit by subtracting from the contents of the counter. It will indicate the address of the data. By inputting the lower 2 bits as a selection signal of the selection circuit 26, the lower 2 bits are used to correct the data delay amount of 3 clocks or less. By doing so, the input signal S11 is output as the output signal S12 after being accurately delayed by an amount obtained by adding eight clocks to the delay amount designation data S18. The extra delay of 8 clocks does not cause any problem if a small amount of 8 clocks is designated at the time of use. In this embodiment, the data is read out and written in parallel every 4 clocks, but this has the advantage that the speed of the memory circuit is slower than the data clock, which is more practical. . Of course, when the data clock is faster, it is obvious that it can be dealt with by increasing the number of parallel data.

Next, a more detailed embodiment of the displacement detection circuit 18 will be described with reference to FIGS. 5 and 6. In FIG. 5, there are two systems of space differentiating circuits on the left side, and there is a position shift detecting circuit on the right side. First, the space differentiating circuit will be described. Blocks 31a to 31c are one line shift registers having the number of pixels for one scan of the line sensor, and 32a to 32c and 33.
Reference characters a to 33c each represent a shift register for one pixel. 1
The shift register for pixels is composed of flip-flops for the number of bits of the input signal because the input signal is a multivalued digital signal. When the input video signal S11 is input to this circuit and each shift register is driven by the sampling clock of a line sensor (not shown), the nine signals output from each shift register consist of 3 × 3 pixels in the video plane. It corresponds to the signal of each pixel of the two-dimensional local image. Moreover, the local area of 3 × 3 pixels scans the entire image plane in synchronization with the input image signal. Therefore, the data of the peripheral 8 pixels of this 3 × 3 pixel is fully added by the adder circuit 34, and the data of the central pixel is subtracted by the signal S35 obtained through the 8 × circuit 35 and the subtractor circuit 36 to obtain the spatial differentiation, that is, The bright and dark change points can be emphasized. This spatial differential signal S36 is compared with the threshold value θ by the comparison circuit 37, and if the signal S36 is binarized so as to be “1” when the signal S36 is larger than the threshold value θ, the signal S37 will have only the light-dark boundary portion in the image. The differential binarized signal becomes "1". On the other hand, the other input video signal S12 is also converted into the differential binarized video signal S57 by a completely similar circuit. The misregistration is detected by checking the degree of coincidence with the one of the differential binarized signals obtained by slightly shifting the position on the screen, and detecting the shift amount of the image that is most in agreement.

Next, the position shift detection circuit on the right side will be described. In the figure, 38a to 38c, 58a and 58b are 1
Line shift registers, 39a to 369c, 40a, 5
9a is a 1-pixel shift register. 41a to 41
f is an EOR (exclusive OR) gate, 42a to 42f are AND gates, and 43a to 43f are counters. By doing so, the signals S39a, S39c, S38b, and S40a represent image signals that are adjacent to each other in four directions on the video centering on S39b for the same reason as described in the explanation of the spatial differentiation circuit. Here, since S39b and S59a are delayed by the shift register by exactly the same time, if the input signals S11 and S12 are exactly the same, they are exactly the same signals, and S39a, S39c, and S39.
a and S40a are output signals of images obtained by spatially shifting S39b by one pixel. Therefore, the EOR gates 41a to 41f respectively determine the number of pixels that are coincident with S59a and do not coincide, that is, "1", for a certain period of time.
3a to 43f, the pattern with the smallest count value is the best matched pattern. Therefore, by checking the position of the counter with the smallest count value, the signals S11 and S1
You can know the most plausible amount of 2. The control signals S181 and S182 are control signals for moving the counter in a constant cycle, and are signals as shown in FIG. 6, for example. That is, the counter is reset in S182, and then the gate 42 is reset for a certain time in S181.
A-42f are opened and the number of "1" of the output of the EOR gates 41a-41f is counted. S183 is a result set signal to the next register 48, which sets the final result of the positional deviation detection.

The blocks 44a and 44b are minimum position detecting circuits, which are circuits for detecting and outputting the position of the counter showing the minimum value among the counters. For example, if the value of the counter 43a is the smallest, the minimum position detection circuit 44a indicates "-".
1 ", 43b" 0 ", 43c" +1 "
Is output as a signal S44a, and the result indicates the amount of positional deviation in the vertical direction. Similarly 44
b indicates the amount of positional deviation in the horizontal direction as a signal S44b, "-
Outputs 1 "," 0 "," +1 ". Blocks 45 and 4
Reference numeral 6 denotes a circuit for converting the vertical two-dimensional positional deviation amount into a one-dimensional positional deviation amount. The vertical direction positional deviation amount is multiplied by the number of pixels of one raster by a constant multiplication circuit 45, and the horizontal direction positional deviation amount is further calculated. The shift amount is added by the cowton circuit 46.
Blocks 47 and 48 are an adder circuit and a register, respectively.
This is a circuit for adding a newly detected position shift amount to the current position shift amount stored in the register 48 and setting the new position shift amount in the register 48. Register 4
8 is set by the control signal S183, and its content is input to the delay circuit 12 as S18 as described above.
With the above circuit, two images S11 and S
The positional deviation amount between 12 is detected, and the delay amount can be adjusted so that S11 and S12 match.

FIG. 7 is a more detailed embodiment of the activation control circuit 17. The blocks 63 and 64 are registers, and the inspection start coordinate X _S and the inspection stop coordinate X _E are written from the computer 19 as a signal S191 prior to the inspection. S
7 is an output signal of the position detector, which is the current position X of the mobile base.
Is always input to the coincidence circuits 61 and 62 as S7. The block 65 is the output signals S61 and S62 of the coincidence circuit.
It is a flip-flop that is set and reset by. With the start of the inspection, the movable table starts moving in the X direction,
When the position X of S7 coincides with the inspection start coordinate X _S of the register 63, the flip-flop 65 is set and the output signal S17 becomes "1" to notify the timing generation circuit 16 that the inspection is being performed. When the movable table further moves and coincides with the inspection stop coordinate X _E of the register 64, the flip-flop 65 is reset and S17 becomes “0” to notify the timing generation circuit that the inspection is stopped. In this way, the activation of the whole inspection circuit is controlled.

FIG. 8 shows a more detailed embodiment of the defect judgment circuit 14 and the defect data storage circuit 15. In the figure, 71
a to 71e are 1-line shift registers, and 72a to 72e.
e, 73a to 73e, 74a to 74e, 75a to 75e
Is a 1-pixel shift register. If this circuit is activated by the line sensor sampling clock, the "defective" video signal S13 can be input and the 5 × 5 local area video signal can be output in parallel. Blocks 76a-76e and 77
Is an adder, which sums up the number of "1" s from the parallel output 5 × 5 pixel local image. Since the input signal S13 is a "defect" image in which the defective portion is "1", the number of "1" indicates the defect area in the 5 × 5 local image. Therefore, if the defect area signal S77 is compared with the threshold value S781 by the comparator 78, the detection signal S78 becomes "1" only when the defect is large to some extent, and becomes "0" in other cases, and the "defect signal" caused by a slight noise is generated. It is possible to perform a stable defect determination without being mistaken as a defect. When "1" is output by the defect determination circuit, the moving platform coordinate signal S7 at that time is output.
(X, Y) and the scanning position signal y of the line sensor are set in the register 79, and are further stored in the storage circuit 81 at a timed timing by the one-shot circuit 80. Since the one-shot circuit 80 stores the pixel coordinates of a large defect in the memory circuit 81 only at the rising edge of S78, continuous writing of the pixel coordinates of large defects to the memory circuit 81 is stopped.
The contents of the memory circuit are read by the computer 19 as a signal S191.

From the above description, it is made clear that the present invention can be concretely implemented.

The present invention can be modified in various ways other than the above embodiment. For example, the delay circuit in FIG. 2 may be used as a simple storage circuit, and a repeating pattern may be stored in advance and repeatedly read during inspection. Also, when another pattern is sandwiched between repeated patterns, a function to temporarily stop the shift register clock by the moving platform coordinates calculated from the design data is added, and the input of another pattern is ignored. You can also make it possible to inspect. Further, instead of using a line sensor as the image pickup device, the same effect can be obtained by scanning the pattern to be inspected one-dimensionally with light or an electron beam that is narrowed and detecting the reflected light amount or the reflected electron amount. To be

[0030]

According to the present invention, it is possible to correct the positional deviation even without a marker or the like, and it becomes possible to compare two images under exactly the same imaging conditions, which is far superior to the prior art. It becomes possible to accurately compare two patterns to be inspected, and it becomes possible to extract defects in a fine pattern such as a VLSI.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a conventional technique.

FIG. 2 is an overall configuration diagram showing an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a delay circuit 12.

FIG. 4 is a diagram showing timing of control signals.

FIG. 5 is a detailed explanatory diagram of the positional deviation detection circuit 18.

FIG. 6 is a diagram showing timing of control signals.

FIG. 7 is a detailed explanatory diagram of a startup control circuit 17.

FIG. 8 is a detailed explanatory diagram of a defect determination circuit 14 and a defect data storage circuit 15.

[Explanation of symbols]

1a, 1b ... Imaging device, 3 ... Comparison circuit, 4 ... Inspected object,
5a, 5b ... Pattern to be inspected, 6 ... Moving base, 7 ... Position detector, 9 ... Illuminator, 10 ... Line sensor, S10 ... Video signal, 11 ... AD converter, 12 ... Delay circuit, 13 ... Comparison circuit, 14 ... Defect determination circuit, 15 ... Defect data storage circuit, 16 ... Timing generation circuit, 17 ... Startup control circuit,
18 ... Position shift detection circuit, 19 ... Calculator.

 ─────────────────────────────────────────────────── ───Continued from the front page (56) References JP-A-58-37923 (JP, A) JP-A-55-74409 (JP, A) Patent Office Reference 82-1679 (Journal of the Television Society, Vol. 136, No. 1982, PP. 38-44)

Claims (1)

[Claims] 1. A includes an imaging means for obtaining a video signal by scanning the object to be inspected, in the defect inspecting apparatus of a repeating pattern of repeated patterns to check the appearance of the object to be inspected that are arranged at a predetermined pitch, the test A movable table for fixing and moving an object, a converting means for converting a video signal obtained by the image pickup means into a multivalued digital signal, and a multivalued digital signal converted by the converting means for the pitch of the repeating pattern. The delay means for delaying, the comparing means for comparing the first multi-valued digital signal delayed by the delaying means with the second multi-valued digital signal converted at that time, and the comparing means. The first and second multivalued data to be compared.
By delaying the digital signal in time, the two
Spatial correspondence between the first and second multilevel digital signals
The position is shifted for each predetermined pixel by a minute shift amount, and each shift is performed.
Two above first and second multi-valued digit for quantity
Measure the degree of coincidence of the
Position shift that detects and adjusts the amount delayed by the delay means
A defect inspection apparatus for a repetitive pattern, comprising: a detection unit , for inspecting a defect in the repetitive pattern.