JPH05264466A - Inspecting apparatus for defect of repeated pattern - Google Patents

Abstract

PURPOSE:To obtain a defect inspecting apparatus which eliminates an erroneous detection by inspecting only to-be-naturally-inspected repeated patterns. CONSTITUTION:The apparatus is provided with a comparison means 13 for comparing a first multi-value digital signal corresponding to one part including the repeated pattern with a second multi-value digital signal corresponding to a part predetermined pitches prior to the one part including the repeated pattern. Moreover, the apparatus is provided with an activation control means 17. The control means 17 storing an inspection starting coordinate and an inspection end coordinate of the repeated pattern starts the comparison at the comparison means when it comes to the inspection starting coordinate of the repeated pattern, and ends the comparison at the comparison means when it reaches the inspection end coordinate of the repeated pattern. A defect of tone repeated pattern is thus inspected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for extracting defects of an object to be inspected in which portions including repetitive patterns are arranged at a predetermined pitch, and is particularly suitable for appearance inspection of a semiconductor memory integrated on a wafer. The present invention relates to a defect inspection device for repetitive patterns.

[0002]

2. Description of the Related Art A semiconductor (silicon or the like) wafer is one of the objects to be inspected for a repeated pattern. The wafer undergoes various wafer processing steps such as oxidation, photoresist processing, diffusion, thin film formation, vapor deposition, and the like to form a circuit pattern on the wafer.

Particularly, in a wafer in which a semiconductor memory is built, chips, which are repetitive patterns, are formed at a predetermined pitch. Then, between adjacent chips, cutting margins for dividing the wafer into individual chips exist at equal intervals.

Conventionally, this type of inspection apparatus has two image pickup devices 1a and 1b as shown in FIG. 1, one of which picks up a repetitive pattern 5a and the other of which picks up another repetitive pattern 5b having the same pattern. Then, the video signals 2a and 2b are compared by the comparison circuit 3 and the defective portion is estimated from the mismatched portion.

However, when a fine pattern is inspected by such an apparatus, as the image pickup system becomes more precise and higher in magnification,
A slight difference between the two imaging systems, such as a slight misalignment and focus, a slight difference in the lighting condition, and a difference in the distortion of the lens system, etc. appear as large differences in the video signals, so error detection (false alarm) cannot be avoided. , Cannot be used as an inspection device,
There was a problem.

Further, there may be a portion other than the repeated pattern of the object to be inspected. For example, when the object to be inspected is a wafer, this corresponds to a cutting margin for dividing into individual chips. In this case, it is not necessary to compare the portions other than the repeated pattern and estimate the defective portion from the non-matching portion. This is because the repetitive patterns are not arranged in the portions other than the repetitive pattern, and if the non-matching portion of the repetitive patterns is also made defective, an error detection (false alarm) will occur.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above situation, and an object of the present invention is to make the image pickup conditions of two video signals to be compared as completely as possible and perform the original inspection. It is an object of the present invention to provide a pattern defect inspection apparatus which can inspect only repetitive patterns to be inspected and can inspect a fine pattern at a relatively low cost.

[0008]

Therefore, in the present invention, an object to be inspected is an inspection object having a repetitive pattern in which portions including a fine repetitive pattern are repeatedly arranged at a predetermined pitch, such as a wafer of a semiconductor memory. The above object was achieved by adopting the following configuration.

A first aspect of the present invention is a repetitive pattern for inspecting the appearance of an object to be inspected, which comprises image pickup means for scanning an object to be inspected to obtain a video signal, and portions including the repetitive pattern are arranged at a predetermined pitch. In the defect inspection apparatus, the moving table for fixing and moving the object to be inspected, the converting means for converting the video signal obtained by the image pickup means into a multivalued digital signal, and the first multivalued one converted by the converting means. Comparing means for comparing the digital signal with the second multi-value digital signal converted by the converting means at least the predetermined pitch before, and the inspection start coordinates and the inspection end coordinates of the repetitive pattern are stored, and the moving table is stored. The inspection object fixed to
When the inspection start coordinates of the repetitive pattern are reached, the comparison means starts the comparison, and when the inspection pattern coordinates of the repetitive pattern is reached, the start control means for terminating the comparison in the comparison means is provided to inspect the defects of the repetitive pattern. It is characterized by doing.

Further, the second invention of the present application includes an image pickup means for scanning the object to be inspected to obtain a video signal, and inspects the appearance of the object to be inspected in which the portions including the repetitive pattern are arranged at a predetermined pitch. In the defect inspection system for repetitive patterns,
A moving base for fixing and moving the object to be inspected, a converting means for converting the video signal obtained by the image pickup means into a multivalued digital signal, and a delay means for delaying the multivalued digital signal converted by the converting means by the predetermined pitch. And a comparison means (entire inspection circuit) for comparing the first multi-valued digital signal converted by the conversion means with the second multi-valued digital signal delayed by a predetermined pitch, and the inspection of the repeated pattern is started. The coordinates and the inspection end coordinates are stored, and when the object to be inspected fixed to the movable table moves and becomes the inspection start coordinates of the repeated pattern, the comparison by the comparison means is started and the inspection end coordinates of the repeated pattern are set. And a start control means for terminating the comparison in the comparing means when it becomes negative, and inspecting for defects in the repetitive pattern.

[0011]

With the above structure, it is possible to inspect only the repetitive pattern, so that error detection (false alarm) can be prevented.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 2 is an overall configuration diagram of this embodiment. Four
Reference numeral 10 denotes an image pickup system for picking up an image of the object to be inspected and converting it into a video signal, 4 is an object to be inspected, 5a and 5b are repetitive patterns on the object to be inspected, and 6 is a movement for fixing and moving the object to be inspected. A platform, 7 is a position detector, 8 is a moving platform control circuit, 9 is an illuminator, and 10 is a line sensor which scans an image of an inspection object one-dimensionally and converts it into a video signal. That is, the inspection object 4
Is fixed on the moving table 6, and the moving table is moved at a constant speed in the X direction by the moving table control circuit 8. Repeating pattern 5a
Is illuminated by the illuminator 9, and its image is detected by the line sensor 1
Image on 0. Therefore, by repeatedly driving the line sensor, the image of the repeating pattern 5a is output as the video signal S10. At this time, if the same repetitive pattern 5b as 5a is arranged in the X direction, exactly the same video signal is output as the video signal S10 with a delay of the difference between the positions of 5a and 5b.

Generally, in a semiconductor memory, portions including the same repeating pattern are arranged at a predetermined pitch. Therefore, if the video signal delayed by the predetermined pitch is compared with the video signal at that time, A pattern defect can be detected as a mismatched portion. The circuit block shown in FIG. 2 is for realizing such a function.

The output signal S10 of the line sensor 10 is AD
It is converted into a digital signal S11 by the converter 11. This is because the following processing is easier for digital signals than for analog signals. The digital video signal 11 is electrically delayed by the above-mentioned predetermined pitch by the delay circuit 12, and is compared with the original signal S11 by the comparison circuit 13. The comparison circuit 13 outputs the signals S11 and S12.
"1" when the difference is greater than a certain threshold,
It is a circuit that outputs a binary video signal S13 that becomes "0" when it is small. That is, the video signal S13 is a defect video signal in which only the defect candidate area is "1".

In many cases, the defective video signal S13 actually contains noise due to minute shape variations of the repeated pattern, alignment error, and the like. Defect determination circuit 1
Reference numeral 4 is a circuit for extracting only a defective portion to be trusted from the defective image S13 including such noise. This function can also be realized, for example, by determining that the area of the defect is equal to or larger than a certain threshold value, as described later in detail.

Denoted at 15 is a defect data storage circuit, which receives the defect detection signal S14 from the defect determination circuit, and detects the position of the moving table and the scanning coordinate y in the line sensor at that time from the position detector 7 and the timing circuit 16, respectively. It is a circuit for inputting and storing it in a memory circuit. This stored data is read by the computer 19 after the image input of the object to be inspected is finished, and is used for displaying it as defect position data to the operator.

Reference numeral 16 denotes a timing generation circuit, which is a circuit for generating various kinds of timing pulses necessary for each circuit of the device such as a synchronizing signal of the line sensor 10 and a signal scanning coordinate y on the line sensor and supplying them to each circuit. is there.

Reference numeral 17 denotes a start control circuit which stores the inspection start coordinates and the inspection end coordinates set by the computer 19 in advance, and outputs "1" when the moving table position X from the position detector 7 coincides with the starting coordinates. It has a function of giving an inspection start signal which becomes "0" when it coincides with the end coordinate to the timing generation circuit to notify the inspection time.

With the above arrangement, the repetitive patterns 5a and 5b on the object to be inspected can be inspected as follows. First, the computer 19 calculates the moving position of the movable table and the start and end coordinates of the inspection from the position of the repeating pattern, and moves the movable table by the movable table control circuit 8 and causes the start control circuit 17 to start and end the inspection. Set the coordinates. The timing generation circuit 16 constantly sends a timing signal required for each circuit to drive the circuit, but when the inspection start signal S17 is received from the start control circuit 17, the comparison circuit 13 starts the comparison. When the start control circuit 17 detects the end of the inspection, it interrupts the computer 9 and notifies that the inspection is completed. When the inspection end is detected, the computer 19 reads out the defect coordinates from the defect data storage circuit 15 and records or displays them for the operator to end the inspection operation for one unit. By repeating this series of operations a required number of times, it is possible to inspect the entire surface of the inspection object.

In the above description, the digital video signal S11 and the signal S12 passed through the delay circuit 12 are
Although it is ideally assumed that the positions perfectly match, in reality, there are many cases where the positions do not match due to the speed fluctuation of the moving table and the inclination of the moving direction. The position shift detection circuit 18 is an additional circuit effective in such a case. That is, when there is a slight difference in position, the correction can be made by adjusting the delay time of the delay circuit. Therefore, the position shift detection circuit, which will be described in more detail later, detects the amount of position shift between the two images, and the delay circuit The delay amount of 12 may be corrected.

Hereinafter, the delay circuit 12 and the positional deviation detection circuit 1
8, detailed examples of the activation control circuit 17, the defect determination circuit 14, and the defect data storage circuit 15 will be described to clarify that the present invention can be implemented.

First, a detailed embodiment of the delay circuit 12 will be described with reference to FIGS. 3 and 4.

The digital video signal S11 is a clock signal CLK not shown in the shift registers 21a-21b.
Inputs one data at a time. The output signal of each shift register is set in the registers 22a to 22d at every 4 clocks by the timing pulse S124, and further by the timing signal S122 which follows it.
It is written in the memory circuit 23. The write address at this time is given by the signal S123, which is the same as the content of the counter 29 due to the operation of the timing signal S120 and the selection circuit 27. The counter 29 outputs the timing signal S121.
Therefore, every 4 clocks, the value is incremented by 1 every time. That is, by these operations, the data of the input signal S11 is collected into four continuous data and sequentially written in parallel in the memory circuit 23.

In reading data, the read data from the memory circuit is set in parallel in the shift registers 24a to 24d at the rising edge of the timing signal S124 and is output as the signal S125 while being shifted by the clock signal CLK (not shown). Another shift register 25a
Is input to ~ 25d. Since the reading from the memory circuit 23 to the shift register is performed once every 4 clocks by the timing pulse S124, the shift register becomes just dense and 4 data are input at the same time. The parallel outputs from the shift registers 25a to 25d are selected by the selection circuit 26.
Output by the delay circuit output signal S12. The address S123 of the memory circuit at the time of reading is obtained by subtracting the data of the upper bits except the lower 2 bits of the delay amount designation data S18 from the outside from the contents of the counter 29. The upper bit data excluding the lower 2 bits is the number obtained by dividing the delay amount by 4 and discarding the remainder, and is written just ahead by the delay time in the memory circuit by subtracting from the contents of the counter. It will indicate the address of the data. By inputting the lower 2 bits as a selection signal of the selection circuit 26, the lower 2 bits are used for correcting the data delay amount of 3 clocks or less. In this way, the input signal S11 is output as the output signal S12 after being accurately delayed by an amount obtained by adding eight clocks to the delay amount designation data S18. The extra delay of 8 clocks does not cause any problem if a small amount of 8 clocks is designated at the time of use. In this embodiment, the data is read out and written in parallel for every four clocks, but this has the advantage that the speed of the memory circuit is slower than the data clock, which is more practical. .. Of course, when the data clock is faster, it is obvious that it can be dealt with by increasing the number of parallel data.

Next, a more detailed embodiment of the displacement detection circuit 18 will be described with reference to FIGS. 5 and 6. In FIG. 5, there are two systems of space differentiating circuits on the left side, and there is a position shift detecting circuit on the right side. First, the spatial differentiation circuit will be described. Blocks 31a to 31c are one line shift registers having the number of pixels for one scan of the line sensor, and 32a to 32c, 33.
Reference characters a to 33c each represent a shift register for one pixel. 1
Since the input signal is a multi-valued digital signal, the shift register for pixels is composed of flip-flops for the number of bits of the input signal. When the input video signal S11 is input to this circuit and each shift register is driven by the sampling clock of a line sensor (not shown), the nine signals output from each shift register consist of 3 × 3 pixels in the video plane. It corresponds to the signal of each pixel of the two-dimensional local image. Moreover, the local area of 3 × 3 pixels scans the entire image plane in synchronization with the input image signal. Therefore, the data of the peripheral 8 pixels of the 3 × 3 pixels are fully added by the adder circuit 34, and the data of the central pixel is subtracted by the subtraction circuit 36 from the signal S35 obtained through the octuple circuit 35. The bright and dark change points can be emphasized. The spatial differential signal S36 is compared with the threshold value θ by the comparison circuit 37, and if the signal S36 is binarized so as to be “1” when the signal S36 is larger than the threshold value θ, the signal S37 has only the light-dark boundary portion in the image. The differential binarized signal becomes "1". On the other hand, the other input video signal S12 is also converted into the differential binarized video signal S57 by the same circuit. The misregistration is detected by checking the degree of coincidence with a position on the screen where one of the differential binarized signals is slightly shifted, and detecting the shift amount of the image that is most in agreement.

Next, the position shift detection circuit on the right side will be described. In the figure, 38a to 38c, 58a and 58b are 1
Line shift registers, 39a to 369c, 40a, 5
9a is a 1-pixel shift register. 41a to 41
f is an EOR (exclusive OR) gate, 42a to 42f are AND gates, and 43a to 43f are counters. By doing so, the signals S39a, S39c, S38b, and S40a represent image signals adjacent to each other in four directions on the video centering on S39b for the same reason as described in the explanation of the spatial differentiating circuit. Here, since S39b and S59a are delayed by the shift register by exactly the same time, if the input signals S11 and S12 are exactly the same, they are exactly the same signals, and S39a, S39c, and S39.
a and S40a are video output signals obtained by spatially shifting S39b by one pixel. Therefore, the EOR gates 41a to 41f each determine the number of pixels that coincide with S59a and do not coincide with each other, that is, the number of "1", for a certain time.
3a to 43f, the pattern with the smallest count value is the best matched pattern. Therefore, by checking the position of the counter with the smallest count value, the signals S11 and S1 are detected.
You can know the most plausible amount of 2. The control signals S181 and S182 are control signals for moving the counter in a constant cycle, and are signals as shown in FIG. 6, for example. That is, the counter is reset in S182, and then the gate 42 is reset for a certain time in S181.
The number "1" of the outputs of the EOR gates 41a to 41f is counted after opening a to 42f. S183 is a subsequent set signal to the register 48, which sets the final result of the positional deviation detection.

The blocks 44a and 44b are minimum position detecting circuits, which are circuits for detecting and outputting the position of the counter showing the minimum value among the counters. For example, if the value of the counter 43a is the smallest, the minimum position detection circuit 44a indicates "-".
1 ", 43b" 0 ", 43c" +1 "
Are output as signals S44a, respectively, and the result indicates the amount of positional deviation in the vertical direction. Similarly 44
b is the amount of positional deviation in the horizontal direction as a signal S44b, which is "-
Outputs 1 "," 0 ", and" +1 ". Blocks 45 and 4
Reference numeral 6 denotes a circuit for converting the vertical two-dimensional positional deviation amount into a one-dimensional positional deviation amount, which is obtained by multiplying the vertical direction positional deviation amount by the number of pixels of one raster by a constant multiplying circuit 45, and further calculating the lateral direction position. The shift amount is added by the cowton circuit 46.
Blocks 47 and 48 are an adder circuit and a register,
This is a circuit for adding a newly detected position shift amount to the current position shift amount stored in the register 48 and setting the new position shift amount in the register 48. Register 4
8 is set by the control signal S183, and the content thereof is input to the delay circuit 12 as S18 as described above.
With the above circuit, two images S11 and S
The positional deviation amount between 12 is detected, and the delay amount can be adjusted so that S11 and S12 match.

FIG. 7 is a more detailed embodiment of the activation control circuit 17. The blocks 63 and 64 are registers, and the inspection start coordinate X _S and the inspection stop coordinate X _E are written from the computer 19 as a signal S191 prior to the inspection. S
7 is the output signal of the position detector, which is the current position X of the mobile platform.
Is always input to the coincidence circuits 61 and 62 as S7. The block 65 is the output signals S61 and S62 of the coincidence circuit.
It is a flip-flop that is set and reset by. With the start of the inspection, the movable table starts moving in the X direction,
When the position X of S7 coincides with the inspection start coordinate X _S of the register 63, the flip-flop 65 is set and the output signal S17 becomes "1" to notify the timing generation circuit 16 that the inspection is being performed. When the movable table further moves and coincides with the inspection stop coordinate X _E of the register 64, the flip-flop 65 is reset and S17 becomes "0" to notify the timing generation circuit that the inspection is stopped. In this way, the activation of the whole inspection circuit is controlled.

FIG. 8 shows a more detailed embodiment of the defect judgment circuit 14 and the defect data storage circuit 15. In the figure, 71
a to 71e are 1-line shift registers, and 72a to 72e.
e, 73a to 73e, 74a to 74e, 75a to 75e
Is a 1-pixel shift register. If this circuit is activated by the line sensor sampling clock, the "defective" video signal S13 can be input and the 5 × 5 local area video signal can be output in parallel. Blocks 76a-76e and 77
Is an adder, which sums the number of "1" s from the parallel output 5 × 5 pixel local image. Since the input signal S13 is a "defect" image in which the defective portion is "1", the number of "1" indicates the defect area in the 5 × 5 local image. Therefore, if the defect area signal S77 is compared with the threshold value S781 by the comparator 78, the detection signal S78 becomes "1" only when the defect is large to a certain extent, and "0" at the other, and the "defect signal" caused by a slight noise is obtained. It is possible to make a stable defect determination without being mistaken for a defect. When "1" is output by the defect determination circuit, the moving platform coordinate signal S7 at that time is output.
(X, Y) and the scanning position signal y of the line sensor are set in the register 79, and are stored in the storage circuit 81 at a timed timing by the one-shot circuit 80. Since the one-shot circuit 80 stores the pixel coordinates of a large defect in the memory circuit 81 only at the rising edge of S78, continuous writing of the pixel coordinates of a large defect in the memory circuit 81 is stopped.
The contents of the memory circuit are read by the computer 19 as a signal S191.

From the above description, it is made clear that the present invention can be implemented concretely.

The present invention can be modified in various ways other than the above-mentioned embodiment. For example, the delay circuit in FIG. 2 may be a simple storage circuit, and a repeating pattern may be stored in advance and repeatedly read during inspection. When another pattern is sandwiched between repeated patterns, a function to temporarily stop the clock of the shift register by the moving platform coordinates calculated from the design data is added, and the input of another pattern is ignored. It is also possible to make it possible to inspect. Further, instead of using the line sensor as the image pickup device, the same effect can be obtained by scanning the object to be inspected one-dimensionally with light or an electron beam that is narrowed down and detecting the reflected light amount or the reflected electron amount. Be done.

[0033]

According to the present invention, it becomes possible to compare two images under exactly the same imaging conditions,
By eliminating the need to compare locations other than repetitive patterns, it is possible to compare two repetitive patterns much more accurately than in the prior art, and it is possible to extract defects in fine patterns such as VLSI. become.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a conventional technique.

FIG. 2 is an overall configuration diagram showing an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a delay circuit 12.

FIG. 4 is a diagram showing timing of control signals.

FIG. 5 is a detailed explanatory diagram of the positional deviation detection circuit 18.

FIG. 6 is a diagram showing a timing of a control signal.

FIG. 7 is a detailed explanatory diagram of a startup control circuit 17.

FIG. 8 is a detailed explanatory diagram of a defect determination circuit 14 and a defect data storage circuit 15.

[Explanation of symbols]

1a, 1b ... Imaging device, 3 ... Comparison circuit, 4 ... Inspected object,
5a, 5b ... Repeating pattern, 6 ... Moving base, 7 ... Position detector, 9 ... Illuminator, 10 ... Line sensor, S10 ... Video signal, 11 ... AD converter, 12 ... Delay circuit, 13 ... Comparison circuit, 14 Defect determination circuit, 15 Defect data storage circuit, 16 Timing generation circuit, 17 Start control circuit,
18 ... Position shift detection circuit, 19 ... Calculator.

Claims (11)

[Claims] 1. A defect inspection apparatus for a repetitive pattern, comprising an image pickup means for scanning an object to be inspected to obtain a video signal, and inspecting the appearance of the object to be inspected, wherein portions including the repetitive pattern are arranged at a predetermined pitch. A moving table for fixing and moving the object to be inspected, a converting means for converting the video signal obtained by the image pickup means into a multivalued digital signal, and a first multivalued digital signal converted by the converting means. And comparing means for comparing at least the second multi-value digital signal before the predetermined pitch converted by the converting means, and inspection start coordinates and inspection end coordinates of the repetitive pattern are stored, and the movement is performed. When the object to be inspected fixed to the table moves and reaches the inspection start coordinates of the repeating pattern, the comparison in the comparing means is started to inspect the repeating pattern. A repeat pattern defect inspection apparatus, comprising: a start control unit for ending the comparison in the comparison unit when the end coordinates are reached, for inspecting a defect in the repeat pattern. 2. The defect inspection apparatus for a repetitive pattern according to claim 1, wherein the image pickup means is a line sensor. 3. The image pickup means obtains a video signal of the object to be inspected by scanning the object to be inspected with an electron beam and detecting an amount of backscattered electrons generated by irradiation of the electron beam. The defect inspection apparatus for a repetitive pattern according to claim 1. 4. The defect inspection apparatus for a repetitive pattern according to claim 1, wherein the repetitive pattern is a pattern of a semiconductor memory that is regularly arranged. 5. The comparing means comprises: the first and the second.
2. The defect of the repetitive pattern according to claim 1, wherein a difference between the multi-valued digital signals of 1 is taken, and whether the difference is larger or smaller than a predetermined threshold value is judged to output a binary digital signal. Inspection equipment. 6. A repetitive pattern defect inspecting apparatus for inspecting an appearance of an inspected object, wherein a portion including the repetitive pattern is arranged at a predetermined pitch, comprising an image pickup means for scanning the inspected object to obtain a video signal. A movable table for fixing and moving the object to be inspected, converting means for converting the video signal obtained by the image pickup means into a multivalued digital signal, and the multivalued digital signal converted by the converting means for the predetermined value. Delay means for delaying the pitch, comparison means for comparing the first multi-valued digital signal converted by the conversion means with the second multi-valued digital signal delayed by the predetermined pitch by the delay means, When the inspection start coordinates and the inspection end coordinates of the repetitive pattern are stored and the inspection object fixed on the movable table moves to the inspection start coordinates of the repetitive pattern, the comparison hand To initiate the comparison in, and a start control means for terminating the comparison in comparison means when it is inspected end coordinate of the repeating pattern, defect inspection device features and repeating pattern to inspect a defect of the repeated pattern. 7. The defect inspection apparatus for a repetitive pattern according to claim 6, wherein the imaging means is a line sensor. 8. The image pickup means scans the object to be inspected with an electron beam to detect the amount of backscattered electrons generated by irradiation of the electron beam to obtain a video signal of the object to be inspected. 7. The defect inspection apparatus for repetitive patterns according to claim 6. 9. The defect inspection apparatus for a repetitive pattern according to claim 6, wherein the repetitive pattern is a pattern of a semiconductor memory that is regularly arranged. 10. The defect inspection apparatus for a repetitive pattern according to claim 6, wherein the delay means delays the multivalued digital signal by using a shift register. 11. A defect inspection apparatus for a repetitive pattern according to claim 9, wherein said delay means delays by a pitch of a portion including the regularly arranged semiconductor memory pattern.