JP2710527B2 - Inspection equipment for periodic patterns - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for inspecting defects such as scratches, pinholes, black spots and dust on an inspection object having a periodic pattern such as a shadow mask and a color filter for a liquid crystal display panel.

[0002]

2. Description of the Related Art Conventionally, inspection of defects in a periodic pattern has been carried out visually with a naked eye or using a microscope. The inspection has a drawback that the inspection accuracy and reliability are reduced. Various inspection apparatuses have been proposed to solve this problem. JP-A-62-2
The device disclosed in Japanese Patent Publication No. 130343 is one example.

FIG. 7 is an explanatory view showing the principle of inspection by this conventional apparatus. FIG. 7A shows an example of a periodic pattern as an inspection target. In this periodic pattern, two light and dark areas are repeated. FIG.
FIG. 7C shows an example of a multi-valued image (an image having a gradation corresponding to lightness) obtained by imaging this pattern along the line AA in FIG. 7A, and FIG. Is an image obtained by delaying the multi-valued image by one cycle. FIG. 7D shows FIG.
9 is a difference image obtained by calculating a difference between two multi-value images of (b) and (c). In this conventional device, a portion in the difference image whose value is equal to or larger than a predetermined threshold is determined as a defect. Each image in FIGS. 7B to 7D is represented by an image signal.

[0004]

However, the repetition period of the pattern is not always an integral multiple of the pixel which is the minimum unit constituting the image. Therefore, the gradient of the gradation change at the point where the brightness of the pattern changes (change point) is
Generally, the difference image differs for each repetition period. Therefore, as shown in FIG.
High values also appear at transition points. As a result, there is a problem that it is erroneously determined that a defect exists even in the vicinity of the change point.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a periodic pattern inspection apparatus for inspecting a periodic pattern for defects without error.

[0006]

A periodic pattern inspection apparatus according to the present invention is an apparatus for inspecting a defect in an inspection object whose pattern repeats at a constant cycle,
(A) image input means for obtaining a multi-valued image having a gradation corresponding to the brightness of the inspection object, and (b) shifting the multi-valued image by an integral multiple of the period in a direction in which the pattern repeats. First displacement means for obtaining a displaced multi-valued image; (c) difference calculating means for calculating a difference between the multi-valued image and the displaced multi-valued image to obtain a differential multi-valued image; An absolute value calculating means for calculating an absolute value of the value image to obtain an absolute multi-value image;
(E) first binarizing means for comparing a value in the absolute multi-valued image with a predetermined first threshold and binarizing according to a result of the comparison to obtain a first binary image; , (F)
(G) comparing a value in the edge image with a predetermined second threshold, and an edge extracting unit for obtaining an edge image representing an edge portion in the multi-valued image obtained by the image input unit;
By binarizing according to the comparison result, the second binary
Second binarizing means for obtaining a value image; and (h) the second binarizing means.
Second displacement means for obtaining a displacement binary image in which the value image is shifted by an integral multiple of the period in a direction in which the pattern repeats;
(I) logical product calculating means for calculating a logical product of the second binary image and the displacement binary image to obtain a mask image;
(J) mask means for calculating a logical product of an inverted image of the mask image and the first binary image to obtain a masked image; and (k) a defect in the inspection object based on the masked image. And detecting means for detecting

In the present invention, in order to avoid complicated description, an "image signal" which represents an image and is processed by each means is used.
And "image" itself without distinguishing them
Is expressed as

[0008]

The inspection apparatus according to the present invention obtains a difference image between a multivalued image of an inspection object having a periodic pattern and a displacement multivalued image, and binarizes its absolute value, thereby obtaining an inspection object. A binary image to be a defect candidate existing in the object is extracted. In the binary image, in addition to the defect candidate image, useless images corresponding to the change points in the multi-valued image are mixed. The mask image obtained based on the multi-valued image expresses this change point, and by calculating the logical product of the inverted image of the mask image and the binarized image, an unnecessary image is obtained from the binarized image. It is removed and only the masked image corresponding to the defect candidate is extracted. Based on the masked image, a defect is selected from the defect candidates to detect the defect.

[0009]

【Example】

[1. FIG. 2 is a block diagram showing the overall configuration of an inspection apparatus according to an embodiment of the present invention. The image input block (image input means) 10 is a device portion for obtaining a multi-value image of the inspection object 1. In the image input block 10, the inspection object 1 is placed on the stage 11 and transported in the sub-scanning direction Y. In the course of transport, the image of the inspection object 1 is read in the main scanning direction X in pixel units by the reading device 12. A / D conversion circuit 1
3 digitizes the image sent from the reading device 12 to obtain a multi-valued image. This multi-valued image is compared with the comparison block 20
Is input to the mask generation block 30. Stage 11
Is driven by a stage drive system 14 controlled by a control system 15. Further, the control system 15 is controlled by the microprocessor unit 70.

In a comparison block 20, an image obtained by delaying the multi-valued image by an integral multiple of the pattern repetition period is compared with the original multi-valued image. Then, a binary image obtained by binarizing the absolute value of the difference between these two images is obtained and supplied to the defect position identification / defect type block 40. Mask generation block 3
At 0, a mask image is created based on the multi-valued image. The defect position identification / defect type block 40 is a comparison block 20
The position and the type of the defect candidate are specified based on the image obtained by calculating the logical product of the binary image input from the mask image and the inverted image of the mask image.

[0011] The defect detection block 60 specifies a defect position.
From the image of the defect candidate sent from the defect type block 40, a defect candidate having a size equal to or larger than a predetermined value is determined as a defect,
The defect image and its position coordinates are stored. The coordinates are read out by the microprocessor unit 70, and the image
It is displayed at T71. The defect confirmation device 73 includes a CRT 71
Is enlarged and displayed. The defective product removing device 74 conveys the inspection target object determined to have a defect to a defective product tray or the like. The operation of the microprocessor unit 70 is instructed by an operator operating the keyboard 72 as appropriate.

[2. Comparison Block] FIG. 1 is a block diagram showing the internal configuration of a comparison block 20, a mask generation block 30, a defect position identification / defect type block 40, and a defect detection block 60. FIG. 3 is a schematic diagram showing images Pa to Pm in the process of being processed by these blocks.

The multi-valued image Pa obtained by the image input block 10 is sequentially input to a delay circuit (first displacement means) 21 and a difference circuit (difference calculation means) 22 of a comparison block 20 for each pixel. In the multi-valued image Pa whose example is shown in FIG.
A region surrounded by a rectangle (drawn with a satin pattern) is, for example, an image region having an intermediate gradation value. Repeating units A, G
The hatched area indicates a defect candidate having a low gradation value, that is, a defect candidate (black defect candidate) that appears in an image as a dark portion. The white area drawn in the repeating unit D represents a defect candidate having a high gradation value, that is, a defect candidate (white defect candidate) that appears in the image as a bright part. The range to be tested (effective range) is the repeating unit A
ＧG.

The delay circuit 21 delays the multi-level image Pa by one cycle and outputs the delayed multi-level image (displaced multi-level image) Pb. The difference circuit 22 includes a multi-valued image Pa and a delayed multi-valued image P
The difference b is calculated and output as a difference multi-valued image. An absolute value circuit (absolute value calculating means) 23 calculates the absolute value of the differential multi-valued image and outputs it as an absolute multi-valued image. Binarization circuit 2
4 (first binarizing means) binarizes the value of the absolute multi-valued image by comparing it with a predetermined threshold (first threshold).
Output as a value image (first binary image). Binarization is
For example, this is performed by assigning a value “1” to an area having a value higher than the threshold and assigning a value “0” to an area other than the threshold. The line / pixel delay 25 is a binarization circuit 2
4 is a delay circuit that delays the image output from the pixel 4 by a predetermined number of main scanning lines and further delays the image by a predetermined number of pixels in the main scanning direction X. This line pixel delay 25
Adjusts the timing of input to the defect position identification / defect type block 40 such that an image at the same pixel as the image input to the defect position identification / defect type block 40 from the mask generation block 30 is input. It is provided for.

FIG. 3 shows a binary image Pc (first binary image) output from the line / pixel delay 25. The binary image Pc has a value “1” in a portion corresponding to a defect candidate in either the multi-valued image Pa or the delayed multi-valued image Pb (shown by hatching in FIG. 3). In addition, the outline of the rectangular area corresponding to the change point has a value “1” in a part or the whole (depicted by a solid line in FIG. 3). The image of the contour portion is an unnecessary image portion other than the image to be a defect candidate, and is an image portion to be removed in order to avoid erroneous determination in defect determination.

[3. Mask Generation Block] The mask generation block 30 generates a mask image Pm for removing unnecessary image portions in the binary image Pc. Multi-valued image P
a is the mask generation block 3 together with the comparison block 20.
0 is also input at the same time. The input multi-valued image Pa is
First, in the line memory 31, three pixels are developed in the sub-scanning direction Y. Edge extraction circuit 32 (edge extraction means)
Is converted into a multi-valued image Pa for three lines developed in the line memory 31 by, for example, JP-A-2-7956 by the same applicant.
No. 6 or Japanese Patent Publication 2-
A known spatial filter disclosed in, for example, Japanese Patent No. 39913 or the like is applied to obtain an edge image expressing a spatial change of an image. The edge image represents, for example, the magnitude of the spatial change rate (derivative) of the multi-valued image Pa. That is, the edge image has a larger value at a change point of the multi-valued image Pa as the value changes more steeply. Therefore, FIG.
Has a large value in the outline of the portion corresponding to the defect candidate in the multi-valued image Pa and the outline of the rectangular area.

The binarizing circuit 33 (second binarizing means)
By comparing the value of the edge image with a predetermined threshold value, the edge image is binarized to obtain a binary image Pj (second binary image). Therefore, as shown in FIG. 3, the binary image Pj has the value "" in the outline of the defect candidate and the outline of the rectangular area.
1 "(drawn with solid lines).

The delay circuit 34 (second displacement means) delays the binary image Pj by one period and outputs it as a delayed binary image (displaced binary image) Pk. The logical product circuit (logical product calculation means) 35 calculates the logical product of the binary image Pj and the delayed binary image Pk, and outputs the result as a mask image Pm. The mask image Pm has a value “1” only in a portion where the value is “1” in both the binary image Pj and the delayed binary image Pk.
Therefore, the image corresponding to the contour of the defect candidate appearing in the binary image Pj and the delayed binary image Pk is the mask image P
It disappears at m. Therefore, the mask image Pm expresses only a portion corresponding to a useless image in an image corresponding to a change point in the multi-valued image Pa. That is, in the example of FIG. 3, the mask image Pm has a value “1” only in a portion corresponding to the rectangular outline in the multi-valued image Pa. The inversion circuit 36 includes an inverter, and inverts the value of the mask image Pm.

[4. Defect location identification / defect type block]
Both the inverted image of the mask image Pm and the binary image Pc are input to the AND circuit 41 (mask means). The logical product circuit 41 calculates the logical product of these images and outputs the result as the masked image Pd. In other words, the AND circuit 41
From the portion having the value “1” in the binary image Pc,
The portion having the value “1” in the mask image Pm is removed. Therefore, in the masked image Pd, unnecessary image portions in the binary image Pc are removed, and the masked image Pd is removed.
d has the value “1” only in the portion corresponding to the defect candidate. The position and type of the defect candidate are specified based on the masked image Pd.

<4-1. In the position identification of defect candidate> masked image Pd, as shown in FIG. 3, one defect candidate appears over two repetition units. Therefore,
The position of a defect candidate is specified based on the principle described below.

FIG. 4 is a schematic diagram showing the principle of specifying the position of the defect candidate. In FIG. 4, images P, Q, and R are
Each represents a multi-level image Pa of one repetition unit adjacent to each other in the periodic pattern. The image P has both a black defect candidate (shown by hatching), the image Q has both a white defect candidate (shown by white) and a black defect candidate, and the image R has a white defect candidate. In the figures of these images, a region surrounded by a rectangle (drawn in a satin pattern) represents an image region having an intermediate gradation value. The binary images Pc obtained from the differential multivalued image S obtained from the images P and Q and the differential multivalued image T obtained from the images Q and R are the images U and V, respectively. Here, for the sake of simplicity, it is assumed that there are no unnecessary image parts,
A description of the process of applying the mask is omitted. As shown in FIG. 4, the defect candidates appearing in the image Q are the image U and the image V
Appear on both sides. Therefore, by calculating the logical product of these images U and V, an image W in which only the defect candidates existing in the original image Q appear is obtained. By repeating the above operation for each repetition unit, the position of the defect candidate can be specified.

In the defect position specifying / defect type block 40 based on this principle, first, the masked image Pd is delayed by one cycle by the delay circuit 42 to obtain a delayed binary image Pe. Subsequently, the logical product of the masked image Pd and the delayed binary image Pe is calculated by the logical product circuit 43, and the defect candidate image Pf is obtained. This defect candidate image P
f corresponds to the image W described above.

As understood from FIG. 4, the image P and the image R are required to specify the defect candidate of the image Q. Therefore, it is not possible to specify the position of a defect candidate appearing in the image of both the first repeating unit and the last repeating unit using only this principle. In order to compensate for the missing part in the position specification, the following operation may be additionally performed. That is, in order to specify a defect candidate in the first repetition unit, a logical product of the inverted image of the image V and the image U may be calculated. In the resulting image, defect candidates in the first repetition unit appear. In the defect position specifying / defect type block 40 based on this principle, the masked image Pd is inverted by the inverting circuit 44, and the inverted image and the delay 2 are inverted by the AND circuit 45.
The logical product with the value image Pe is calculated, and a defect candidate image Pg is obtained. In the defect candidate image Pg, a defect candidate in the first repeating unit A of the original multi-valued image Pa appears.

In order to specify a defect candidate in the last repetition unit, a logical product of the inverted image of the image U and the image V may be calculated. In the resulting image, defect candidates in the last repeat unit appear. Based on this principle, in the defect position specifying / defect type block 40, the delayed binary image Pe is inverted by the inverting circuit 46, and the logical product of the inverted image and the image to be masked Pd is calculated by the logical product circuit 47, and the defect is calculated. A candidate image Ph is obtained. In the defect candidate image Ph, a defect candidate in the last repeating unit G of the original multi-valued image Pa appears.

Since these defect candidate images Pg and Ph are calculated only after both the masked image Pd and the delayed binary image Pe are output, the result of identifying the defect candidate of the first repetition unit A and the second And the result of specifying the defect candidate of the last repetition unit G and the result of specifying the defect candidate of the immediately preceding repetition unit F are simultaneously output. In other words, as the defect candidate images Pf, Pg, and Ph, images corresponding to the same repeating unit are obtained at the same time. Therefore, defect location identification and
In the defect type block 40, the delay circuit 48 delays the defect candidate image Pf by one period, and the delay circuit 49 delays the defect candidate image Ph by two periods. Then, these defect candidate images Pf, Pg,
And Ph for each repetition unit to obtain a defect candidate image Pi. That is, the selection circuit 50 selects the defect candidate image Pg for the first repeating unit A, and selects the last repeating unit G
, The defect candidate image Ph is selected, and for the repetition units BF between them, the defect candidate image Pf is selected. As a result, the defect candidate image Pi expresses the defect candidates in all the repeating units from the first repeating unit to the last repeating unit G without duplication.

<4-2. Determining the Type of Defect Candidate> The defect candidate image Pi includes both the defect candidates, the black defect candidate and the white defect candidate, and it is not possible to identify which of them is the same. The principle of specifying the type of defect based on the defect candidate image Pi will be described below.

Comparison block 2 in the block diagram of FIG.
At 0, the comparison between the multi-valued image Pa and the delayed multi-valued image Pb is performed in the difference circuit 22, and the difference multi-valued image obtained by the value of those images, that is, the degree of brightness, The sign is positive or negative. The type of the defect candidate can be specified by storing the code of the differential multi-valued image and referring to both the code and the defect candidate image Pi.

FIG. 5 is a schematic diagram showing the principle of specifying the type of the defect candidate. In FIG. 5, images P, Q, R,
S and T each represent the same image as the image of the same reference numeral shown in FIG. The images S and T are obtained by subtracting the repetition unit of the next cycle from the repetition unit of one cycle before. Therefore, the value is negative in the image portion corresponding to the black defect candidate in the repetition unit of the previous cycle, and is positive in the image portion corresponding to the white defect candidate. Conversely, the value is positive in the image portion corresponding to the black defect candidate in the next cycle repetition unit, and negative in the image portion corresponding to the white defect candidate. By performing binarization so that a portion having a negative sign in the image S has a value “1”, a code image L expressing a negative sign is obtained. Similarly, a binarized code image M is obtained such that a portion having a negative sign in the image T has a value “1”. Further, by calculating the logical product of the inverted image of the code image M and the code image L, the image N
Get. By calculating the logical product of the image N and the image W (FIG. 4), an image expressing only the white defect candidates appearing in the image Q is obtained. By repeating the above operation for each repetition unit, the position of only the white defect candidate can be specified. That is, the type of the defect candidate can be specified in addition to the position of the defect candidate.

Based on this principle, the defect position specifying / defect type block 40 first binarizes the difference multi-valued image obtained by the difference circuit 22 so that the image portion having a negative sign has the value "1". The obtained encoded image is obtained from the difference circuit 22. The code image is delayed by a predetermined line and a predetermined pixel by the line / pixel delay 51 to adjust the timing with the defect candidate image Pi. Further, the code image whose time has been adjusted is inverted by the inversion circuit 52,
The logical product with the defect candidate image Pi is calculated by the logical product circuit 53. The image PW obtained by the operation represents only white defect candidates.

On the other hand, the logical product of the code image output from the line / pixel delay 51 and the defect candidate image Pi is calculated by the logical product circuit 54 without passing through the inversion circuit 52, so that only the black defect candidate is calculated. Image P to be expressed
B is obtained. These two images are displayed in the defect detection block 6
0.

[5. Defect Detection Block] The defect detection block 60 is provided with two systems of line memories 61a and 61b and two systems of defect detection circuits 62a and 62b corresponding to the images PW and PB, respectively. FIG.
FIG. 3 is a block diagram showing an internal structure of a line memory 61a and a defect detection circuit 62a. The line memory 61b and the defect detection circuit 62b also have the same structure.

The line memories LM1 and LM2 store the image PW
Are delayed by one line, and D flip-flops DF1 to DF
F9 delays the image one pixel at a time in synchronization with the clock signal. Accordingly, the outputs of the D flip-flops DF1 to DF9 are 3 pixels × 3 in the main scanning direction X and the sub-scanning direction Y.
The image PW is two-dimensionally developed in the range of the pixel. The AND circuit AND1 selects 2 pixels × 2 pixels from the 3 pixels × 3 pixels and calculates the logical product of those images. The AND circuit AND1 outputs the value “1” only when any of the input four-pixel images has the value “1”. Therefore, when the defect candidate is large enough to include these four pixels, the AND circuit AND1 outputs a value “1” at a certain point in the scanning process. That is, the AND circuit AND1 detects a defect having a size of 2 pixels × 2 pixels or more from the defect candidates. Similarly, the AND circuit AND2 detects a defect having a size of 3 pixels × 3 pixels or more. Outputs of these AND circuits AND1 and AND2 are input to the selection circuit SEL. The image for one pixel is also input to the selection circuit SEL at the same time. This image is
This corresponds to a detection signal of a defect having a size of one pixel or more.

The selection circuit SEL selects one of these three inputs based on a selection signal transmitted from the microprocessor unit 70, and stores it in the defect information storage circuit MEM. A coordinate signal is simultaneously input to the defect information storage circuit MEM from the microprocessor unit 70 in synchronization with scanning for each pixel. Therefore, the defect information storage circuit MEM
Is 1 pixel or more, 2 pixels × 2 pixels or more, or 3 pixels × 3
A defect having a size equal to or larger than a pixel is stored together with its coordinates.

[6. Modification] In this embodiment, nine D flip-flops are arranged in the defect detection circuit. However, a larger defect size can be set by further increasing the number of D flip-flops. Also, any D
By selecting the outputs of the flip-flops and calculating their logical product, a defect of any shape can be detected.

In the above embodiment, the defect candidate image is divided into two systems corresponding to the white defect candidate and the black defect candidate, and the two systems of line memories 61a and 61b and the defect detection circuits 62a and 62b Each was processed. The line memory and the defect detection circuit may be configured as one system, and after processing the defect candidate image Pi with these, the code image may be applied to separate the two systems corresponding to the white defect and the black defect. .

The edge image obtained by the edge extracting circuit 32 in the above embodiment may be subjected to an emphasis process.

[0037]

According to the inspection apparatus of the present invention, a mask image obtained on the basis of a multi-valued image of an inspection object having a periodic pattern is applied, so that an unnecessary image can be converted from a binary image representing a defect candidate. The part is removed, and only the masked image corresponding to the defect candidate is extracted. Based on the masked image, a defect is selected from the defect candidates to detect the defect. Therefore, the inspection apparatus of the present invention has an effect that the defect can be inspected without error.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an internal configuration of a comparison block, a mask generation block, a defect position identification / defect type block, and a defect detection block.

FIG. 2 is a block diagram showing an overall configuration of the inspection device according to the embodiment of the present invention.

FIG. 3 is a schematic diagram showing images Pa to Pm in the course of processing.

FIG. 4 is a schematic diagram showing the principle of specifying the position of the defect candidate.

FIG. 5 is a schematic diagram showing the principle of specifying the type of a defect candidate.

FIG. 6 is a block diagram showing an internal structure of a line memory 61a and a defect detection circuit 62a.

FIG. 7 is an explanatory view showing the principle of inspection by a conventional apparatus.

[Explanation of symbols]

 Reference Signs List 10 image input block (image input means) 21 delay circuit (first displacement means) 22 difference circuit (difference calculation means) 23 absolute value circuit (absolute value calculation means) 24 binarization circuit (first binarization means) 32) Edge extraction circuit (edge extraction means) 33 Binarization circuit (second binarization means) 34 Delay circuit (second displacement means) 35 AND circuit (AND operation means) 41 AND circuit (mask) Means) Pa multivalued image Pb delayed multivalued image (displacement multivalued image) Pc binary image (first binary image) Pd masked image Pj binary image (second binary image) Pk delayed binary image (Displacement binary image) Pm mask image

Claims (1)

(57) [Claims] 1. An apparatus for inspecting a defect in an inspection object in which a pattern is repeated at a constant period, wherein: (a) an image input means for obtaining a multi-valued image having a gradation corresponding to the brightness of the inspection object (B) first displacement means for obtaining a displaced multi-valued image obtained by displacing the multi-valued image by an integral multiple of the period in a direction in which the pattern is repeated; (E) a difference calculating means for calculating a difference from the value image to obtain a differential multi-valued image; (d) an absolute value calculating means for calculating an absolute value of the differential multi-valued image to obtain an absolute multi-valued image; Comparing the value in the absolute multi-valued image with a predetermined first threshold,
By binarizing according to the comparison result, the first 2
First binarization means for obtaining a value image, (f) edge extraction means for obtaining an edge image representing an edge portion in the multi-valued image obtained by the image input means, and (g) a value in the edge image. A second binarizing means for comparing with a predetermined second threshold value and binarizing according to the comparison result to obtain a second binary image; and (h) the second binary image And (i) a logical product of the second binary image and the displaced binary image. , And
AND operation means for obtaining a mask image; (j) mask means for calculating an AND operation between an inverted image of the mask image and the first binary image to obtain an image to be masked; A detection unit for detecting a defect in the inspection object based on an image.