JPH03252546A - Wiring pattern inspection device - Google Patents

Abstract

PURPOSE:To classify and detect various kinds of line abnormality with simple constitution without any complicate positioning by deciding feature information imparted with a label number produced on a substrate to be inspected with a relative position to previously stored information. CONSTITUTION:A wiring pattern formed on a printed board 101 is converted photoelectrically by an image input means 102 and the obtained gradation image is subjected to binarization 105, while the wiring pattern is deleted from the background of each picture element one by one picture element, the process is repeated a predetermined number of times as to all picture elements to perform a line thinning process 106, thereby outputting a skeleton image. Then a feature extracting means 107 scans this image within (n)X(m) scanning windows and refers to a look-up table to extract the features of the wiring pattern at its end terminal, T branch, and terminal and the numbering of the feature information is carried out. This feature information is extracted and stored in a feature information storage means 108 by using a conforming printed board 101 and a decision processing means 109 refers to the information as the relative position to the information on the board 101 to be inspected to output only a real flaw.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a wiring pattern inspection device for inspecting wiring patterns on printed circuit boards, photomasks, etc. for defects.

2. Description of the Related Art Conventionally, inspection for defects in printed circuit boards and the like has relied on human visual inspection. However, as products become smaller and lighter, the wiring patterns of printed circuit boards are becoming increasingly finer and more complex. Under these circumstances, humans can inspect extremely detailed wiring patterns while maintaining high inspection accuracy.
Moreover, it has become difficult to continue testing for long periods of time, and automation of testing is strongly desired.

As a method for detecting defects in wiring patterns, Jorge, C., S., Anil K., and J.
, C,5anz and Anil K, Jai
n: ””Machine-vision tech
hiques (or in spection of
printed wiring boards and
thick-filemcircuits'', 0pt
icl 5ociety of america,
Vol.

3, No, g/september, I) I) 1465
~1482.1986) have introduced a number of methods, and these mainly include the design rule method and the comparison method.
It can be classified into two methods. However, these methods have advantages and disadvantages.

Among them, an interesting method with a promising future is Jonr, Mandeville (Jonr, Mandeville: “Nov
e 1method for analysis of
"printed circuit images",
IBM J,Res,DEVELOP,,VOL
, 29, no.

1, JANUAPY, 1985),
We have proposed a method for detecting defects in wiring patterns by shrinking or expanding binarized image data and then thinning the data.An example of this method will be described below.

FIG. 6 shows the flow of defect detection processing. (a)-(d
) shows the detection of a disconnection, and (e) to (h) show the detection of a short circuit.

(a) shows a defect image, where point B and point C are fatal defects such as line width abnormality or disconnection, and point 8 is not considered a defect. In the first step (b), image shrinkage processing (processing to remove one pixel from the periphery) is performed. This process causes the defect b to become a disconnection. As the second step, thinning processing (processing to remove pixel by pixel from the periphery until it becomes a single line) is performed. As a result, the wiring pattern becomes a single line. As the third step, In d), scan the 3X3 logic mask and create LtJT (look
Detect defects while referring to
Point b and point C can be detected as disconnections.

Furthermore, the junction point between the terminal portion and the wiring pattern is also detected.

Next, regarding short circuits and line abnormalities (e) to (h)
This will be explained along the flow of processing.

(e) shows a defect image, in which point b and point C are considered to be fatal defects of abnormalities between lines and short circuits. In the first step (f), image dilation processing (inflating one pixel at a time starting from the surrounding pixels) is performed, thereby bringing point pb into a short-circuit state. In the second step (g), thinning processing is performed to make -1 lines. In the third step (h), defects are detected by scanning a 3×3 logic mask and referring to an LUT (look up table), and points b and C can be detected as T-branches, that is, short circuits. In the manner described above, wire breaks, line width abnormalities, short circuits, and line spacing abnormalities can be detected.

Regarding image processing methods such as thinning processing and dilation processing, please refer to "Fundamentals of Image Recognition [1]" by Shunji Mori and Yuko Itakura.
'', which is described in detail in Ohmsha, so a detailed explanation is omitted.

Problems to be Solved by the Invention Now, a method has been described in which a binarized image is contracted or expanded to promote defects, thinned, and then a 3×3 logical mask is scanned to detect defects. This method can be said to be a promising method as it can reliably detect defects.

However, this method has problems, such as the inability to distinguish between short circuits and design problems at T-branches. It has also been proposed to learn the coordinates of the T-branch in advance using a non-defective board, and then compare the test board with the non-defective board to distinguish whether the T-branch is caused by a short or by design. However, depending on the method of mounting the boards, the positional error of wiring patterns between boards is said to be ±0.3 to 0.6 aua, and alignment with good quality boards is also a big problem.

In view of the above problems, the present invention provides a wiring pattern inspection device that has a simple configuration and can classify and detect various line abnormalities without complicated positioning.

Means for Solving the Problems In order to solve the above problems, the technical solution of the present invention includes an image input means for photoelectrically converting a wiring pattern formed on a printed circuit board, and a grayscale image from the image input means.
a binarization means for converting into a value image; a thinning means for repeatedly thinning all pixels a predetermined number of times while removing one pixel from the background of the wiring pattern to output a skeleton image; and a thinning means for outputting a skeleton image. A feature extraction means that scans the image with an nXm scanning window and refers to a lookup table to extract features of the wiring pattern such as the termination, T-branch, and terminal of the wiring pattern, and also numbers (labels) the extracted feature information. and feature information storage means for extracting and storing the numbered feature information from the feature extracting means on non-defective printed circuit boards in advance, and the feature information storage means for storing the numbered feature information from the printed circuit board to be inspected. A determination processing means is provided for outputting only true defects while referring to their relative positions with the numbered feature information from.

Function The present invention first photoelectrically converts a wiring pattern formed on a printed circuit board, and converts the obtained grayscale image into a binary image using a binarization means. Using a binary image, thinning processing is repeated zero times to remove one pixel from the background of each pixel of the wiring pattern to obtain a thinned image (skeleton image).

When the pixel of interest is at the skeleton image position, the n x m scanning window is scanned and the features of the wiring pattern such as the termination, T-branch, terminal, etc. of the wiring pattern are extracted by scanning the n x m scanning window and referring to the lookup table, as well as the detected features. By numbering the information and aligning it with the relative position of each numbered feature information from the feature information storage means learned in advance using a good board, complicated processing for position correction becomes unnecessary. .

EXAMPLE A first example of the present invention will be described below with reference to FIG.

FIG. 1 is a block diagram showing a first embodiment of the wiring pattern inspection apparatus of the present invention. In FIG. 1, 101 is a printed circuit board, 102 is a diffuse illumination device 104 such as a ring-shaped light guide, and an imaging device 10 such as a CCD camera.
105 is a binarization means for converting a grayscale image into a binary image; 106 is a thinning processing means for removing one pixel from the background using the binary image; 107tj is a thinning processing means 106; 108 is a feature extraction means for extracting and numbering the features of the wiring pattern from the thinning processed image (skeleton image); 108 is a feature information storage means for storing feature information (learning data) of a non-defective board; 109 is a feature of the board to be inspected A determination processing means for determining a true defect from information and learning data in the feature information storage means 108 is shown.

The operation will be explained below based on FIG.

A wiring pattern formed on a printed circuit board 101 is illuminated with a diffuse illumination device 104 such as a ring-shaped light guide, and the image input means 102 equipped with an imaging device 103 such as a CCD camera (one-dimensional or two-dimensional) is used to determine the shading. Input as an image. In this embodiment, since the following description will be made using a Rusk scan image, an example will be shown in which a one-dimensional CCD camera is used as the imaging device 103. In order to separate the background and the wiring pattern from the grayscale image obtained by the image input means 102, the image is compared with an arbitrary threshold value by the binarization means 105 and converted into a binary image. Using the binary image from the thinning processing means 106Fi and the binarization means 105, the thinning process of removing one pixel at a time from the background side of the wiring pattern is performed zero times, and a thinned image (skeleton image) is output. The feature extraction means 107 scans the skeleton image from the thinning processing means 106 with an n×m scanning window, and extracts feature information such as the termination, T-branch, and terminal of the wiring pattern from the state of eight pixels surrounding the pixel of interest. and numbering (labeling). The feature information storage means 108 stores the numbered feature information from the feature extraction means 107 on non-defective boards, and is read out when testing the test target board. The determination processing means 109 calculates the numbered characteristic information of the terminal-T branch and terminal of the wiring pattern from the characteristic extraction means 107 and the numbered characteristic information of the non-defective board from the characteristic information storage means 108. The true defect is determined from the relative position.

By repeating and sequentially performing the above operations, the entire surface of the printed circuit board 101 can be inspected. This series of operations is performed synchronously by appropriate signals.

Next, the thinning processing means 106, the feature extraction means 107, the feature information storage means 108, and the determination processing means 109 will be explained in more detail.

In the thinning process, a thinned image (skeleton image) is obtained by repeating the process of moving the wiring pattern one pixel from the outside 0 times. This will be explained below using the following.

A binary image is scanned with a 3×3 scanning window as shown in FIG. 2(b), and when the pixel of interest (center pixel * of the window) is 1, depending on the states of the eight neighboring pixels d1 to d8, It is determined whether or not to convert the pixel of interest to O (that is, erased) using an LUT, and the deletion determination of the pixel of interest is processed in four steps. The reason for this is to prevent erasure of patterns with even pixel width.
LUTs (A) to LUTs shown in Figure 2 (C) to (f)
In (D), patterns for cutting from the top, bottom, left, and right are registered.

FIG. 2(a) shows a detailed block diagram of a thinning processing means for removing one pixel from the background side of a wiring pattern, and will be described below.

The binary image 201 from the binarization means 105 is input to the line memory 202 for line delay and the 3×3 scanning window 203, and is transferred while taking the timing of the pixel synchronization signal, although it is not shown in the figure. It's something to do. The output of the 3×3 scanning window 203 is converted into a LUT which is a lookup table.
(A) 204 to determine whether to erase the pixel of interest. The same process is repeated 4 times in cascade to output a skeleton image 215 with one pixel removed.If you perform the same process for any number of pixels you want to remove, you can obtain the thinned side @ (skeleton image @). .

Next, a detailed block diagram of the feature extraction means 107 is shown in FIG. 3, and will be explained below.

The feature extracting means 107 detects features such as the termination, T-branch, and terminal of the wiring pattern using the skeleton image from the thinning processing means 106, and scans the n× scanning window to detect the peripheral 8 of the pixel of interest. It is detected based on the state of the pixel. In this embodiment, the scanning window will be described as 3×3.

In the figure, a skeleton image 301 from a thinning processing means 106 is transferred to a line memory 302 and a 3×3 scanning window 3.
03, the states of the pixel of interest and eight surrounding pixels from the 3×3 scanning window 303 are determined by the LUT, and the type 308 of the detected feature is output. LUT i
For example, by preparing a reference table as shown in Fig. 3(b) to (ri), it is possible to distinguish between terminal tab breaks, T-branches, terminals, etc. of the wiring pattern. At this time, a counter 305 assigns a label number 309 to the pixel of interest, for example, in the order of occurrence.By feature extraction, a synchronization signal 307, etc. is input, and the coordinate data generator 306 generates coordinate data 31 of the pixel of interest.
Outputs 0.

Next, FIG. 4 shows a processing flow of the determination processing means 109, and Tables 1 and 2 below show examples of characteristic information extracted from the characteristic information storage means 108 and the board to be inspected. FIG. 5 shows an example of characteristic information and defect detection, and will be described below.

1st table: Characteristic extraction of non-defective substrates 2nd table: Characteristic extraction of substrates to be measured The judgment processing means 109 performs judgment processing in accordance with the processing flow shown in FIG. 4 to judge true defects. In the first step, the characteristic information storage means 108-
Read the characteristic information of the same label number from . In the second step, it is determined whether the type of feature information matches and whether the difference between the relative coordinates of the inspected board and the relative coordinates of the non-defective board is within an arbitrary tolerance value. If the determination result is Y, the characteristic information is registered, so it is not determined to be a defect. As the third step,
If the determination result is N, it is notified as a true defect and the offset value of the label number is updated.

This is to make the label number from the board under test the same as the label number of the non-defective board.

Note that Table 1 and Table 2 above respectively show format examples of the feature extraction information of the feature information storage means ios and the feature extraction information of the board to be inspected. The characteristic information in the characteristic information storage means 108 is for storing characteristic information such as terminations, T-branches, terminals, etc. of wiring patterns that do not include defects on non-defective substrates, and is read out when inspecting the substrate to be inspected.

FIG. 5 shows the wiring patterns of the characteristic points of the non-defective board and the characteristic points of the board to be inspected. FIG. 5(a) shows the feature points of a non-defective board, and the feature information storage means 108 stores information as shown in Table 1. FIG. 5(b) shows a wiring pattern including a defect on the board to be inspected, and characteristic information as shown in Table 2 is detected by the characteristic extraction means 107.

Effects of the Invention As described above, the effect of the present invention is to obtain a skeleton image by repeating the process of removing one pixel from the background side of the wiring pattern 0 times using a binary image.
Scanning is performed using a xm scanning window to extract characteristic information such as terminal ends, T-branches, terminals, etc., and label numbers are assigned in the order of occurrence. The learning is performed in advance using a non-defective board and stored in the characteristic information storage means.

By determining the label-numbered feature information generated on the board to be inspected based on the relative position of each label-numbered feature information from the feature information storage means, true defects can be detected without the need for complicated alignment. It becomes possible to detect.

[Brief explanation of drawings]

FIG. 1 is a block wiring diagram of a wiring pattern inspection device according to an embodiment of the present invention, and FIG. 2 is a detailed block wiring diagram of a thinning processing means in the same device, and FIGS.
is a diagram showing the state of thinning processing, FIG. 3(a) is a detailed block diagram of the feature extraction means in the same device, and FIG.
b) to (i) are diagrams showing features extraction.

Claims (1)

[Claims] An image input means for photoelectrically converting a wiring pattern formed on a printed circuit board; a binarization means for converting a grayscale image from the image input means into a binary image; A thinning processing means that repeats thinning processing on a pixel a predetermined number of times and outputs a skeleton image; and a thinning processing means that scans the skeleton image with an n×m scanning window and refers to a lookup table to determine the end of the wiring pattern.・Feature extraction means for extracting the characteristics of the wiring patterns of T-branches and terminals and numbering the extracted feature information, and a feature for extracting and storing the numbered feature information from the feature extraction means in advance on a non-defective printed circuit board. information storage means; and a determination processing means for outputting only true defects while referring to the numbered feature information from the printed circuit board to be inspected as a relative position of the numbered feature information from the feature information storage means. Equipped with wiring pattern inspection equipment.