JP2712803B2 - Wiring pattern inspection equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring pattern inspection apparatus for inspecting a wiring pattern of a printed circuit board or a photomask for defects.

2. Description of the Related Art Conventionally, inspection for defects of printed circuit boards and the like has relied on visual inspection by humans. However, as products become smaller and lighter, wiring patterns become finer and more complex. In such a situation, it is difficult for a human to keep a very fine wiring pattern for a long time while maintaining high inspection accuracy, and automation of the inspection is strongly desired.

As a method for detecting a defect in a wiring pattern, George L. et al. C. San and Anil Jane (Jorge LCSanz a
nd Anil K. Jain: “Machine-vision techniques for in
spection of printed wiring boards and thick-film
circuits ", Optical Society of America, Vol.3, No.9, se
ptember, pp. 1465-1482, 1986) introduces a number of methods, which can be roughly classified into two methods, a design rule method and a comparison method. However, these methods have advantages and disadvantages.

Among them, one promising and interesting method is Jon R. Mandevile: “Novel method f
or analysis of printed circuit images ", IBM J. Res.D
EVELOP., VOL.29, NO.1, JANUARY, 1985)
A method for detecting a defect in a wiring pattern by contracting or expanding the quantified image data and then thinning the same has been proposed, which will be described below as a conventional example.

FIG. 9 shows the flow of the process of defect detection. (A) ~
(D) shows a disconnection detection process, and (e) to (h) show a short-circuit detection process.

(A) shows image data including a defect. Points b and c are fatal defects due to abnormal line width and disconnection, and point a is not a defect. In the first step (b), an image contraction process (a process of removing one pixel from the periphery) is performed. As a result of this processing, the defect at point b is broken and the defect is exaggerated. In the second step (c), a thinning process (repeating the process of removing one pixel at a time from the periphery until a single line is performed) is performed. Thus, the wiring pattern becomes one line. In the third step (d), a 3 × 3 logical mask is scanned to detect defects while referring to an LUT (Look Up Table).
Points b and c can be detected as broken lines (marked with □). Further, the junction between the terminal portion and the wiring pattern is also detected (marked with ○).

Next, regarding the short circuit and the line-to-line abnormality (e) ~
A description will be given along the flow of the process (h).

(E) shows image data including a defect, where point b and point c are fatal defects of line-to-line abnormalities and short circuits, and a
Points are not considered defects.

In the first step (f), the image is expanded (expanded one pixel at a time from the peripheral pixels), whereby point b is brought into a short state. (G) as the second step
Then, thinning processing is performed to make one line. In the third step (h), the 3 × 3 logical mask is scanned and the LUT
Defect detection is performed with reference to the (look-up table), and a short-circuit can be detected at the point b and the point c as a T branch (indicated by a square). Further, the junction between the terminal portion and the wiring pattern is also detected (marked with ○).

As described above, disconnection, line width abnormality, short circuit, and line-to-line abnormality can be detected.

The image processing methods such as thinning processing, dilation processing, and erosion processing are described in detail in Shunji Mori and Tsugako Itakura: "Basic Image Recognition [I]", Ohmsha, and will be described in detail. Omitted.

Problems to be Solved by the Invention As described above, the method of subjecting a binarized image to shrinkage or dilation, exaggerating the defect, thinning it, scanning a 3 × 3 logical mask, and detecting the defect has been described. This method is based on the design rule method and can be said to be a promising method that can reliably detect defects.

However, this method is based on the design rule method, and if there are multiple settings for line width violation and minimum line violation detection, multiple image contraction and expansion and thinning processing processes are required, and the hardware burden is increased. Increase. In addition, there is a problem that a short circuit of a thick wiring pattern that cannot be thinned or a short circuit between large lands cannot be inspected.

The present invention has been made in view of the above problems, and provides a wiring pattern detection device that can detect various line width abnormalities and can detect a large short and a land-to-land short with a simple configuration.

Means for Solving the Problems In order to solve the above problems, a technical problem of the present invention is to provide an image input unit for photoelectrically converting a wiring pattern formed on a printed circuit board, and a binary image from the image input unit. A binarizing means for converting to an image, and a thinning process that is repeated a predetermined number of times for all pixels while shaving one pixel at a time from the background side of the wiring pattern, and outputs a flag indicating the shaved target pixel and a skeleton image A first line-thinning means for outputting a distance-converted image in which a thinning step value is added as a distance value from the background with a flag indicating a target pixel removed from the first line-thinning means Image converting means, second thinning processing means for performing only the thinning processing a predetermined number of times on the skeleton image from the first thinning means, and skeleton images from the second thinning processing means. Edge extracting means for extracting an edge from the image and outputting an edge image;
A feature extraction means for comparing with at least one set threshold value and extracting a terminal end and a T-branch from the edge image from the edge extraction means; And a determination means for comparing the feature information from the feature extraction means with the reference data from the feature information storage means to detect only true defects.

The present invention photoelectrically converts a wiring pattern formed on a printed circuit board and converts the obtained grayscale image into a binary image by binarizing means.
Convert to value image. Using the binary image, a first thinning process is performed such that each pixel is removed one by one from the background of the wiring pattern, and a distance value from the background is given to the removed pixel to obtain a skeleton image and a distance-converted image. . The skeleton image is further subjected to only thinning processing by the second thinning processing means, and the edge is extracted to obtain an edge image. Processes and wiring patterns that require one or more distance-converted images to be compared with an arbitrary threshold value to detect line width anomalies, extract the terminal T-branch from the edge image, and perform line width measurement using the distance-converted images The process is divided into processes for detecting the connection relationship. The process of detecting the connection relationship of the wiring pattern is to perform only the thinning process a predetermined number of times, and extract the edges of the skeleton image to reduce the number of thinning processes to a thick wiring pattern into a line figure and to extract the features. In addition to detecting line width abnormalities, defects of large wiring patterns such as large shorts and shorts between lands can be easily inspected.

Embodiment 1 Hereinafter, a first embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram showing an embodiment of a wiring pattern inspection apparatus according to the present invention. In FIG. 1, reference numeral 101 denotes a printed circuit board; 102, an image input unit having a diffused illumination device such as a ring-shaped light guide 104; and an imaging device 103, such as a CCD camera; 105, a grayscale image into a binary image. Binarization means for converting, 106 is first thinning processing means for shaving one pixel at a time from the background using a binary image, 107 is distance image converting means for converting to the shortest distance value from the background, and 108 is further thinning Second thinning processing means for performing processing; 109, an edge extracting means for detecting an edge from a skeleton image; 110, a comparison with an arbitrary set threshold value using a distance-transformed image; 112 is a feature information storage means for storing feature information in advance as reference data on a non-defective substrate, and 111 is a feature for comparing and determining the feature information of the substrate to be inspected with the reference data from the feature information storage means 112. It is a stage.

 This will be described below with reference to FIG.

The wiring pattern formed on the printed circuit board 101 is illuminated by a diffused illumination device 104 such as a ring-shaped light guide, and C
The image is obtained as a grayscale image by the image input means 102 provided with the imaging device 103 such as a CD camera (one-dimensional or two-dimensional). In the present embodiment, a raster scan image will be described below, and an example in which a one-dimensional CCD camera is used as an imaging device will be described. In order to separate the background and the wiring pattern from the grayscale image obtained by the image input means 102, the image is converted into a binary image by comparing it with an arbitrary threshold value previously obtained by a density histogram or the like by the binarization means 105.

The first thinning processing means 106 receives the two
Using the value image, a thinning process for removing one pixel at a time from the background of the wiring pattern is performed for all pixels a predetermined number of times, and a flag indicating the removed target pixel and a skeleton image are output. The distance image conversion unit 107 includes a first thinning processing unit 106
Then, a distance conversion image is output in which a thinning step value is added as a distance value from the background of the wiring pattern with a flag indicating that the pixel is a target pixel that has been removed from the image. Second thinning processing means
108 performs only a predetermined number of thinning processes for further reducing the skeleton image from the first thinning processing unit 106 by one pixel from the background. The edge detecting means 109 extracts an edge of the skeleton image of the second thinning processing means 108 and outputs an edge image. The feature extracting unit 110 detects the line width abnormality of the wiring pattern by comparing the distance conversion image from the distance conversion unit 107 with one or more arbitrary setting thresholds, and detects the end and T from the edge image from the edge extraction unit 109. Detects branching and detects connection abnormalities such as disconnection or short circuit of the wiring pattern. The characteristic information storage unit 112 collects in advance the characteristic information such as the line width abnormality and the connection abnormality from the characteristic extraction unit 110 on a non-defective substrate, and stores it as reference data. The judging means 111 compares the characteristic information on the substrate to be inspected from the characteristic extracting means 110 with reference data stored in advance in the characteristic information storage means 112 and detects only true defects.

The above operation is repeated and sequentially performed, so that the entire surface of the printed circuit board 101 can be inspected. This series of operations is performed in synchronization with an appropriate signal.

Next, the first thinning processing means 106, the distance image converting means 1
07, the second thinning processing means, the edge extraction means 109, the feature extraction means 110, the determination means 111, and the feature information storage means will be described in further detail.

First, the thinning processing will be described. The thinning process is a process for obtaining a skeleton image (one line figure) by repeating a process of cutting one pixel at a time from the outside of the wiring pattern a predetermined number of times. A general method of the thinning process is shown in FIG. This will be described with reference to FIGS.

The binarized image is scanned in a 3 × 3 scanning window as shown in FIG. 2 (b), and when the pixel of interest (the central pixel * of the window) is 1, the binary image corresponds to the state of the neighboring eight pixels d1 to d8. It is determined using a LUT (lookup table) whether or not the target pixel is to be converted to 0 (that is, cut). The erasure judgment of the target pixel
The processing is performed separately for each direction. This is to prevent erasure of a pattern having an even-numbered pixel width. LUT (A) to LUT (D) register upper, lower, left, and right erasure determination patterns, respectively.
One example is shown in FIGS. 2 (c) to (f).

Next, the first thinning processing means will be described with reference to a detailed block diagram of the thinning processing for removing one pixel with reference to FIG.

The binary image 201 from the binarizing means 105 is stored in the line memory 20.
The data is input to the 2 and 3 × 3 scanning windows 203 and is transferred while taking the timing of the pixel synchronization signal (not shown). The output of the 3 × 3 running window 203 is input to the LUT (A) 204 in which the erasure determination table is written, and it is determined whether or not the pixel of interest is to be erased. The same processing is performed in cascade and processed in four directions, and a skeleton image cut by one pixel is output. One skeleton image can be obtained by performing the same processing a predetermined number of times.
Further, the binary image 201 is delayed by a delay memory 214 for synchronizing with the skeleton image 215, and a flag 217 indicating a target pixel removed by taking an exclusive OR 216 with the skeleton image 215 is output.

Next, FIG. 3 shows a detailed block diagram of the distance image conversion means 107, which will be described below.

First, the first thinning means 106 connects the one-pixel thinning processing block 301 to n stages, and outputs a flag indicating a skeleton image 312 and a target pixel removed from each stage of the one-pixel thinning processing block 301. doing. Range image conversion means 107
In this example, a distance conversion image 313 is output from the final stage, which is composed of a selector corresponding to each stage of the one-pixel thinning processing block 301 and a multi-level line memory.

At first, either the distance value “0” or “1” of the selector 302 is selected by the flag from the one-pixel thinning processing block # 1 and stored in the line memory 303. That is, if the flag is “1”, the distance value selects “1”. Next, the selector 304 selects either the data from the line memory 303 or the distance value “2” with the flag from the one-pixel thinning processing block # 2, and combines the data with the preprocessing result. By repeating this processing up to the one-pixel thinning processing block #n, a distance conversion image 313 can be finally obtained as a synthesis result of the distance values obtained in each stage.

Next, FIG. 4 shows a detailed block diagram of the second thinning processing means 108, which will be described below.

Basically, it is the same as the first thinning processing means. The difference is that there is no need to output a flag indicating that the line has been cut to perform only the thinning process, and a description thereof will be omitted.

Next, FIG. 5 shows a detailed block of the edge extracting means 109, which will be described below.

The skeleton image 415 from the second thinning processing means 108 is input, and 3 × 3 is input to the line memory 501 and the 3 × 3 scanning window 502.
Mask processing is performed with the PLD (programmable logic device) 503. The PLD 503 constitutes an edge extraction port magic. The edge extraction is usually performed by detecting a pattern of a target pixel and its surrounding pixels, and when the output is gxy, the PLD 503 is configured by the following logical expression (1).

In the case of an 8-connected edge image gxy = fxy · (a · c · e · g) (1) The logical formula in the case of a 4-connected edge image is shown below for reference.

In the case of a four-connected edge image gxy = fxy · (a · b · c · d · e · f · g · h) Next, FIG. 6 shows a detailed block diagram of the feature extracting unit 110, which will be described below.

The feature extraction unit 110 detects line width abnormality from the distance conversion image and connection abnormality detection from the edge image. First, detection of a contact abnormality from an edge image will be described.
The mask processing is performed by the line memory 601 and the 3 × 3 scanning window 602 and the LUT 603. The LUT 603 detects a target pixel and its surrounding pixels using a pattern. The detection pattern of the T branch 604 and the detection pattern of the end point 605 are tabulated.

Next, detection of a line width abnormality will be described. The basic idea is to detect the skeleton position by mask scanning on the skeleton image, measure the line width at that time, and compare it with the measurement threshold. The delay memory 606 and the delay memory 613 are for synchronizing with T branch / end point detection. Skeleton image 31 from first thinning processing means
2 is input, the line memory 614, the 3 × 3 scanning window 615, and the LUT 61
The mask processing is performed by 6 and the skeleton is detected. LUT
In 616, a table of skeleton detection patterns from the pattern of the target pixel and its surrounding pixels is tabulated. To measure the line width, the distance conversion image 313 from the distance image conversion unit 107 is input, the line memory 607, the 3 × 3 scanning window 608, and the line width calculation are performed.
In step 609, the line width is calculated by mask processing.
There are various methods for the line width calculation 609, but in this embodiment, the method (2) of adding the average distance of the distance value of the target pixel and the distance values of the eight pixels around the target pixel is adopted.

Line width W = fxy + 1/8 (Σdi + 0.5) (2) (di: distance value of d1 to d8 peripheral pixels, fxy: distance value of the pixel of interest) Compare the line width violation 6
11 is to be detected. Further, in the present embodiment, one threshold value is compared, but a plurality of threshold values such as a minimum line width and a maximum line width can be easily set. As the feature information, coordinate data is output together with the types of features described above.

Next, the characteristic information storage unit 112 and the determination unit 111 will be described.

The feature information storage unit 112 collects in advance the feature information from the feature extraction unit 110, such as line width abnormalities and connection abnormalities, on non-defective substrates and stores them as reference data.

The determination unit 111 compares the feature information on the substrate to be inspected from the feature extraction unit 110 with reference data previously stored in the feature information storage unit 112 and detects only true defects.
FIG. 7 shows the processing flow. (A) When the characteristic information of the substrate to be inspected is notified, (b) comparison is made with the reference data from the characteristic information storage means 112. (c) If they match, it is determined as a good product. It is determined as a defect.

Next, a processing example of the present invention will be described using the processed image of FIG.

FIG. 8 (a) shows an example of a distance-converted image subjected to distance conversion, and FIG. 8 (b) shows an example of a line width abnormality obtained by feature extraction. In the present embodiment, a line width abnormality of 7 pixels or less and a maximum line width of 13 pixels or more are detected as line width abnormalities. FIG. 8 (c) shows an example of an image obtained by detecting edges from a skeleton image.

Extracting edges and extracting features from skeleton images
By detecting the junction indicated by the mark as a T-branch,
Large shorts and shorts between lands can be easily detected.

Effect of the Invention As described above, the present invention performs the first thinning processing such that each pixel is removed one by one from the background of the wiring pattern, and assigns a distance value from the background to each of the removed pixels to obtain a skeleton image. Obtain a distance-converted image and detect a line width or more. Further, only the thinning processing is performed on the skeleton image by the second thinning processing means, the edge is extracted and an edge image is obtained, and the connection relationship between the end point and the wiring pattern such as the T branch is detected. In other words, the processing is divided into a process that requires the measurement of the line width based on the distance conversion image and a process that detects the connection relationship between the wiring patterns. The process of detecting the connection relation of the wiring pattern further includes performing only the thinning process a predetermined number of times, and extracting a feature of the thick wiring pattern into a line figure with a small number of thinning processes by extracting edges of the skeleton image. In addition to the detection of an abnormal line width, a defect of a large wiring pattern such as a large short circuit and a short circuit between lands can be easily inspected.

[Brief description of the drawings]

FIG. 1 is a block diagram of a wiring pattern inspection apparatus according to an embodiment of the present invention, and FIG. 2 is a diagram showing a detailed block connection diagram and a thinned pattern of a first thinning processing means in the apparatus. 3 is a detailed block connection diagram of the distance image conversion means in the apparatus, FIG. 4 is a detailed block connection diagram of the second thinning processing means of the apparatus, and FIG. 5 is a detailed block connection of the edge extraction means of the apparatus. FIG. 6, FIG. 6 is a detailed block connection diagram of the feature extracting means of the apparatus, FIG. 7 is a processing flowchart of the judging means, FIG. 8 is a view showing a processing state of the present invention, and FIG. It is a figure showing a state of processing of an inspection device. 101 ... Printed circuit board, 102 ... Image input means, 103 ...
Image pickup device, 105 binarization means, 106 first thinning processing means, 107 distance image conversion means, 108 second thinning processing means, 109 edge extraction means, 110 ... characteristic extracting means, 111 ... determining means, 112 ... characteristic information storing means, 20
2 ... line memory, 203 ... 3x3 scanning window, 204 ... LU
T.

 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Hidehiko Kawakami 3-10-1, Higashi-Mita, Tama-ku, Kawasaki-shi, Kanagawa Matsushita Giken Co., Ltd. (56) References JP-A-62-131391 (JP, A) JP-A-1-106180 (JP, A) JP-A-63-58582 (JP, A) JP-A-63-184046 (JP, A) JP-A-62-197752 (JP, A) JP-B-62-18956 ( JP, B2)

Claims (1)

(57) [Claims] An image input means for photoelectrically converting a wiring pattern formed on a printed circuit board; a binarizing means for converting a grayscale image from the image input means into a binary image; First thinning processing means for repeatedly thinning a predetermined number of times for all pixels while shaving one pixel at a time and outputting a flag indicating a shaved target pixel and a skeleton image; A distance image conversion unit that outputs a distance conversion image in which a thinning step value is added as a distance value from the background with a flag indicating a target pixel that has been removed from the processing unit, and a skeleton image from the first thinning unit And a second thinning processing means for performing only a thinning processing a predetermined number of times, and an edge extracting means for extracting an edge from the skeleton image from the second thinning processing means and outputting an edge image A feature extraction unit that compares the distance conversion image from the distance image conversion unit with one or more arbitrary set thresholds and extracts a terminal end and a T-branch from the edge image from the edge extraction unit; Feature information storage means for previously collecting feature information from a non-defective substrate and storing the same as reference data, and comparing only the feature information from the feature extraction means with the reference data from the feature information storage means to detect only true defects. A wiring pattern inspection device comprising a determination unit.