JP2819905B2 - Wiring pattern inspection equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring pattern inspecting apparatus for inspecting a wiring pattern on a printed circuit board or a photomask for defects.

[0002]

2. Description of the Related Art Conventionally, inspection for defects of a printed circuit board or the like relies on a visual inspection by a human. However, as products become smaller and lighter, wiring patterns become finer and more complex. In such a situation, it is difficult for a human to keep a very fine wiring pattern for a long time while maintaining high inspection accuracy, and automation of the inspection is strongly desired.

As a method for detecting a defect in a wiring pattern, George L. et al. C. Saint and Anil. Kei. Jane (Jorge LCSanz and Anil K. Jain: "Machine-vision
techniques for inspection of printed wiring boards
and thick-film circuits ", Optical Society of Ameri
ca, Vol. 3, No. 9, september, pp. 1465-1482, 1986), etc., and a large number of methods are introduced, which can be roughly classified into two methods, a design rule method and a comparison method. However, these methods have advantages and disadvantages.

Among the promising and interesting methods,
John Earl. Mandeville (JonR. Mandevile: "Novel
method for analysis of printed circuit images ", IBM
J. Res. DEVELOP., VOL. 29, NO. 1, JANUARY, 1985), which proposes a method for detecting defects in wiring patterns by shrinking or expanding the binarized image data and then thinning it. This will be described below as a conventional example.

FIG. 8 shows a flow of a defect detection process.
(A) to (d) show disconnection detection processing, and (e) to (e)
(H) shows a short detection process.

FIG. 1A shows image data containing a defect. Points b and c are fatal defects due to abnormal line width and disconnection, and point a is not a defect. In the first step (b), an image contraction process (a process of removing one pixel from the periphery) is performed. As a result of this processing, the defect at point b is broken and the defect is exaggerated. In the second step (c), a thinning process (repeating the process of removing one pixel at a time from the periphery until a single line is performed) is performed. Thus, the wiring pattern becomes one line. In the third step (d), the LUT is scanned by scanning the 3 × 3 logic mask.
The defect detection is performed with reference to the (look-up table), and the point b and the point c can be detected as a disconnection (marked with □). Further, the junction between the terminal portion and the wiring pattern is also detected (marked with ○).

Next, short-circuits and line-to-line abnormalities will be described with reference to the processing flows (e) to (h).

FIG. 3E shows image data including a defect. Points b and c are fatal defects of line-to-line abnormalities and short-circuits, and point a is not a defect.

In the first step (f), an image expansion process (expanding one pixel at a time from peripheral pixels) is performed.
As a result, the point b is short-circuited. In the second step (g), a thinning process is performed to make a single line.
In the third step (h), a 3 × 3 logic mask is scanned to detect a defect while referring to an LUT (look-up table), and a short circuit is detected as a point B and a point C as a T branch (marked with □). it can. Further, the junction between the terminal portion and the wiring pattern is also detected (marked with ○).

As described above, disconnection, line width abnormality, short circuit, and line-to-line abnormality can be detected. In addition, thinning processing
The image processing methods such as the expansion processing and the contraction processing are general methods of graphic processing, and thus detailed description is omitted.

[0011]

As described above,
A method has been described in which a binarized image is subjected to shrinkage or dilation processing, a defect is exaggerated, a thin line is formed, and a 3 × 3 logical mask is scanned to detect the defect. This method is based on a design rule method, and generally determines whether a feature such as a T-branch is due to a design or a defect by comparing it with reference data. However, in the manufacturing process, it is difficult to always maintain and maintain a stable pattern especially in the etching process, and the wiring pattern width is ± 20 to ± 40 with respect to the standard pattern.
In many cases, a tolerance of about% is provided. Therefore, in the thinning process, the way of forming a skeleton image is significantly different between a case where the wiring pattern of -20 to -40% is thinner and a case where the wiring pattern of +20 to + 40% is thicker. In this case, when compared with the reference data, the skeleton image may or may not be a single line, and T
The position coordinate of a branch or the like changes or becomes very unstable, so that the inspection apparatus has many false reports.

The present invention has a simple configuration in view of the above problems,
An object of the present invention is to provide a wiring pattern inspection apparatus capable of absorbing the instability of a manufacturing process such as an etching process and performing a stable inspection.

[0013]

The technical problem of the present invention to solve the above problems SUMMARY OF THE INVENTION includes an image input means for photoelectrically converting a wiring pattern formed on the PCB, shading from the image input means A binarizing means for converting an image into a binary image;
A thinning processing means for converting the image into a skeleton image condensed by n pixels by a predetermined number of pixels, and detecting a feature point such as an end and a T branch from the skeleton image from the pre-thinning processing means ;
First feature extracting means for extracting feature information comprising an identification code and coordinates of the feature point, and mn-th , n-th, and n + m-th stages from the thinning processing means on a standard non-defective substrate in advance.
Features such as terminal and T-branch from skeleton image of eyes
A second feature extraction unit for detecting points and further extracting feature information comprising an identification code and coordinates obtained by performing a logical product and a logical sum of feature points of each thinning stage number, and a feature from the second feature extraction unit. A feature information storage means for storing information as reference data; and a determination means for comparing the feature information from the first feature extraction means with the reference data from the feature information storage means to detect only true defects. It is.

[0014]

DETAILED DESCRIPTION OF THE INVENTION The present invention, a wiring pattern formed on the print substrate to photoelectric conversion, converts the grayscale image obtained by the binarization means binary image. A skeleton image connected by narrowing a predetermined n pixels while maintaining the connectivity from the background side of the wiring pattern is obtained, and the characteristic points such as the termination and the T branch are detected.
A first feature extraction is performed as feature information including a feature point identification code and its coordinates . In advance, feature points such as the end and T branch are detected from the skeleton images of the nth stage and the nth stage ± mth stage from the thinning processing means using a standard non-defective substrate,
Logical product and logical hydrated identification feature points of each thinning stages
Feature information consisting of the code and its coordinates as the second feature extraction
And store it as reference data. In the inspection target substrate, the first feature is extracted and compared with the previous reference data to detect only true defects, thereby absorbing the instability of the manufacturing process.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a block diagram showing an embodiment of a wiring pattern inspection apparatus according to the present invention. In FIG. 1, 10
Reference numeral 1 denotes a printed circuit board; 102, an image input unit including a diffused illumination device 104 such as a ring-shaped light guide; and an imaging device 103 such as a CCD camera.
Binarizing means for converting into a value image; 106, a thinning processing means for thinning one pixel at a time from the background; 107, a first feature extracting means for extracting features such as terminal and T branches from the skeleton image; 109, a standard non-defective substrate A second feature extraction unit for extracting features such as terminal end and T-branch from the skeleton image using
Reference numeral 110 denotes a feature information storage unit that stores the feature information from the second feature extraction unit as reference data, and 108 denotes a determination unit that compares features extracted from the substrate to be inspected with the reference data and detects only true defects. is there.

The operation of the wiring pattern inspection apparatus configured as described above will be described. First, a printed circuit board 101 to be inspected is imaged by an image input means 102 using a CCD camera or the like to obtain a grayscale image. In this embodiment, an example in which a CCD line sensor camera is used as the image input unit 102 will be described. The illumination system is not particularly limited, but it is well known that binarization can be easily performed by using a wavelength near 600 nm where the reflection luminance difference between the substrate (eg, glass epoxy) and the copper pattern is large. Recently, ultra-high brightness LEDs (for example, GaAlAs 660 nm)
Or InGaAlP (620 nm) is commercialized, and it can be said that arranging them on a line is also an effective illumination method. The obtained grayscale image is converted into a binary image by a binarizing means 105 at a threshold level previously obtained from a density histogram or the like. here,
The wiring pattern side is binarized to “1” and the base material side is binarized to “0”. The converted binary image is converted to thinning means 10
In step 6, a skeleton image narrowed by a predetermined number of n pixels while maintaining connectivity from the background side is obtained. First feature extraction means 107
Performs feature extraction such as termination and T-branch from the skeleton image from the thinning means 106. Second feature extraction means 1
In step 09, the terminal and the T-branch are extracted from the skeleton images of the nth and nth ± mth stages from the thinning means 106 on the standard non-defective board, respectively, and the logical product and the logical sum are extracted as the characteristic information. I do. The feature information storage unit 110 stores the feature information from the second feature extraction unit 109 as reference data. The judging means 108 compares the characteristic information from the first characteristic extracting means 107 with the reference data from the characteristic information storing means 110 on the substrate to be inspected, and detects only true defects. The detected defect information is not shown in FIG. 1, but is displayed on the terminal together with the coordinates, or is stored in a storage device, read out as needed, and notified to the operator. Repeat the above operation,
By sequentially performing the inspection, the entire surface of the printed circuit board 101 can be inspected. This series of operations is performed in synchronization with an appropriate signal.

Next, a thinning processing means 106, a first feature extraction means 107, and a judgment means 108 will be described with reference to FIGS.
• Second feature extraction means 109 and feature information storage means 1
10 will be described in more detail.

The thinning means 106 will be described in detail with reference to FIGS. FIG. 2 is a block diagram of the thinning means 106. In general, the thinning processing is performed by using a frame memory for one surface to perform thinning one pixel at a time while maintaining the connectivity from the background side of the wiring pattern a plurality of times or one pixel width in which all the wiring patterns are connected. This is repeated until a skeleton image is obtained. In addition, since this method requires a long processing time, a thinning unit for one-pixel processing is configured by hardware described later, and real-time processing can be performed by processing the thinning unit in an arbitrary-stage pipeline. Therefore, FIG. 2 inputs the binary image 201,
The thinning units 202 to 206 for one pixel process perform n-stage pipeline processing to obtain a thinned image 208 in real time. Further, in order to create the reference data, the thinning process # n-m-th stage, # n-th stage, and # n + m
The skeleton image from the stage is output, and is delayed by the memory 210 to synchronize the skeleton image nm-m20.
9, skeleton image n208 and skeleton image n +
m207 is obtained.

The thinning unit for one pixel processing will be briefly described below. The thinning process is a well-known image processing method of line graphic processing, and is described in, for example, "Tamura: Comparative Study on Thinning of Figures, IPSJ Image Processing Funding, 1-1 (1975)". We are comparing each method. FIG. 3 shows and describes a well-known thinning processing method as an example. FIG. 3 shows a case where the input binary image 301 is stored in a line memory 306, 3 ×
The mask processing composed of three scan windows 307 and LUTn 308 is divided into four subcycles 302 to 305 to perform processing and output a thinned image 309. Each subcycle has the same configuration and an LUT (lookup table) Only the content of

Next, FIG. 4A shows the first feature extracting means 1.
07 is shown in the detailed block diagram and described below. The first feature extracting unit 107 receives the skeleton image n401, and inputs the skeleton image n401 to the line memory 402, the 3 × 3 scanning window 403, and the LU.
FIG. 4 shows an example of an LUT in which a mask process is performed in T404 and a feature point is detected from a pattern of a target pixel and its peripheral pixels in a skeleton image n401.
4 (b) and FIG.
4 shows a branch detection pattern.

FIG. 5 shows a detailed block diagram of the second feature extracting means 109, which will be described below. The second feature extraction unit 109 receives the skeleton image nm 501 and receives a line memory 502, a 3 × 3 scanning window 503, and an LUT 504.
Detecting the end points 5 05 and T min Toki 5 06 by the mask processing with the. Similarly, for the skeleton image n and the skeleton image n + m, an end point and a T-branch are detected with the same configuration. In addition, each detected endpoint 505, 511, 517 and T-branch 506, 512,
The feature points 518 are provided by AND circuits 519 and 52 for each feature point.
End point is logical operations in 1 and the OR circuit 520, 522
5 23 and the end point 5 24 and T min Toki 5 25 and T-branch 5
26 is obtained.

Next, the characteristic information storage means 110 and the judgment means 108 will be described below with reference to FIG.

The characteristic information storage means 110 stores the characteristic information from the second characteristic extraction means 109 as reference data using a standard non-defective substrate in advance and is read at the time of inspection. The feature information from the second feature extraction means 601 is I
The information is stored in the first memory (feature information storage unit) 607 together with the coordinate information by the CPU 605 via the / F 603.

The determining means 108 determines that the characteristic information from the first characteristic extracting means 602 is
U is notified to detect a true defect by comparing with the reference data read from the first memory which is the feature information storage means.

FIG. 7 shows a processing flow of the judgment means 108 and will be described. Step (a) is notified to the CPU 605 every time feature information is generated from the first feature extraction unit.
In step (b), when the characteristic information is notified, the CPU 60
Reference numeral 5 reads reference data from the first memory 607. In step (c), the notified feature information and the X
Compare the Y coordinate with the feature. If they match, the process proceeds to step (d), and is judged as a non-defective product, and waits for notification of the next feature information. If they do not match, the process proceeds to step (e), where the defect information is determined as a defect, and the defect information is stored in the second memory together with the coordinate information, and a notification of the next feature information is awaited. This is repeated until one substrate is completed.
The defect information stored in the memory of the I / F 60 is read out.
9 to the confirmation device 610. Confirmation device 61
0 is not directly related to the present invention but is described for reference. Generally, current defect detection technology cannot completely detect only a defect, and the final defect detection is based on defect information. Is to reconfirm visually and to correct simple defects.

Next, the reference data will be described in more detail with reference to an example. Table 1 shows the relationship between the degree of etching and the number of thinning steps.
Indicates the degree of etching .

[0028]

[Table 1]

The thinning nm is a line width + 20% (etching is too small), and the thinning n is a line width ± 0% (etching standard).
And thinning n + m indicates a line width of −20% (excessive etching). In addition, ○ indicates that a T-branch or an end point was detected, and ● indicates that a finite number of thinnings could not be detected without a single pixel width. It can be seen that the end point has been detected. At the same time, a logical product and a logical sum of characteristic points of each number of thinning stages, which are features of the present invention, are shown. Also, as reference data ,
Table 2 shows an example of a data format including the coordinates (x, y) and the identification code (T branch or end point) .

[0030]

[Table 2]

Further, logical product and logic in the identification code
Table 3 shows the meaning of determination based on the combination of the bits of the sum .

[0032]

[Table 3]

Therefore, in the comparison judgment, when the logical product and the logical sum are "1 and 1", it is sufficient to directly determine the coincidence or non-coincidence in order to stably detect the logical product and the logical sum.
In the case of 0, 1 ", the line width is (2n + 1) × the number of thinning stages n.
In some cases, the detection is performed because of being close to the resolution, and in the other case, the detection is not performed. As the comparison determination, stable processing can be realized by determining both as non-defective products or excluding them from the comparison.

Although the present embodiment has been described for the case where the determination is made by a combination of the logical product and the logical sum of the characteristic points of each thinning stage number, the determination can be made only by the logical product or only the logical sum. Let me add that. Further, in the present embodiment, the first feature extracting means and the second feature means have been described separately, but the functions can be easily switched by only the second feature extracting means.

[0035]

As described above, according to the present invention, first, a wiring pattern formed on a printed circuit board is photoelectrically converted,
The obtained grayscale image is converted into a binary image by the binarizing means. A skeleton image connected by narrowing a predetermined n pixels while maintaining the connectivity from the background side of the wiring pattern is obtained, the terminal end and the T branch are detected, the identification code of the feature point and its coordinates
The first feature extraction of feature information consisting of Using a standard non-defective substrate in advance, feature points such as the end and T-branch are detected from the skeleton images of the nth and nth ± mth stages from the thinning processing means, and the logical product of the feature points of the respective thinning stages is detected. A second feature extraction is performed by using a logical sum of the identification code and its coordinates as feature information and stored as reference data. The first feature extraction is performed on the substrate to be inspected, and only the true defect is detected by comparing with the reference data, thereby absorbing the instability of the finite number of thinning processes from the allowable line width due to the manufacturing process. In addition, an inspection apparatus with few false alarms can be provided, and its effect is significant.

[Brief description of the drawings]

FIG. 1 is a block diagram of a wiring pattern inspection apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of a thinning unit which is a main part of the wiring pattern inspection apparatus in the embodiment.

FIG. 3 is a detailed block diagram of a thinning unit which is a main part of the wiring pattern inspection apparatus in the embodiment.

FIG. 4A is a block diagram of a first feature extraction unit which is a main part of the wiring pattern inspection apparatus in the embodiment; FIG. 4B is a conceptual diagram of an end point detection pattern of the wiring pattern inspection apparatus in the embodiment; FIG. 4 is a conceptual diagram of a T-branch detection pattern of the wiring pattern inspection apparatus in the embodiment.

FIG. 5 is a block connection diagram of a second feature extraction unit which is a main part of the wiring pattern inspection apparatus in the embodiment.

FIG. 6 is a block diagram of a feature information storage unit and a determination unit which are main parts of the wiring pattern inspection apparatus according to the embodiment;

FIG. 7 is a view showing a processing flow of a determination unit which is a main part of the wiring pattern inspection apparatus in the embodiment.

FIG. 8 is a diagram showing a flow of a conventional wiring pattern inspection process;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Printed circuit board 102 CCD camera 103 Image input means 104 Illumination means 105 Binarization means 106 Thinning means 107 First feature extraction means 108 Judgment means 109 Second feature extraction means 110 Feature information storage means 201 Binary images 202 to 206 Thinning processing unit 207 to 209 Skeleton image 210 Memory 301 Binary image 302 to 305 Thinning subcycle 306 Line memory 307 Scan window 308 LUT (lookup table) 309 Thin line image 401 Skeleton image n 402 Line memory 403 Scan window 404 LUT 405 Endpoint detection 406 T-branch detection 501, 507, 513 Skeleton images 502, 508, 514 Line memories 503, 509, 515 Scanning windows 504, 510, 516 LUT 505, 11, 517 Endpoint detection 506, 512, 518 T branch detection 519, 521 Logical product circuit 520, 522 Logical sum circuit 523, 524 Endpoint 525, 526 T branch 601 Second feature extraction means 602 First feature extraction means 603, 604, 609 I / F 605 CPU 606 CRT 607 First memory (characteristic information storage means) 608 Second memory (storage of defect information) 610 Confirmation device

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hidehiko Kawakami 3-10-1, Higashi-Mita, Tama-ku, Kawasaki-shi, Kanagawa Matsushita Giken Co., Ltd. (56) References JP-A-4-73759 (JP, A) Kaihei 4-3271 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G01B 11/00-11/30 G01N 21/88 H05K 3/00

Claims (1)

(57) [Claims] An image input means for photoelectrically converting a wiring pattern formed on a printed circuit board; a binarizing means for converting a grayscale image from the image input means into a binary image; Thinning processing means for converting into a skeleton image connected by narrowing a pixel by a predetermined n pixels while maintaining connectivity, and detecting a feature point such as an end and a T branch from the skeleton image from the pre-thinning processing means ; Its features
A first feature extraction unit for extracting feature information comprising an identification code and coordinates of each of the skeleton images of the nm-th, n-th and n + m-th stages from the thinning processing unit on a standard non-defective substrate. A second feature extracting means for detecting a feature point such as a terminal end and a T-branch, and further extracting feature information consisting of a logical product and a logical sum of the feature points of each number of thinning stages and an identification code and its coordinates; A feature information storage unit that stores feature information from the second feature extraction unit as reference data, and compares the feature information from the first feature extraction unit with the reference data from the feature information storage unit to determine only true defects. A wiring pattern inspection apparatus comprising: a determination unit for detecting.