JPH06203141A - Wiring pattern inspecting device - Google Patents

Abstract

PURPOSE:To accurately inspect the line width of a wiring pattern by giving the binary image data of a printed circuit board processing of fine lines, adding a distance label and providing a length measured value while referring to the distance label along the center line of the finely lined image. CONSTITUTION:A gradation image provided by photoelectrically converting the wiring pattern on a printed circuit board 101 is binarized by a binarizing means 105, fine line means 106 and 107 repeat processing for erasing the picture elements of the wiring pattern from the background side one by one while using this binary image and convert it to the fine line image. At such a time, erase position judging means 108 and 109 detect the position of the picture element to be erased by the correspondent fine line means and control the positions and order to erase the patterns with fine lines. Distance label adding means 110 and 111 and the distance labels to the erase positions at the same time as the erase of picture elements due to these fine lines, and a length measuring means 113 measures the line width of the wiring pattern while referring to this distance label along the center line of the finely lined image and detects the position offensive to the specified line width.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring pattern inspection device for inspecting a defective wiring pattern on a printed circuit board, a photomask or the like.

 2. Description of the Related Art As electronic components are mounted on printed boards with higher density, wiring patterns are becoming finer. Conventionally, visual inspections by humans have been performed to inspect defective printed circuit boards, but it is becoming difficult to maintain inspection accuracy for a long time while maintaining inspection accuracy due to fine wiring patterns. Automation is required.

 As a defect inspection method for wiring patterns, J. Elle. C. Sants and A. K. Jane (JLCSanz and AKjain, "Machine vision techniques for inspection of printed wiring boards and thinck-film circuits," J.Opt.Soc. Amer., Vo13, no.9, pp.1465-1482, Sept.1986) Many other methods have been introduced, and many methods classified as the design rule method or the comparative method have been proposed. Although these methods have merits and demerits, one of the most promising interesting methods in the future is JR Mandeville, "Novel Method for analysis of printed circuit image s," IBM J.Res.Develop., Vol.29, No. 1, pp. 73-86, Jan. 1985), which is a method of contracting or expanding binary image data and then thinning it to detect defects in a wiring pattern, which will be described below as a conventional example. FIG. 10 shows the procedure of defect detection processing. The figure (a)-(d) shows the detection procedure of a missing defect, and the figure (e)-(h) shows the detection procedure of a protruding defect.

 First, a method for detecting missing defects will be described with reference to the drawings. (a) shows a defect image. Points b and c are detected as fatal defects due to insufficient line width and disconnection, and point a is not detected as a defect. In the first step (b), the image is contracted (eroded) by a predetermined size to cut off the connection of points b.

As the second procedure, in (c), the pattern is thinned to a width of 1 pixel. As the third procedure, in (d), the connectivity of the thinned image is determined in the 3 × 3 local area (the position indicated by □ in the figure), and the points b and c are detected as broken lines. It is shown that the joint portion of the terminal portion and the wiring pattern (the position indicated by a circle in the figure) can also be detected as a feature point by the connection determination of the 3 × 3 local region.

 Next, a method for detecting a protruding defect will be described with reference to the drawings. (e) shows a defect image. Points b and c are detected as fatal defects due to abnormal line width and short circuit, and point a is not detected as a defect. In the first step (f), a new connection is generated at the point b by expanding the image by a predetermined size. As the second procedure, in (g), the pattern is thinned to 1 pixel width. As the third procedure, in (h), the connectivity of the thinned image is determined in the 3 × 3 local region (the position indicated by □ in the figure), and the points b and c are detected as branch points, that is, shorts. Line width thickening, wire breakage and short circuit can be detected by the above procedure.

 Problems to be Solved by the Invention The method of detecting defects by shrinking and expanding a binary image to enhance the features of defects and then thinning the lines to determine connection by 3 × 3 local regions has been described. This method can be said to be a promising method because it can detect defects surely by skillfully utilizing the design rule of the wiring pattern.

 However, it is not possible to classify short lines and broken lines or thick lines and shorts because the features of defects are promoted by shrinkage and expansion processes. In addition, when there are multiple violation line width settings, multiple image contraction, expansion, and thinning processing processes are required, which poses a problem that the burden on the hardware increases when implementing the device.

 In view of the above-mentioned problems, the present invention can perform an error-free inspection even when wiring patterns having a plurality of line widths exist on the same printed circuit board, and can detect defects such as disconnection and short circuit as well as line width inspection. It is possible to provide a wiring pattern inspection device capable of performing various defect inspections.

 Means for Solving the Problems In order to solve the above problems, the technical solution means of the present invention is to provide an image input means for optically detecting and photoelectrically converting a wiring pattern formed on a printed circuit board, and the image input means. Means for converting the grayscale image signal from the image into a binary image signal, first to nth thinning means for erasing the pattern pixel by pixel from the background side, and the first to nth thinning means The first to n-th erase position determining means for designating the position of the pixel to be erased in the means to each thinning means, and the first to nth erase position determining means for giving a distance label to the pixel position erased by the thinning. A distance measuring unit that measures the line width of the wiring pattern by referring to the distance label obtained from the nth distance labeling unit along the core line of the thinned image obtained by the distance labeling unit and the nth thinning unit. Steps and thinned images And endpoint detection means for detecting the end point of the pattern from the measured values according to the line and the measuring means, which is constituted from a branch detection means for detecting the branch of the wiring pattern from the core of the thinned image.

 Function The present invention firstly binarizes a grayscale image obtained by photoelectrically converting a wiring pattern formed on a printed circuit board, and thins and distance labels the binarized image to perform a thinned image. And the distance image is converted and the length measurement value is obtained by referring to the distance label along the core line of the thinned image, so that it is possible to easily inspect the line widths of multiple wiring patterns without being limited to the inspection of a specific line width. .

 Secondly, the 4-connected edge or 8-connected edge position of the pattern is specified as the position of the pixel to be erased by thinning, and the edge connection is switched in a predetermined order each time thinning is performed. By providing, it is possible to obtain a range image with a small error with a simple configuration.

 Thirdly, in the predetermined thinning repetition, the position of the pixel to be erased is specified by changing it to a position different from the 4-connected edge or 8-connected edge. A value can be given, and the accurate pattern width can be measured at the core position of the wiring pattern.

 Fourthly, various inspections can be performed in order to extract features such as branches and end points of the thinned image and to distinguish between abnormal wiring width of the wiring pattern and disconnection or short circuit.

 Embodiment One embodiment of the present invention will be described below with reference to FIG.

 FIG. 1 is a block diagram of a wiring pattern inspection apparatus according to an embodiment of the present invention. In FIG. 1, 101 is a printed circuit board, 102 is an image inputting means equipped with a diffused illumination device such as a ring-shaped light guide of 104 and an image pickup device such as a CCD camera, and 105 is a grayscale image. Binarization means for converting into a binary image, 106, 107 and thinning means for erasing the constituent pixels of the wiring pattern one by one from the outside, 108 and 109 for detecting the erasing position of the pixels of the thinning means. The erasing position determining means, 110 and 111 detect whether or not the pixel determined to be the erasing position in the erasing position determination has been erased by the thinning of that time, and give a distance label to the attention pixel position. Means, 112 is a defect detecting means for detecting a defect of the wiring pattern using the thinned image from the nth thinning means 107 and the distance image from the nth distance labeling means 111, and 113 is a core line of the thinned image. Along the distance label Length measuring means for measuring the line width of the line pattern, 114 is an end point detecting means for detecting the end point of the pattern from the core line of the thinned image and the length measurement value by the length measuring means, 115 is a wiring pattern from the core line of the thinned image The branch detection means for detecting the branch of the network is shown.

 The operation of the above configuration will be described below. A wiring pattern formed on the printed circuit board 101 is illuminated by a diffused illumination device 104 such as a ring-shaped light guide, and is input as a grayscale image by an image input means 102 including an image pickup device 103 such as a CCD camera. In this embodiment, an example in which a one-dimensional CCD sensor camera is used as the image pickup device will be shown. The binarizing means 102 compares the grayscale image obtained by the image inputting means 102 with a predetermined threshold value and converts it into a binary image in which the wiring pattern portion is 1 and the base material portion is 0. The first to n-th thinning means 106 to 107 use the binary image from the binarizing means 105 to erase the wiring pattern pixel by pixel from the background side (convert from 1 to 0). The process is repeated n times to convert to a thinned image. At this time, the first to n-th erasing position judging means 108 to 109 detect the pixel positions to be erased by the corresponding first to n-th thinning means, and delete the pattern by thinning n times. Control where and how you go. The first to n-th distance labeling means 110 to 111 detect the judgment result of the erasing position judging means and whether or not the pixel of interest has been erased by the thinning of that time, and the attention is performed according to the procedure described later. Give a distance label to the pixel position. The defect detecting unit 112 is composed of a length measuring unit 113, an end point detecting unit image 114, and a branch detecting unit 115, and uses the thinning image and the distance image to extract the characteristics of defects such as line width violation, disconnection, and short circuit. It is something to do. The length measuring unit 113 refers to the distance image along the core line of the thinned image, measures the line width of the wiring pattern, and detects a position that violates the specified line width. Further, the end point detecting means 114 detects the end position of the core line of the thinned image and refers to the length measurement value of the line width at that position to detect the disconnection of the wiring pattern. Further, the branch detection unit 115 detects the branch position of the core line of the thinned image. In the above configuration, the first to n-th erasing position determining means 108 and 109 are provided in order to control the property of the range image obtained by the first to n-th distance labeling means. That is, the 1st to n-th distance labeling means 110, 111 give a thinning reproduction number n to a position where a pixel is erased at the same time as the 1st-nth thinning, and The property of the range image obtained by the erasing order is determined. For example, in the first to n-th erasure position determination procedures, if the 4-connected edge position of the pattern is specified as the pixel erasure position, the obtained distance image becomes an 8-neighbor distance (chess-bord distance) image, and the pixel erasure is performed. If you specify the 8-connected edge position of the pattern as the position, the obtained distance image will be a city-block distance image. The 1st to n-th erasure position determination means switches the edge connection state between 4 connection and 8 connection in accordance with a predetermined order for each repetition of thinning of the pixel, and an error from the Euclidean distance. The purpose is to suppress.

Further, among the first to n-th erasing position determining means, the specific erasing position determining means changes and specifies the erasing slip position to a position different from the 4th connection edge position or the 8th connection edge position, and The distance value to be used is a minimal path from the pattern boundary.

 Next, the image signal processing in the first to n-th thinning means 106 to 107 and the first to n-th erase position determining means 108 to 109 will be described with reference to FIGS. 2, 3, 4, and 5. Will be described with reference to.

 FIG. 2 is a diagram showing an example of the image signal processing of the thinning means performed once. In FIG. 2, 220 is a binary image input terminal from the preceding thinning means, 221 is a thinned image output terminal, 222 is a pixel erase position determination signal output terminal, 201 is a thinning circuit, and 240 is a thinning circuit. Is an erase position determination circuit, 202 is an edge detection circuit, 203 is an erase position correction circuit, 231, 232, 233 and 234 are 3 × 3 scanning windows for thinning processing, and 203 and 204 are for erase position correction determination. 3 × 3 scanning windows, 206, 207, 208, and 209 are look-up tables (hereinafter referred to as “look-up tables” for performing the erase determination of the pixel of interest using the pixel values in the 3 × 3 area and the determination signal from the erase position determination circuit 240. LUT), 223 is the pixel of interest of the edge detection circuit, and 210, 211, 212 and 213 are erase determination signals for controlling the pixels to be erased in the thinning processing 206 to 209.

 The operation of signal processing in FIG. 2 will be described below. The input image from the terminal 220 is first scanned by a 3 × 3 scanning window composed of the position of interest 223 and the registers in the vicinity of the position 223, and is input to the erase position determination circuit 240. In the erasure position determination circuit 240, the edge detection circuit 202 first converts the edge image into 1 when the target position is the boundary point of the pattern and 0 when it is not the boundary point. The operation of the edge detection circuit 202 will be described with reference to FIG. FIG. 3 is a diagram showing the arrangement of data in the 3 × 3 scanning window described above.

As shown in the figure, assuming that the data of the pixel of interest 223 is d0 and the data in its 8 neighborhoods is d1 to d8 , the four connected edges are d0 ・ ( d1 ・ d2 ・ d3 ・ d4 ・ d5 ・ d6 ・ d7 ・ d8 ) An 8-connected edge can be converted into an edge image by the logic of dg · ( d1 · d3 · d5 · d7 ). However, · is the logical product, Indicates negation. The erasure position correction circuit 203 corrects the pixel position to be erased by thinning from the 4th connection edge or the 8th connection edge position using the edge image and the input image. A method of obtaining an octagonal range image by conversion will be described. In the first to n-th erasure position determining means, erasure of 4-connected edges and erasure of 8-connected edges are alternately repeated, and an octagonal range image is obtained by giving a thinning repetition number n to a position where a pixel is erased. . As a result, the distortion of the distance between the square lattice space and the Euclidean space can be relaxed as compared with the 4-neighborhood distance or the 8-neighborhood distance. The octagonal distance is a relatively accurate value in a specific direction (eg, horizontal, vertical, 45 ° direction), but the distance in the direction between them has an error compared to the distance defined in Euclidean space. The erasure position correction circuit 203 aims to suppress this error, and in the specific iteration of the thinning from the 1st to the n-th, the erasure position specified by the 4 or 8 connection edges is specified. change. The operation of the erase position correction circuit 203 will be described below with reference to FIGS. 2 and 4. In FIG. 2, the edge image detected by the edge detection circuit 202 is scanned by the 3 × 3 scanning window 205. At the same time, the same position of the input image is scanned by the 3 × 3 scanning window 204. Then, by referring to the two 3 × 3 patterns of the two scanning windows 204 and 205, it is determined whether or not the target position is the position to be erased. FIG. 4 is a diagram showing a combination of an input image and an edge image when the erasing position is changed and designated from 4 connected edges or 8 connected edges. The first example of changing the erasing position is the iteration in which four connected edges are erased. In any of the patterns shown in (1), since the attention position is not erased, the attention position of the edge image (the center of the 3 × 3 window) is changed to 0 and withdrawn from the erasure candidate. In the second example of changing the erase position, the input image has the pattern shown in Fig. 6 (a) and the edge image at the same position is shown in Fig. 3 (c) in the repetition of deleting the 8-connected edges. If any of the patterns is shown, the target position needs to be erased, so the target position of the edge image (center of the 3 × 3 window) is changed to 1 and taken as a candidate for deletion. Although illustration is omitted for convenience of explanation, the same erase position is changed for the rotationally symmetric patterns 3 and 3 other than the pattern shown in FIG. A specific example of the determining means in the erase position determining means is shown below. For example, the order of the erase position determination from the 1st to the 10th is In the above procedure, if the edge to be detected is 4 connected, it means 4 connected edge, and if it is 8, it means 8 connected edge. Regarding the correction of the erasing position, the case of ◯ indicates that the edge position is changed, and the case of × indicates that the edge position remains the erasure candidate position.

 The erasure determination signal 210 is input to the thinning LUT 206 at the same time as the image signal of the thinning scanning window 231, and the erasure determination signal is ON in the LUT, and the pattern connectivity is preserved even if the target position is erased. If so, the pixel of interest is erased. The erase determination signal 210 is delayed by using a line memory and a shift register to match the timing, and the erase determination signals 211, 212, and 213 are input to the LUTs 207 to 209 at the same time as the data of the scanning windows 232 to 234, and the same as the LUT 206. Is determined. These series of processes are performed by shifting pixel by pixel in synchronization with the pixel clock of the CCD sensor (not shown). The pixel erasure determination in LUTs 206 to 209 will be described below. The LUTs 206 to 209 determine whether to erase the target position from the bit patterns in the 3 × 3 scanning windows 231 to 234 when the erase determination signals 210 to 213 are on. When the target pixel is erased, 0 is output, and when the target pixel is saved, 1 is output. The first to nth thinning means cascade-connect the thinning circuits of FIG. 2 in n stages, and thin the pattern one pixel at a time from the background side while maintaining the connectivity of the patterns. Pixel erasure judgment in thinning is to erase attention when the pattern is not cut and connectivity is preserved even if the pixel of interest in the 3 × 3 window is erased. However, for a pattern with a width of 2 pixels, the pattern disappears by one window scan only by determining the connectivity, so pixel erasing in one thinning is usually performed in multiple subcycles. Therefore, in one sub-cycle, the pattern disappears by limiting the cutting direction. Such a method is called parallel thinning processing, and it is described in detail in "Contributions to thinning method", PRL Research Institute of Shinkai, PRL 75-66 (1975-12), and detailed explanation is omitted. To do. The present embodiment is an example in which one thinning is divided into four sub-cycles for cutting from the upper, lower, left and right directions, and FIG. 5 shows an example of patterns registered in the LUTs 206 to 209. FIG. 5 shows an example of erasable patterns registered in the LUTs 206 to 209. The determination results are registered in the LUTs 206 to 209 in the order of (a) to (d) in the figure using the erase determination signal and the data of the 3 × 3 window as addresses. As the determination result, 0 is registered when the pixel of interest is erased, and 1 is registered when the pixel of interest is saved.

 Next, the procedure of the first to nth distance labeling, 110 and 111 will be described. The distance labeling means determines the value of the distance label given to the position of interest from the thinned image signal from the terminal 221, the erase determination signal from the terminal 222, and the distance image to the preceding stage. The determination operation of distance labeling will be described below with reference to FIG. FIG. 6 is a flowchart showing the determination operation of the nth distance labeling. The distance image input to the first distance labeling means is a distance image whose distance label is 0 when the binary image signal from the binarization means 105 is 0 and which is distance label 1 when the binary image signal is 1. Shall be done. First, if it is determined in step 601 that the position of interest is an erasure candidate position, that is, if the erasure judgment signal is on, the process proceeds to step 603, the distance label is not updated, and the value of the distance label of the position of interest is set. Save as is. On the other hand, in the determination of 601, when the position of interest is not the erasure candidate position, that is, when the erasure determination signal is off, the process proceeds to the determination of step 602. In step 602, it is determined whether or not the distance label having the value n is attached to the position of interest by labeling the distances up to the (n−1) th distance. If the distance label is n, the process proceeds to step 604. The value is updated to (n + 1), and if the distance label is a value other than n, proceed to the processing of 603 and save the value. By the above procedure, the input binary image is converted into a range image with a range label from the value 1 to (n + 1). In the above procedure, the distance label (n + 1) is given in step 604 in order to give the distance label to the core line position of the thinning.

 FIG. 7 shows a range image obtained by the above processing. In FIG. 7, the position marked with a circle is the position of the core line of the thinned image. The length measuring unit 113 is a process for measuring the width of the pattern along this core line position.

The specific processing of the length measuring means 113 will be described below with reference to FIG. The distance label of each pixel in the distance image shown in FIG. 7 indicates the distance from that position to the nearest edge position. Therefore, the sum of the distance value at the core line position for thinning and the distance value for the neighboring pixels indicates the line width of the wiring pattern at that core line position. In the present embodiment, the line width measurement value W is determined by the following arithmetic expression. Let D0 be the distance value of the position of interest, Di (i = 1 to 8) the distance value of 8 pixels near the position of interest, and σ be the resolution of the image input. However, int [*] indicates that the fractional part of * is truncated. For example, at the pixel position 701 in FIG. 7, the length measurement value W = 5σ. In the length measuring means 113, the length measurement value W is compared with the minimum line width W0 determined by the design of the printed circuit board, and a position where W <W0 is detected as a minimum line width violation. The upper limit value W 1 of the line width may be set as a reference value to be compared with the length measurement value W, and a position violating W0 ≦ W <W1 may be detected as a line width violation. Furthermore, the lower limit value W2 and the upper limit value W3 of the second line width are set (however, W2> w1), and the position where W2 ≦ W <W3 is violated is also detected as a line width violation. Will also be possible. If the minimum line width W0 = 6σ is set, the pixel position 701 in FIG. 7 is detected as a line width violation position.

 Next, the specific processing of the end point detection means 114 will be described with reference to FIG. FIG. 8 shows a detection pattern when detecting the end points of the core line by thinning. Illustrations of rotational symmetry and mirror symmetry are omitted in FIGS. The determination of the end point detection is performed according to the following procedure.

The thinned image from the nth thinning means 107 is scanned with a 3 × 3 window, and when the bit pattern of the window dish matches any of the patterns shown in FIGS. Position. These processes can be realized by the same structure as the window scanning process and LUT shown in FIG. If the position of interest is a disconnection candidate position, the line width measurement value at that position is compared with the terminal width of the printed wiring pattern. When the minimum value of the terminal width is Wt, when the length measurement value W from the length measurement means 113 is W <Wt, it is detected as a disconnection position.

 Next, the specific processing of the branch detection means 115 will be described with reference to FIG. FIG. 9 shows a detection pattern when detecting a branch point of a core line due to thinning. In the figure, illustration of rotational symmetry and mirror symmetry is omitted. In the branch detection, the thinned image from the nth thinning means 107 is scanned by a 3 × 3 window in the same manner as the processing configuration of the end point detecting means 114, and the bit pattern in the window is shown in FIG. If it matches any of the patterns in (m), it is detected as a branch position. The branch of the core wire of the wiring pattern represents the defect feature of short circuit, so it is detected as the defect position.

 EFFECTS OF THE INVENTION As an effect of the present invention, with respect to the binary image data of the printed circuit board, thinning erasure candidate pixels are detected, and the pixels to be erased in each thinning are 4 connected edges for each thinning iteration. By switching to 8-connected edges, a distance label can be given at the same time as thinning, so that an octagonal distance image can be obtained, and the line width of horizontal, vertical, and diagonal wiring patterns can be accurately inspected with a simple configuration. . Further, by changing the position of the erasure candidate pixel from the 4-connected or 8-connected edge position at a specific iteration of thinning, a distance image accurately reflecting the distance from the edge of the pattern can be obtained. Accurate length measurement can be performed in all directions of the pattern. Further, in the defect detection means, the line width measurement value based on the distance value at the core line position of the thinned image and an arbitrary line width threshold value can be directly compared, and the line width inspection can be easily performed.

Also, by providing a plurality of line width thresholds for comparison with the line length measurement value at the core position in the defect detection means, there is no false alarm even if there are wiring patterns of different line widths on the same printed circuit board. Can be inspected. Moreover, since the defect inspection means detects the end point and branch of the core line of the thinned image, not only line width inspection but also defects such as disconnection and short circuit can be recognized, and various defect inspections are possible.

[Brief description of drawings]

 FIG. 1 is a block connection diagram of a wiring pattern inspection device according to an embodiment of the present invention, and FIG. 2 is a block connection diagram of signal processing of thinning means and erase position determination means, which are essential parts of the device. FIG. 3 is a diagram showing a pixel arrangement of the same 3 × 3 scanning window, FIG. 4 is a diagram showing a pattern for changing the erase position, and FIG. 5 is a diagram showing a pattern to be erased in the thinned LUT. FIG. 6 is a flow chart showing the same distance labeling procedure, FIG. 7 is a view showing the same distance image, FIG. 8 is a view showing a bit pattern for detecting the same end point, and FIG. 9 is a bit pattern for detecting the same branch. FIG. 10 is a diagram showing a defect detection procedure in the conventional wiring pattern inspection apparatus. 102 ... Image input means, 103 ... Imaging device, 104 ... Illumination device, 105 ... Binarization means, 106 ... First thinning means, 107 ... Nth thinning means, 108 ... First erasing position determining means, 109 ... Nth erasing position determining means, 110 ... First distance labeling means, 111 ... Nth distance labeling means, 112 ... Defect detecting means, 113 ... … Length measuring means, 114 …… End point detecting means, 115 …… Branch detecting means.

[Procedure amendment]

[Submission date] Hei 5.3.15 (1) Amend the column for claims in the specification as attached. (2) Correct "Pixel is given" on the second to fourth lines on page 9 of the specification to "Give a new distance label to the pixel position of interest by referring to the distance value of the pixel." (3) In the 13th line to the 16th line on the 10th page, "Give a target pixel ~" is given, "the distance value of the target pixel is referred to, and the distance label of the target pixel is updated according to the procedure described later. Will be corrected to (4) Correct "Minimal path" on page 12, line 10 of the same to "Minimum value".

[Claims]

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hidehiko Kawakami 3-10-1 Higashisanda, Tama-ku, Kawasaki-shi, Kanagawa Matsushita Giken Co., Ltd.

Claims (2)

[Claims] 1. An image input means for optically detecting a wiring pattern formed on a printed circuit board and performing photoelectric conversion, and a binarizing means for converting a grayscale image from the image input means into a binary image. By the first to nth thinning means for erasing the pixels forming the wiring pattern pixel by pixel from the background side, and by detecting the 4th connecting edge or the 8th connecting edge of the pattern, the 1st to 1nth thinning means The first to n-th erase position determining means for designating a 4-connected edge or an 8-connected edge as the position of the pixel to be erased, and the first to n-th erased pixel erasing means and at the same time giving a distance label to the erased position. Distance labeling means, length measuring means for measuring the line width of the wiring pattern by referring to the distance label along the core line of the thinned image obtained by the first to n-th thinning means, and thinning Picture The core wire before SL and end point detection means for detect the end point of the pattern from the measured values by the measuring means, the wiring pattern inspecting apparatus having a branch detection means for detecting a branch wiring pattern from the core of the thinned image. 2. The first to n-th erase position determining means changes the position of the pixel to be erased to a position different from the 4-connected edge or 8-connected edge by thinning in the predetermined erase position determining means. The wiring pattern inspection apparatus according to claim 1, wherein the wiring pattern inspection apparatus is specified.