JPH0786468B2 - Printed circuit board pattern inspection method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board pattern inspection method, and more particularly to a method for detecting a neck break between a land and a line of a wiring pattern.

[Conventional technology]

As electronic components become smaller, lighter, and more sophisticated, the patterns of printed circuit boards are becoming finer and higher in density.
There is a demand for finer patterns and smaller through holes. In particular, as a through hole for conduction of a multilayer board,
0.5 mm to 0.1 mm, which has been further reduced from the past 0.8 mm diameter
Through holes, called diameter mini via holes, are currently used.

As the diameter of through holes becomes smaller, new technologies are desired in various fields such as through hole plating technology, drilling, and reliability inspection.

Generally, the drilling process is less accurate than the photoetching process, and the through holes often shift from the pattern. A through hole having a diameter of about 0.8 mm has a sufficiently large land around it, and even if the through hole is slightly displaced, the electrical reliability of the substrate is not significantly affected.

However, as the size of through holes has become smaller and smaller, the size of the land has also become smaller, and the accuracy of reliably forming a hole for the through hole in the land has become uncertain during drilling.
Therefore, the electric reliability of the printed circuit board is deteriorated due to the positional deviation of the holes, and the importance of the positional deviation inspection of the through holes increases.

The hole displacement inspection requires approaches from both the electrical inspection and the visual inspection. In the visual inspection, an inspection machine of a type that detects light leaked from a crack of plating is known, but various problems have been pointed out as the number of layers of a board increases. Further, it cannot be applied to the inspection of the pattern breakage caused by the relative displacement between the through hole and the pattern.

18A and 18B are diagrams showing the relative positional relationship between the land R and the through hole H. In FIG. 18A, the center O of the through hole H coincides with the center of the land R,
It has a good pattern. In FIG. 18B, the center of the land R and the center O of the through hole H are displaced,
A part of the through hole H projects outside the land R. The size of this protruding portion is determined by the opening angle θ. When the opening angle θ is larger than a predetermined reference, the pattern break is determined to be defective.

As described above, by determining the opening angle θ, it is possible to determine whether the pattern is broken or not, and there is also proposed a technique intended to automate the determination.

[Problems to be Solved by the Invention]

However, in the quality judgment by measuring the opening angle θ, there is a problem that it is difficult to judge what is called “neck break” in which the land R and the line L are cut as shown in FIG. For example, the measuring method of the opening angle θ disclosed in Japanese Patent Application No. 1-82117 by the present applicant is to enlarge the contour of the through hole H to obtain the enlarged contour RP, and observe the degree of overlap between this and the land R. However, the opening angle θ (= θ ₁
+ Θ ₂ ) was measured. However, in this case, it is impossible to judge whether the neck is broken or not even if the quality can be judged, and it is desired to obtain the judgment whether the neck is broken or not in view of the manufacturing process management of the wiring pattern.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of inspecting a printed circuit board for automatically determining a neck break of a wiring pattern.

[Means for Solving the Problems]

The present invention is a pattern inspection method for a printed circuit board, which photoelectrically scans the printed circuit board and determines a relative positional relationship between a wiring pattern on the printed circuit board and a through hole based on image data read for each pixel. The pattern image indicating the wiring pattern and the hole image indicating the through hole are obtained based on the read image data, and the pattern image is subjected to the thinning process to obtain the thinned pattern image, which includes the hole image. The window is set, the number of end points of the thinned pattern image is calculated in the window, and the disconnection of the wiring pattern neck is detected from the number of end points.

[Action]

In the present invention, the thinned pattern image presents the "cut" of the original wiring pattern as an end point, and the number of end points in the window set including the hole image includes information on whether the neck is broken or not. Therefore, by counting this, it is determined whether or not a neck break has occurred.

〔Example〕

A. Overall Configuration and Schematic Operation FIG. 2A is a block diagram showing the overall configuration of a pattern inspection apparatus to which an embodiment of the present invention is applied.

A printed circuit board 11 to be inspected is placed on the stage 10. The printed circuit board 11 is sent in the transport direction Y while the image is read by the reading device 20 in each line direction X. The reader 20 has thousands of elements.
A plurality of CCDs are arranged in series in the line direction X,
The pattern of the printed circuit board 11 is read for each pixel. The read image data is sent to the binarization circuits 21a and 21b. The binarization circuit 21a uses a Hall image original signal H described later.
IS ₀ is generated, and the binarization circuit 21b generates a pattern image original signal PIS ₀ described later. Both the signals HIS ₀ and PIS ₀ are input to the pattern inspection circuit 30.

The pattern inspection circuit 30 has a function to be described later, inspects a wiring pattern (including a land) and a relative positional relationship between the wiring pattern and the through hole, and outputs the result to the central processing unit (MPU) 5
Give to 0.

The MPU 50 controls the entire device via the control thread 51. The control system 51 generates an XY address or the like for specifying the address of the data obtained in the pattern inspection circuit 30. The XY address is also given to the stage drive system 52 to control the transport mechanism of the stage 10.

CRT60 receives various commands from MPU50,
For example, a hall image is displayed. Keyboard 70
Are used to input various commands to the MPU 50.

The option section 80 includes a defect confirmation device 81 and a defective product removal device 8
2 and the defect position marking device 83 are arranged.
The defect confirmation device 81 is a device for enlarging and displaying the detected defect on the CRT 60, for example. The defective product removing device 82 is a device for transporting the printed circuit board 11 to a defective product tray or the like when the defective printed circuit board 11 is detected. In addition, the defect position marking device 83
Is a device for marking a defective portion on the printed circuit board 11 directly or at a point on the sheet corresponding to that portion. These devices are installed as needed.

B. Reading Optical System FIG. 3A is a diagram showing an example of a reading optical system including the stage 10, the printed circuit board 11, the reading device 20 and the like shown in FIG. 2A.

In FIG. 3A, the height from the light source 22 is reflected by the half mirror 23 and irradiated on the printed board 11 on the stage 10. On the printed circuit board 11, there are a base B, a wiring pattern L, a through hole H, and a land R around the base B as a base. The light reflected from the printed circuit board 11 is a half mirror
After passing through the lens 23, the light enters the CCD 24 provided in the reading device 20 through the lens 25. The CCD 24 sequentially reads the reflected light from the base B, the wiring pattern L, the through holes H, the lands R, etc. on the printed circuit board 11 which is sent in the carrying direction Y.

FIG. 4 is a graph showing a signal waveform read on the line AA ′ in FIG. 3A and an example of a pattern obtained by synthesizing the signal waveforms.

As shown in the signal waveform of FIG. 4, the reflected light is relatively small in the base B, and a signal having a level between the thresholds TH1 and TH2 (TH1 <TH2) is generated. Since the land R is formed of a metal such as copper, a lot of light is reflected at this portion, and a signal having a level equal to or higher than the threshold TH2 is generated. In addition,
A signal of the same level is generated also in the wiring pattern L. In the through hole H, there is almost no reflected light, and a signal having a level equal to or higher than the threshold TH1 is generated.
Further, between the through hole H and the land R, there is usually an edge (opening edge) E formed at the time of drilling.
There is rattling and inclination in this part, and the reflected light level in this part does not have a particularly constant value, but it is almost the threshold value TH.
It is between 1 and the threshold TH2.

The signal from the reading device 20 is supplied to the binarization circuits 21a and 21b shown in FIG. 2A.
In, for example, it is binarized by using thresholds TH1 and TH2, respectively. The binarization circuit 21a generates a hole image HI indicating the through hole H, and the binarization circuit 21b generates a pattern image PI indicating the land R and the wiring pattern P. These two images HI and PI are used as signals necessary for the processing described later.

FIG. 3B is a diagram showing another example of the reading optical system. Light source 22
Similarly to the example shown in FIG. 3A, the light from a passes through the half mirror 23 and the lens 25 as reflected light inside the reading device 20.
It is irradiated on CCD24. In this example, a light source 22b is further provided on the back side of the stage 10, and the light passing through the through hole H is also applied to the CCD 24. Therefore, in the through hole H, the signal level is the highest and the land
In R and the wiring pattern L, the signal level is medium, and in the base B and the edge E, the signal level is relatively low.

Furthermore, as another example, two or more rows of CCD24 are prepared and the light source 2
2a detects the land R and the wiring pattern L,
Only the through hole H may be detected by the light source 22b, and the data thereof may be separately output to the binarization circuit in the subsequent stage.

C. Pattern Inspection Circuit FIG. 2B is a block diagram showing an internal configuration of the pattern inspection circuit 30 shown in FIG. 2A.

The hole image original signal HIS ₀ and the pattern image original signal PIS ₀ generated by the binarization circuits 21a and 21b of FIG. 2A are given to the noise filters 32a and 32b via the interface 31, respectively. The noise filters 32a and 32b remove noise by performing smoothing processing, etc.
The pattern image signal PIS is generated respectively.

Both the hole image signal HIS and the pattern image signal PIS are given to all of the comparison inspection circuit 33, the DRC (Design Rule Check) circuit 34, and the through hole inspection circuit 35.

The comparison / inspection circuit 33 is a circuit for comparing and collating the hole image signal HIS and the pattern image signal PIS with the image signal obtained for the reference printed circuit board prepared in advance, and for identifying a portion where they are different from each other as a defect. . As the reference printed circuit board, a printed circuit board which is of the same type as the printed circuit board 11 to be inspected and which is determined in advance to be a good product is used. This method (comparative method) is disclosed, for example, in JP-A-60-263807 by the present applicant.
It is disclosed in the publication.

The DRC circuit 34 extracts the characteristics of the pattern P on the printed circuit board 11, such as the line width, the pattern angle, and the continuity, and determines whether or not the values deviate from the designed values. It is a circuit that performs an inspection.
This DRC method is disclosed in, for example, Japanese Patent Application Laid-Open No. 57-149905.

D. Through hole inspection circuit (D-1). Outline Before explaining the detailed structure and operation of each part of the through-hole inspection circuit, the outline will be described below.

FIG. 1A is a block diagram showing the internal structure of the through-hole inspection circuit 35 shown in FIG. 2B, and FIG. 1B shows the flow of a pattern inspection method for a printed circuit board performed with the structure shown in FIG. 1A. It is a flowchart.

The center judgment and diameter measuring circuit 36 in FIG.
This is a circuit for outputting the information CP regarding the center position (hereinafter "center CP") and the information regarding the diameter, for example, the diameter D, and corresponds to step S11 in FIG. 1B.

The center CP may be a value of coordinates (X, Y), or may be in the form of setting a bit in the position information matrix [X, Y]. In any case, it is not always necessary to accurately determine the central CP in the present invention, as will be described later.

Examples of the configuration of the circuit 36 include a configuration that forms a cross operator. In FIG. 5, a cross-shaped spatial operator (cross operator) OP is applied to the hall image HI obtained from the hall image signal HIS, and the length d of the portion where the four arms of the operator OP and the hall image HI overlap each other. By comparing _{1 to} d ₄ , information about the center of the hole image HI and its diameter can be obtained. Such a space operator method is disclosed in, for example, the application of Japanese Patent Application No. 2-191343 by the present applicant. Alternatively, the background of the Hall image HI is expanded using the expansion processing described later, and the Hall image HI is equivalently expanded.
May be reduced to obtain the center CP, and the diameter D may be obtained from the required number of reduction steps.

The center CP and the diameter D of the hole image HI thus obtained are input to the window setting circuit 38. In this circuit, the size necessary for judging the neck break from the center CP,
For example, a window W having a size of 4D × 4D is set. Specifically, for example, CP = (x _C , y _C ), W ₁ = (x _C + 2D, y _C + 2D) W ₂ = (x _C + 2D, y _C −2D) W ₃ = (x _C −2D, The rectangular area defined by the four points of y _C −2D) W ₄ = (x _C −2D, y _C −2D) is defined as the window W. This process corresponds to step S12 in FIG. 1B.

The hall image signal HIS is also input to the labeling processing circuit 37. Here, each hole image HI generated from the hole image signal HIS is labeled with a different label LAB to identify them from each other. This process corresponds to step S13 in FIG. 1B.

On the other hand, the pattern image signal PIS is input to the thinning circuit 39 and becomes the thinning signal PIL. This is step S in Figure 1B.
Corresponds to 14. A known method for thinning can be used, for example, a 3 × 3 mask shown in FIG. That is, if the 3 × 3 neighborhood of the pixel of interest of the image data matches the pattern of FIG. 10A, replacing the pixel from 1 to 0 can make one pixel thinner from left to right (FIG. )). The same processing as this may be performed for all pixels from four directions in the vertical and horizontal directions. Further, for example, thinning with vectorization as disclosed in Japanese Patent Application Laid-Open No. 2-14383 by the present applicant may be performed.

Returning to FIG. 1A, the window W and the thinned signal PIL are
It is input to the end point extraction circuit 41. Here, the process of step S15, that is, the number N of end points Q is obtained. It is sufficient to determine the neck break by inspecting the vicinity of the land R (through hole H). Therefore, it is sufficient to count the number N of end points in the window W.

A known method, for example, a 3 × 3 mask shown in FIG. 7 can be used for the end point extraction. That is, if the 3 × 3 neighborhood of the pixel of interest in the thinned image data matches any of the eight types of patterns in the figure, the pixel is recognized as the end point Q.

The number N of end points thus obtained is stored in the end point number memory 42 with the label LAB in which the delay in the labeling process S12 and the end point extraction process S15 is corrected by the phase adjusting circuit 40 as an address. In FIG. 1B, step S16 corresponds.

On the other hand, since the center CP is stored in the coordinate memory 43 by using the level LAB as an address, for example, after counting the number N of end points Q of all holes H of the printed circuit board 11, the number of holes H at a certain position is calculated. N can be associated via the label LAB. The neck breakage determination circuit 44 determines whether or not the number N associated in this way is a neck breakage based on the value (step S17), and the coordinates of the hole H determined as a neck breakage are stored in the defect coordinate memory 45. (Step S18). A specific determination method will be described later.

As described above, the through-hole inspection circuit 35 detects the disconnection of the neck of the wiring pattern and determines whether or not there is a defect.

Next, a specific example of detecting a neck break will be described.

(D-2). Labeling Process FIG. 8 shows an outline of the labeling process, FIG. 9 shows a block diagram of the labeling process circuit 37, and FIG. 10 shows a flow chart of the circuit 37. The hole image HI generated by the hole image signal HIS is input to the expansion circuit 37a, and the expanded hole image HF is obtained (step S2
1). A well-known method for this expansion processing, for example, the 11th
As shown in the figure, when the pixel of interest in the image data is 1, all 3 × 3 neighboring pixels may be set to 1.

Next, the expanded hole image HF is input to the labeling circuit 37b and a label LAB is attached (step S22). The expansion treatment is not always necessary for this labeling, but it is desirable to expand the label to a certain size because it is easy to process. For labeling, a known method, for example, as shown in FIG. 12, consider a label L _i (a non-negative integer) in which a unique number is assigned to each inflated hole image HF, and the background also includes the label number 0, Of the labels in the 3 × 3 vicinity of the pixel of interest in the image data, the smallest positive label may be re-assigned as the label of that pixel, and the label value may be repeated until it converges.

Note that Fig. 8 shows the window W for correspondence with the label LAB.
I also showed the situation.

(D-3). End Point Extraction Circuit FIG. 13 shows a block diagram of the configuration of the end point extraction circuit 41, and FIG. 14 shows a flowchart of the same circuit 41. In the end point determination circuit 41a, as described in (D-1), for example, the end points Q ₁ , Q ₂ , in the window W of the pattern PL subjected to the thinning processing using the 3 × 3 mask shown in FIG. Is calculated using the 3 × 3 mask shown in FIG. 7 (step S31).
In the end point number counting circuit 41b, the number N of end points Q ₁ , Q ₂ , ... Is obtained (step S32).

15A and 15B show how endpoints are extracted. In each figure, the upper part shows the relationship between the actual wiring pattern P and the through hole H, and the lower part shows the pattern PL and the end points Q ₁ , Q ₂ , ... (Indicated by ▲ in the figure). The value of N represents the number of end points of the pattern shown above.

(D-4). Neck break determination circuit Figure 16 shows a block diagram of the configuration of the neck break determination circuit 44.
FIG. 17 shows a flowchart of the same circuit 44. The comparison circuit 44a inputs the number N of end points and compares it with a certain reference value to determine whether or not the neck is broken, and corresponds to steps S41 and S42. The output circuit 44b is a circuit for outputting OK / Error according to the above judgment, and the step S4
3 and S44 correspond.

FIG. 15A shows the case where there is no neck break, and FIG. 15B shows the case where there is a neck break. As can be seen from FIG. 15A, when the wiring pattern P is normal and the through hole H is almost correctly aligned with the wiring pattern P, N = 0, and the through hole H moves away from the neck and is displaced. If it occurs, N = 2. Furthermore, when a pattern break that is not a neck break occurs due to a factor other than the position shift of the through hole H, an even number of end points is always generated. Therefore, as a general rule, a neck break does not occur unless N is an odd number. It can be determined (step S41). Even when N = 1, no neck break has occurred, so OK is output (steps S42 and S44).

The case where the neck break occurs is the case where the through hole H covers the vicinity of the neck as in the case of N = 3 in FIG. 15B, and when the pattern break occurs due to factors other than the position shift of the through hole H. Always involves generation of an even number of end points, so in principle it can be considered that a neck break has occurred if N is an odd number of 3 or more. However, as in the case of N = 4 in the same figure, theoretically N may be an even number and a neck break may occur, but experience shows that this case is rare and needs to be considered. There is no. Therefore, if N is an odd number of 3 or more, Error is output (step S43).

E. Modified Example (1) The window W is not limited to the rectangular area described above, and may be, for example, a circular upper area, and an expanded hole image WF may be used as the circular upper area.

(2) The above-mentioned neck break determination criterion can be set arbitrarily.

(3) In addition to the above-mentioned neck breakage inspection, the whole of the through-hole inspection includes the above-mentioned Japanese Patent Application No. 1-8211 by the applicant.
Inspection based on No. 7 opening angle θ can be used.

〔The invention's effect〕

As described above, the printed circuit board inspection method of the present invention reads the wiring pattern of the printed circuit board, thins this pattern image, and counts the end points of the thinned pattern image in the window set near the through hole. Since it is determined whether or not the neck is broken, it is not necessary to strictly determine the center of the circle in the hole image, and the neck of the wiring pattern can be automatically judged by a relatively simple means.

[Brief description of drawings]

FIG. 1A is a block diagram showing an embodiment of the present invention, FIG. 1B is a flow chart showing an embodiment of the present invention, FIG. 2A is a block diagram showing the configuration of an apparatus to which the present invention is applied, and FIG. 2B is A block diagram showing a configuration of a circuit to which the present invention is applied, FIGS. 3A to 3B are conceptual diagrams showing reading by photoelectric scanning, and FIG. 4 is a signal waveform read by FIG. FIG. 5 is a diagram showing the pattern of a cross operator, FIG. 5 is a diagram showing an example of a cross operator, FIG. 6 is a diagram showing an example of thinning, FIG. 7 is a diagram showing an example of end point detection, and FIG. 8 is an example of labeling. FIG. 9, FIG. 9 is a block diagram showing the configuration of the labeling processing circuit, FIG. 10 is a flowchart showing the flow of the labeling processing circuit, FIG. 11 is a diagram showing an example of expansion processing, and FIG. 12 is an example of labeling. Fig. 13 shows the structure of the end point extraction circuit. Fig. 14 is a flow chart showing the flow of the end point extraction circuit, Fig. 15A is a diagram showing the thinning of the wiring pattern without neck break, and Fig. 15B is the thin line of the wiring pattern with neck break. FIG. 16 is a block diagram showing the configuration of the neck cutout determination circuit, FIG. 17 is a flowchart showing the flow of the neck cutout determination circuit, and FIGS. 18A to 18B and FIG. It is a figure which shows a problem. 11 …… Printed circuit board, 38 …… Window setting circuit, 39 …… Thinning circuit, 41 …… End point extraction circuit, 44 …… Neck break judgment circuit, P …… Wiring pattern, PI …… Pattern image, H …… through-hole, HI ...... hole image, has been treated PL ...... thinning pattern, W: window, Q ₁ ~Q ₄ ...... endpoints

Claims (1)

[Claims] 1. A pattern of a printed circuit board, wherein a relative positional relationship between a wiring pattern on the printed circuit board and a through hole is determined based on image data read for each pixel by photoelectrically scanning the printed circuit board. An inspection method comprising: (a) obtaining a pattern image showing the wiring pattern and a hole image showing the through hole based on the image data; (b) performing a thinning process on the pattern image. Give,
Obtaining a thin line pattern image; (c) setting a window including the hole image; (d) obtaining the number of end points of the thin line pattern image in the window; A method for inspecting a printed circuit board pattern, the method comprising: detecting a neck break of the wiring pattern based on the number of printed wiring boards.