JPH04184244A - Method for inspecting pattern of printed circuit board - Google Patents

Abstract

PURPOSE:To automatically judge the neck cutting of wiring by calculating a thinning pattern image on the basis of image data and calculating the number of the endpoints thereof within a window containing a hole image. CONSTITUTION:The wiring pattern of a printed circuit board is read to be thinned and the number of the endpoints of the thinned pattern image within the window set in the vicinity of a through-hole is calculated to judge whether neck cutting is generated. By this method, it is unnecessary to strictly judge the center of the circle in a hole image and the neck cutting of a wiring pattern can be automatically judged by a relatively simple means.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for inspecting patterns of printed circuit boards, and particularly to a method for detecting neck breaks between lands and lines of wiring patterns.

[Conventional technology]

As electronic components become smaller, lighter, and have higher performance,
- Circuit board patterns are also becoming finer and denser, requiring thinner patterns and smaller diameter through holes. In particular, as conduction through holes for multilayer boards, the diameter has been further reduced from the past 0.8W diameter to 0.5m.
A through hole called a mini-via hole with a diameter of m~0, 1 mm is currently used.

As through-holes become smaller in diameter, new technologies are needed in various areas such as through-hole plating, drilling, and reliability testing.

Drilling is generally less precise than photoetching processes, and through holes often deviate from the pattern. 0. A sufficiently large land was provided around the through hole having a diameter of Ill+e+e, so even if the through hole was slightly misaligned, the effect on the electrical reliability of the board was slight.

However, as the diameter of through-holes has become smaller, lands have also become smaller, and the accuracy of drilling holes for through-holes in lands can no longer be guaranteed.

Therefore, a decrease in the electrical reliability of the printed circuit board due to the misalignment of the holes becomes a problem, and the importance of inspecting the misalignment of the through-holes increases.

Inspecting hole misalignment requires approaches from both electrical inspection and visual inspection.

In visual inspection, inspection machines that detect light leaking from cracks in plating are known, but as boards become more multi-layered, various problems have been pointed out. Further, it cannot be applied to inspection of pattern breakage caused by relative positional deviation between a through hole and a pattern.

Figures 18A and 18B show land R and through hole H.
It is a figure showing the relative positional relationship with. In FIG. 18A, the center O of the through hole H coincides with the center of the land R, resulting in a good pattern. In FIG. 18B, the center of the land R and the center 0 of the through hole H are shifted from each other, and a portion of the through hole H protrudes to the outside of the land R. The size of this protruding portion is determined by the aperture angle θ. When the aperture angle θ is larger than a predetermined standard, the pattern breakage is determined to be defective.

As described above, by determining the aperture angle θ, it is possible to determine the quality of pattern breakage, and techniques have also been proposed that are intended to automate the determination.

[Problem to be solved by the invention]

However, the quality judgment based on the measurement of the opening angle θ has a problem in that it is difficult to judge the so-called "neck break" where the land R and the line L are cut, as shown in FIG. For example, the δ1' orthotropy of the aperture angle θ disclosed in Japanese Patent Application No. 1-82117 by the present applicant is obtained by enlarging the outline of the through hole H to obtain an enlarged outline RP, and then determining the overlap between this and the land R. The condition was observed and the opening angle θ (-01+θ2) of the non-overlapping portion was measured. However, with this method, it is possible to judge whether the wire is good or bad, but it is not possible to judge whether or not the wire is broken.Therefore, it has been desired to determine whether or not the wire is broken in order to manage the manufacturing process of the wiring pattern.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for inspecting a printed circuit board that automatically determines whether a neck is broken in a wiring pattern.

[Means to solve the problem]

This invention provides a pattern inspection method for a printed circuit board, in which the relative positional relationship between a wiring pattern and a through hole on a printed circuit board is determined based on image data read for each pixel by photoelectrically scanning the printed circuit board. Based on the read image data, a pattern image indicating a wiring pattern and a hole image indicating a through hole are obtained, and a thinning process is performed on the pattern image to obtain a thinned pattern image, which includes the hole image. A window is set, the number of end points of the thinned pattern image is found within the window, and the number of end points in the wiring pattern is used to detect the edges and cuts of the wiring pattern.

[Effect]

In this invention, the thinned pattern image presents the "breaks" of the original wiring pattern as end points, and the number of end points within the set window including the hole image includes information as to whether or not there is a neck break. By counting this number, it is determined whether or not a neck breakage has occurred.

〔Example〕

A. Overall configuration and general operation FIG. 2A is a block diagram showing the overall configuration of a pattern inspection apparatus to which an embodiment of the present invention is applied.

On the stage 10 is a printed circuit board 11 to be inspected.
is placed. The printed circuit board 11 is conveyed in the transport direction Y while its image is read by the reading device 2° in each line direction X. The reading device 20 has a plurality of CCDs each having several thousand elements arranged in series in the line direction X, and reads the pattern of the printed circuit board 11 pixel by pixel. The read image data is sent to the binarization circuit 21
a, 21b. The binarization circuit 21a generates a hole image original signal H1so, which will be described later.
1b generates a pattern image original signal PIS, which will be described later. Both signals H1s and PIS0 are input to the pattern inspection circuit 30.

The pattern inspection circuit 30 has a function described later, inspects the wiring pattern (including lands) and the relative positional relationship between this and the through hole, and sends the results to the central processing unit I (
MPU) 50.

The MPU 50 controls the entire device via a control system 51. The control system 51 generates an XY address and the like for specifying the address of data obtained by the pattern inspection circuit 30. The XY address is also given to the stage drive system 52 to control the transport mechanism of the stage 10.

The CRT 60 receives instructions from the MPU 50 and displays various calculation results, such as a hole image. The keyboard 70 is used to input various commands to the MPU 50.

The option section 80 includes a defect confirmation device e81. A defective product removing device 82, a defective position marking device 83, and the like are arranged. The defect confirmation bag [81 is a device for enlarging and displaying detected defects on, for example, a CRT 60. Furthermore, the defective product removing device 82 is a device for, when a defective printed circuit board 11 is detected, conveying the printed circuit board 11 to a tray for defective products or the like. Further, the defect position marking device 83 directly marks the defective part on the printed circuit board 11 or marks the part corresponding to the defective part.

- This is a device for marking points on the board.

These devices are installed as needed.

B. Reading optical system FIG. 3A shows the stage 10. shown in FIG. 2A. Printed circuit board 11 and reading device! 20 is a diagram illustrating an example of a reading optical system composed of components such as 20. FIG.

In FIG. 3A, light from light source 22 is transmitted through a half mirror.
23 and is irradiated onto the printed circuit board 11 on the stage 10. On the printed circuit board 11 are a base B serving as a base and a wiring pattern L.

There is a through hole H and a land R around it. The reflected light from the printed circuit board 11 passes through the half mirror 23, and further enters the CCD 24 provided in the reading device 20 via the lens 25. The CCD 24 sequentially reads reflected light from the base B, wiring pattern L, through hole H, land R, etc. on the printed circuit board 11 that is sent in the transport direction Y.

FIG. 4 is a graph showing a signal waveform read along line AA' in FIG. 3A, and an example of a pattern obtained by combining the signal waveforms.

As shown in the signal waveform of FIG.
A signal with a level between H2) is generated. Land R is
Since it is made of metal such as copper, a lot of light is reflected at this portion, and a signal with a level higher than the threshold TH2 is generated. Note that a signal of the same level is also generated in the wiring pattern L. Furthermore, in the through hole H, there is almost no reflected light, and a signal with a level below the threshold iT'H1 is generated. Furthermore, between the through hole H and the land R, there is usually an edge (opening edge) E formed during drilling. There are wobbles and inclinations in this part, and the reflected light level in this part does not take a particularly constant value, but is approximately between the threshold value TH1 and the threshold value TH2.

Reading device! The signal from 20 is sent to the binarization circuit 2 of FIG. 2A.
In 1a and 21b, for example, the threshold value THI.

It is binary-valued using TH2 respectively. Binarization circuit 21
a is a hole image H! showing a through hole H! The binarization circuit 21b generates land R and wiring pattern P.
A pattern image PI is generated. These two images H1 and PI are used as signals necessary for processing to be described later.

FIG. 3B is a diagram showing another example of the reading optical system. The light from the light source 22a is irradiated onto the CCD 24 in the reading device 20 as reflected light via the half mirror 23 and the lenses 25, as in the example shown in FIG. 3A. In this example, a light source 22b is further provided on the back side of the stage 10, and the light passing through the through hole H is also irradiated onto the CCD 24. Therefore, in the through hole H, the signal level is the highest, in the land R1 wiring pattern L, the signal level is medium, and in the base B and edge E, the signal level is relatively low.

Furthermore, as another example, two or more rows of CCD24 are prepared,
The light source 22a may detect the land R and the wiring pattern L, the light source 22b may detect only the through hole H, and the data may be separately output to the subsequent binarization circuit.

C. Pattern Inspection Circuit FIG. 2B is a block diagram showing the internal configuration of the pattern inspection circuit 30 shown in FIG. 2A.

The hole image original signal 1 (1so) and pattern image original signal PISo generated by the binarization circuits 21a, 21b in FIG. 2A are given to the noise filters 32a, 32b through the interface 31. performs smoothing processing and the like to remove noise and generate a hole image signal H1s and a pattern image signal PIs, respectively.

Hole image signal HIS and pattern image signal PI
Both of S are the comparison test circuit 33. DRC (Deslg
nRu1e Check) circuit 34. It is applied to all through-hole inspection circuits 35.

The comparison inspection circuit 33 is a circuit that compares and collates the hole image signal HIS and the pattern image signal PIS with an image signal obtained from a reference printed circuit board prepared in advance, and identifies a portion where they differ from each other as a defect. . As the reference printed circuit board, a printed circuit board that is the same type as the printed circuit board 11 to be inspected and that has been previously determined to be a good product is used. This method (comparative method) is for example
It is disclosed in Japanese Patent No. 263807.

The DRC circuit 34 extracts the characteristics of the pattern P on the printed circuit board 11, such as line width, pattern angle, and continuity.
This circuit tests the quality of the printed circuit board 11 by determining whether these values deviate from the designed values. Regarding this DRC method, for example, Japanese Patent Application Laid-open No. 57
It is disclosed in the publication No.-149905.

D. Through-hole inspection circuit (D-1), overview Before explaining the detailed structure and operation of each part of the through-hole inspection circuit, an overview thereof will be described below.

FIG. 1A shows a through-hole inspection circuit 35 shown in FIG. 2B.
FIG. 1B is a block diagram showing the internal configuration of FIG.
3 is a flowchart showing the flow of a printed circuit board pattern inspection method performed with the configuration shown in the figure.

The center determination and diameter measurement circuit 36 in FIG.
) and diameter information, for example, the diameter, and corresponds to step S11 in FIG. 1B.

The center CP may be the value of coordinates (X, Y), or may be in the form of bits set in the position information matrix [X, Y]. In any case, as will be described later, in the present invention, it is not necessary to accurately determine the center CP.

For example, the circuit 36 may have a cross-shaped configuration. In FIG. 5, a cross-shaped spatial operator (cross operator) OP is applied to the hole image H1 obtained from the hole image signal HIS, and the length d of the portion where the four arms of the operator OP and the hole image H1 overlap is d. By comparing -d4, information about the center of the hole image H1 and its diameter can be obtained. Regarding the method of such a spatial operator, for example, Japanese Patent Application No. 2-19134 filed by the present applicant
It is disclosed in Application No. 3.

Alternatively, the hole image H1 can be
The center CP may be obtained by expanding the background and equivalently reducing the hole image H1, and the diameter may be obtained from the required number of reduction stages.

The center C of the hole image H1 obtained in this way
P and diameter are input to window setting circuit 38. In this circuit, a window W of a size necessary for neck breakage determination, for example, 4D x 4D in the j method, is set from the center CP. Specifically, for example, as CP-(x, y), CC W l-(xc ” 2 D, y c +2 D )W
2- (xo+2D, yo-2D)W3” (
xQ 2D, y, +2D) W4- (x, -
A rectangular area defined by four points (2D, yo-2D) is defined as a window W. This process corresponds to step S12 in FIG. 1B.

The hole image signal HIS is also input to the labeling processing circuit 37. Here, each hole image generated from the hole image signal HIS) has a different label LAB
are attached to distinguish them from each other. This process corresponds to step S13 in FIG. 1B.

On the other hand, the pattern image signal PIS is input to the thinning circuit 39 and becomes the thinning signal PIL. This corresponds to step 514 in Figure 1B. For line thinning, a known method such as a 3×3 mask shown in FIG. 6 can be used. In other words, if the 3x3 near-edge of the pixel of interest in the image data matches the pattern shown in Figure (a), that pixel is changed from 1 to 0.
By replacing it with , it is possible to mesh one pixel from left to right ((b) in the same figure). Processing similar to this may be performed for all pixels from four directions: top, bottom, left, and right. Alternatively, line thinning accompanied by vectorization may be performed, for example, as disclosed in Japanese Unexamined Patent Publication No. 2-14383 by the present applicant.

Returning to FIG. 1A, window W and thinning signal PIL
is input to the end point extraction circuit 41. Here, the process of step S15 is performed, that is, the number N of end points Q is determined. To determine whether the neck is broken, it is sufficient to inspect the vicinity of the land R (through hole H), so the number of end points within the window W is N.
It is enough to count.

A known method, for example, a 3×3 mask shown in FIG. 7, can be used to extract the end points. That is, if the 3×3 neighborhood of the pixel of interest in the thinned image data matches any of the eight patterns shown in the figure, that pixel is recognized as the end point Q.

The number N of end points obtained in this way is stored in the end point number memory 42 using the label LAB whose delay in the labeling process S12 and the end point extraction process S15 has been corrected by the phase adjustment circuit 40 as an address. In FIG. 1B, step S16 corresponds.

On the other hand, since the center CP is stored in the coordinate memory 43 using the label LAB as an address, for example, the printed circuit board 11
After counting the number N of end points Q for all holes H, label the hole H at a certain position and the number N.
It can be associated via B. The neck breakage determination circuit 44 determines whether or not the neck is broken based on the number N associated in this manner.Step 517
), the coordinates of the hole H determined to be broken are stored in the defect coordinate memory 45 (step 518).

A specific determination method will be described later.

In the manner described above, the through-hole inspection circuit 35 detects a neck cut in the wiring pattern and determines whether or not it is defective.

Next, a specific example of detecting neck breakage will be explained.

(D-2) Labeling Process FIG. 8 shows an outline of the labeling process, FIG. 9 shows a block diagram of the labeling processing circuit 37, and FIG. 10 shows a flowchart of the circuit 37.

The hole image H1 generated by the hole image signal HIS is input to the expansion circuit 37a, and an expanded hole image HF is determined (step 521). This expansion process may be carried out using a known method, for example, as shown in FIG. 11, when the pixel of interest in the image data is 1, all pixels in the 3×3 vicinity thereof are set to 1.

Next, the expanded hole image HF is labeled as circuit 37.
b, and add labels L, A B (Stip 5
22). Although the expansion process is not necessarily necessary for this labeling, it is preferable to expand it to a certain size because it makes the process easier.

For labeling, a known method is used, for example, as shown in FIG.
, (non-negative integer), 3 of the pixel of interest in the image data
Among the labels in the ×3 neighborhood, the least positive label is relabeled to that pixel, and the process is repeated until the label value converges.

Note that FIG. 8 also shows the state of the window W for correspondence with the label LAB.

(D-!l), Endpoint Extraction Circuit FIG. 13 shows a block diagram of the configuration of the endpoint extraction circuit 41.
Flowcharts of the circuit 41 are shown in Figure IA14. As explained in (D-1), the endpoint discrimination circuit 41a detects the endpoints Q, Q2, . ... is obtained using the 3×3 mask shown in FIG. 7 (step 531). End point number counting circuit 41
In b, the end points Q, Q2. Find the number N of... (
Stellap 532).

FIGS. 15A and 15B show how end points are extracted. In both figures, the upper row shows the relationship between the actual wiring pattern P and the through hole H, and the lower row shows the thinned pattern PL and the end points Q, Q2°... (indicated by squares in the diagram). The N chain represents the number of end points of the pattern shown above.

(D-4) Neck Breakage Judgment Circuit FIG. 16 shows a block diagram of the configuration of the neck breakage judgment circuit 44, and FIG. 17 shows a flowchart of the same circuit 44. The comparison circuit 44a inputs the number N of end points and compares it with a certain reference value to determine whether or not a neck is broken, and corresponds to steps S41 and S42. Also, the Kawauchi circuit 44b is OK / E rror according to the above judgment.
This is a circuit that outputs, and steps S43 and S44 correspond to this circuit.

FIG. 15A shows a case where there is no neck breakage, and FIG. 15B shows a case where there is a neck breakage. As shown in Fig. 15A, if the wiring pattern P is normal and the through hole H almost correctly matches the wiring pattern P, then N
-0, and if the through hole H is displaced away from the neck, it becomes N-2. Furthermore, if a pattern break that is not a neck break occurs due to a factor other than the misalignment of the through hole H, an even number of end points will always be generated, so as a general rule, if N is not an odd number, it is assumed that a neck break has not occurred. It can be determined (step 541). Also, in the case of N-1, since no neck breakage has occurred, OK is output (step S42.544).

When a neck breakage occurs, for example, as in the case of N-3 in Fig. 15B, the through hole H covers the vicinity of the neck, and furthermore, when a pattern breakage occurs due to factors other than the positional deviation of the through hole H. Since this always involves the generation of an even number of end points, in principle, if N is an odd number of 3 or more, it can be considered that a neck break has occurred. However, as in the case of N-4 in the same figure, it is theoretically possible that N is an even number and a neck break has occurred, but in terms of red experience, such cases are almost impossible and should be considered. There's no need. Therefore, if N is an odd number of 3 or more, IError is output (step 843).

E. Modification (1) The window W is not limited to the above-mentioned rectangular area, but may be, for example, a circular area, and an expanded hole image WF may be used as the circular area.

(2) The above neck breakage determination criteria can be set arbitrarily.

(3) As for through-hole inspection as a whole, in addition to the neck breakage inspection mentioned above, the above-mentioned Japanese Patent Application No. 1-8
The aperture angle θ based test of No. 2117 can be used.

〔Effect of the invention〕

As explained above, the printed circuit board inspection method of the present invention reads the wiring pattern of the printed circuit board, thins the pattern image, and counts the end points of the thinned pattern image within a window set near the through hole. Since it is determined whether a neck is broken or not, there is no need to strictly determine the center of a circle in a hole image, and neck breaks in a wiring pattern can be automatically determined by a relatively simple means.

[Brief explanation of the drawing]

FIG. 1A is a block diagram showing an embodiment of this invention, FIG. 1B is a flowchart showing an embodiment of this invention, FIG. 2A is a block diagram showing the configuration of an apparatus to which this invention is applied, and FIG. 2B is a block diagram showing an embodiment of this invention. A block diagram showing the configuration of a circuit to which this invention is applied; FIGS. 3A and 3B are conceptual diagrams showing reading by photoelectric scanning; FIG. 4 is a signal waveform read by FIG. Figure 5 is a diagram showing the concept of the crosshair operator, Figure 6 is a diagram showing an example of line thinning, Figure 7 is a diagram showing an example of end point detection, Figure 8 is an example of labeling. FIG. 9 is a block diagram showing the configuration of the labeling processing circuit; FIG. 10 is a flowchart showing the flow of the labeling processing circuit; FIG. 11 is a diagram showing an example of expansion processing; FIG. 12 is an example of labeling. 13 is a block diagram showing the configuration of the end point extraction circuit, FIG. 14 is a flowchart showing the flow of the end point extraction circuit, FIG. 15A is a diagram showing thinning of a wiring pattern without neck breakage, FIG. 15B is a diagram showing thinning of the wiring pattern that caused the neck breakage, FIG. 16 is a block diagram showing the configuration of the neck breakage determination circuit, FIG. 17 is a flowchart showing the flow of the neck breakage determination circuit, and FIG. 18A ~ Figures 18B and 19 are diagrams showing problems with the conventional technology. 11... Printed circuit board, 38... Window setting circuit, 39... Thinning circuit, 41... End point extraction circuit, 4
4...Neck breakage determination circuit, P...Wiring pattern, PI...Pattern image, H...Through hole, Hl...Hole image, PL...Thinned pattern, W: window,

Claims (1)

[Claims] (1) A printed circuit board pattern inspection method in which the printed circuit board is photoelectrically scanned and the relative positional relationship between the wiring pattern and the through hole on the printed circuit board is determined based on image data read for each pixel. (a) obtaining a pattern image representing the wiring pattern and a hole image representing the through hole based on the image data; (b) performing line thinning processing on the pattern image; (c) setting a window containing the hole image; (d) determining the number of end points of the thin line pattern image within the window; and (e) determining the end points. Detecting neck breakage in the wiring pattern from the number of pieces of the wiring pattern.