JPH05173803A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To perform the interrupt handling even at the time of a hold request by preventing a CPU from stopping the processing regardless of input of the hold request. CONSTITUTION:An operation control circuit 10 is added to the single chip microcomputer incorporating a CPU 2, an interrupt control circuit 1, a processing I/F 3, a peripheral part 6, a ROM 5, and a RAM 4, and it is designated whether the hold request should be processed as an interrupt handling request or be processed as a hold request to the CPU 2 in the conventional manner in accordance with the level of a preliminarily set control signal CNTL. That is, when the control signal CNTL is '1', a hold request signal HLDR is outputted as a request signal RQ1, and the interrupt control circuit 1 accepts this signal as the interrupt handling request and causes the CPU 2 to perform the interrupt handling and outputs an acknowledge signal AK1. An operation designating circuit 10 outputs the signal AK1 as a hold acknowledge signal HLDA.

Description

Detailed Description of the Invention

[0001]

This invention relates to a single semiconductor substrate,
The present invention relates to a single-chip microcomputer having a memory function and a computer function integrated, and more particularly to a single-chip microcomputer having a hold function and an interrupt function.

[0002]

2. Description of the Related Art In recent years, due to advances in LSI manufacturing technology, high integration has been advanced in the field of single-chip microcomputers, and multi-functionalization has become remarkable. In addition, the application field of single-chip microcomputers has expanded, and along with this, it has a memory outside the chip, and DMA
There are many examples of configuring a system using a controller.

In a system employing DMA, the DMA
The controller outputs a hold request to the single chip microcomputer, and the central processing unit (hereinafter,
The CPU holds the external bus and performs DMA transfer.

FIG. 4 is a block diagram showing the structure of a conventional single-chip microcomputer of this type. The single-chip microcomputer 400 includes an interrupt control circuit 1, a CPU 2, an external interface (hereinafter, referred to as an external I / F) 3, a RAM 4, a ROM 5, a peripheral section 6, internal buses 7 to 9 and signal lines thereof. ..
The ROM 5 is a read-only memory used for storing user programs and fixed data. The RAM 4 is a readable / writable memory used for storing data.

The internal bus 7 is a bus for transferring addresses and data in a time division manner. The internal bus 8 is a bus used when transferring an address from the internal bus 7 via the external I / F 3 when an external memory is accessed. The internal bus 9 is
This is a bus used when transferring data from the internal bus 7 via the external I / F 3 when accessing an external memory.

The CPU 2 performs data processing according to the programs stored in the ROM 5 and the external memory. CP
Program counter (hereinafter referred to as PC) 2a in U2
Is a register that stores the address of the instruction to be fetched. The CPU 2 determines that the hold request signal HLDR is "1".
Becomes, the hold acknowledge signal HLDA is set to "1".
As a result, the hold state is entered.

The peripheral section 6 is composed of a port for communicating with the outside of the chip, outputs data input via the internal bus 7 to the external terminal 6a, and outputs data input from the external terminal 6a to the internal. It has a function of outputting to the bus 7.

When the interrupt processing request signal INTPR is input from the outside, the interrupt control section 1 outputs the interrupt request signal INTR to the CPU 2. After that, the interrupt vector is output to the internal bus 7 in synchronization with the interrupt acceptance signal INTA output from the CPU 2. The CPU 2 executes the interrupt processing program according to the interrupt vector.

The external I / F 3 receives the read strobe signal RST when the hold acknowledge signal HLDA is "1".
B, write strobe signal WSTB, address signal A
All circuits for inputting and outputting the D and data signals DT are set to the high impedance state. Hold acknowledge signal H
When LDA becomes "0" and the hold state is released,
Read strobe signal RSTB, write strobe signal WSTB, address signal AD, and data signal DT are all activated.

Next, the hold request signal HLD of this conventional example.
The operation at the time of R input will be described. When the hold request signal HLDR input from the outside of the chip becomes "1", C
PU2 operates as follows according to the stored value of PC2a. When the stored value of the PC 2a indicates the ROM 5 inside the chip The CPU 2 continues the processing after outputting the hold acknowledge signal HLDA to the outside of the chip and the external I / F 3. The external I / F 3 is an input connected to an external circuit,
All output circuits are in high impedance state.

When the stored value of the PC 2a points to the memory area outside the chip The CPU 2 interrupts the processing after outputting the hold acknowledge signal HLDA to the outside of the chip and the external I / F 3.
Stop. Further, the external I / F 3 puts all the input and output circuits connected to the external circuit into a high impedance state.

When the hold request signal HLDR input from the outside of the chip becomes "0", it operates as follows. When the stored value of PC2a indicates the ROM5 in the chip CPU2 holds hold acknowledge H while continuing the processing.
Set LDA to “0”, and external I / F3 is
Release the high impedance state of the output circuit. When the stored value of the PC 2a indicates a memory area outside the chip The CPU 2 sets the hold acknowledge signal HLDA to "0" and restarts the processing. The external I / F 3 releases the high impedance state of its own input / output circuit.

As described above, in the conventional single-chip microcomputer, when the hold request signal is input during the execution of the program stored outside the chip, the processing of the CPU is stopped.

[0014]

In the above-mentioned conventional single-chip microcomputer, when a hold request is issued from the outside while the program stored in the external memory is being executed, the CPU interrupts the processing, and then the hold operation is performed. Even if there is an interrupt request, it will not be accepted until the status is cleared. Therefore, there is an inconvenience that even if there is an interrupt request that requires a high-speed response, it cannot be fulfilled. Further, conventionally, there is a drawback that the CPU is simply inactive in the hold state, so that the CPU usage efficiency is low and the system throughput is reduced.

[0015]

A single-chip microcomputer according to the present invention has a CP on a single semiconductor substrate.
U, a storage unit, an interrupt control unit, and an external interface unit are configured so that a hold request can be issued to the CPU, and an operation designating circuit is added, and a selection control signal is externally supplied to the operation designating circuit. By inputting, the operation designating circuit can select whether or not to instruct the CPU to stop the operation when a hold request is made in accordance with the selection control signal.

[0016]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. The single-chip microcomputer 100 of the present embodiment is designed so that the operation designating circuit 10 is newly added according to the present invention and signals are exchanged between the interrupt control circuit 1 and the operation designating circuit 10. 4 is different from the conventional example in FIG. 4 in other respects, but the other points are the same as the conventional example, and therefore the operation designating circuit 10 will be mainly described below.

A control signal C input to the operation designating circuit 10
NTL is a signal which is set to "1" or "0" by the user in advance. Then, the operation designating circuit 10
Hold request signal HLDR according to control signal CNTL
Is output as the request signal RQ ₀ or the request signal RQ ₁ ,
And acknowledge signal AK ₀ or acknowledge signal A
It has a function of outputting K ₁ as a hold acknowledge signal HLDA.

The structure and operation of the operation designating circuit 10 will be described below with reference to FIG. The operation designating circuit 10 includes a multiplexer 10a and a demultiplexer 10b.
It is a block composed of. Multiplexer 10a
Is the interrupt control circuit 1 when the control signal CTRL is "1".
The acknowledge signal AK ₁ output from the CPU 2 is output as the hold acknowledge signal HLDA, and when CTNL is “0”, the acknowledge signal AK ₀ output from the CPU 2 is output as the hold acknowledge signal HLDA.

The demultiplexer 10b has a control signal CT.
When RL is “1”, the hold request signal HLDR is output to the interrupt control circuit 1 as the request signal RQ ₁ , and CN
When TL is “0”, the hold request signal HLDR is output to the CPU ₂ as the request signal RQ ₀ .

Next, the operation of this embodiment when the hold request signal HLDR is set to "1" by an external DMA controller or the like will be described. The operation designating circuit 10 operates as follows according to the level of the control signal CTRL. If the operation designating circuit 10 of the control signal CNTL is "1", and outputs the request signal RQ _1, the interrupt control circuit 1 receives the signal as an interrupt processing request. The interrupt control circuit 1 sets the interrupt request signal INTR to "1" and requests the CPU 2 to perform interrupt processing. C
PU2 accepts an interrupt processing request at the final timing of instruction execution, and outputs an interrupt acceptance signal INTA.

The interrupt control circuit 1 outputs the interrupt vector information in synchronization with the interrupt acceptance signal INTA and sets the acknowledge signal AK ₁ to "1". The CPU 2 branches to the interrupt processing program stored in the internal ROM 5 according to the interrupt vector information. Then, the CPU 2 enters a standby state (when the processing program is expanded in the external memory) or returns to the original program (the processing program exists on the ROM 5 in the chip) according to the value stored in the PC 2a. If).

Since the control signal CNTL is "1", the operation control circuit 10 selects the acknowledge signal AK ₁ and outputs the hold acknowledge signal HLDA of "1". The external I / F 3 puts all the input and output circuits connected to the external circuit into a high impedance state. In this state, when the interrupt processing request signal INTPR becomes "1", the CPU 2 processes this interrupt request.

When the control signal CTRL is “0” The operation designating circuit 10 sets the hold request signal HLD of “1”.
R is output as a request signal RQ ₀ , and the CPU 2 receives the above signal as a hold request signal. The CPU 2 stops the operation, shifts to the hold state, and sets the acknowledge signal AK ₀ to “1”. The operation designating circuit 10 is
Acknowledge signal AK because the control signal CTRL is "0"
Select ₀ to select "1" hold acknowledge signal HL.
Output DA. The external I / F 3 puts all the input and output circuits connected to the external circuit into a high impedance state. In this state, even if an interrupt request is input from the outside, C
PU2 does not accept this request.

Next, the hold request signal HLDR is "0".
The operation of this embodiment when If the operation designating circuit 10 of the control signal CNTL is "1", and outputs the request signal RQ ₁ of "0" to the interrupt control circuit 1, the interrupt control circuit 1 determines that no interrupt processing request. When the CPU 2 is operating according to the program on the ROM 5, the processing is continued as it is. If the program in the external memory is in the waiting state during execution, the waiting state is released and the execution of the program is restarted. The interrupt control circuit 1 sets the acknowledge signal AK ₁ to “0”. Since the control signal CTRL is "1", the operation designating circuit 10 acknowledges the acknowledge signal A.
Select K ₁ and hold acknowledge signal H of “0”
Output LDA. The external I / F 3 releases the high impedance state of its input and output circuits.

When the control signal CTRL is “0” The operation designating circuit 10 outputs the request signal RQ ₀ of “0”, and the CPU 2 receives this signal as the hold release signal. The CPU 2 restarts the operation, releases the hold state, and sets the acknowledge signal AK ₀ to “0”.
The operation designating circuit 10 selects the acknowledge signal AK ₀ because the control signal CTRL is “0” and outputs the hold acknowledge signal HLDA of “0”. External I / F
3 releases the high impedance state of its input and output circuits.

As described above, in the first embodiment, the operation designating circuit composed of simple hardware is added and the value of the control signal is set appropriately,
The operation of the CPU at the time of inputting a hold request can be designated as either the interrupt mode or the hold mode.
When the interrupt mode is specified, the program stored in the internal ROM can be executed as an interrupt process even when the hold request is input, and the interrupt process request generated in the hold state can be processed promptly. it can. The hold state may reach several 100 μsec in the case of DMA transfer, for example, but in this embodiment several hundred instructions can be executed during this period.

FIG. 3 is a block diagram showing a second embodiment of the present invention. The single-chip microcomputer 300 of this embodiment is different from the embodiment shown in FIG. 1 in that the control signal CNTL for the operation designating circuit 10 is previously given by the user in the previous embodiment. In this embodiment, this signal is output from the interrupt mask flag 1a incorporated in the interrupt control circuit 1.

The stored value of the interrupt mask flag 1a is
Rewriting is possible by the CPU 2 via the internal bus 7. That is, the preset value is used as the control signal CNTL in the previous embodiment, but it can be appropriately designated by the user program or the like in the present embodiment, so that it can be applied to more various applications. ..

When the stored value of the interrupt mask flag 1a is "1" or "0", that is, the control signal CT
The operation when a hold request is issued to the single-chip microcomputer when RL is "1" or "0" is the same as in the previous embodiment, and therefore its explanation is omitted.

[0030]

As described above, the single-chip microcomputer of the present invention is provided with the operation designating circuit having a simple circuit configuration, and the CP is issued at the time of the hold request by the control signal.
Since the operation of U can be designated as the interrupt mode, the present invention can prevent the CPU from being stopped when a hold request is issued, unlike the conventional case. Therefore, according to the present invention, the CPU can be made to perform the interrupt processing even in the hold state, so that the resources can be effectively used and the processing capability of the microcomputer can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram of an operation designating circuit used in the first embodiment of the present invention.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram of a conventional example.

[Explanation of symbols]

1 interrupt control circuit 1a interrupt mask flag 2 central processing unit (CPU) 2a program counter (PC) 3 external interface section (external I / F) 4 RAM 5 ROM 6 peripheral section 6a external terminals 7, 8, 9 internal bus 10 operation Designating circuit 10a Multiplexer 10b Demultiplexer 100, 300, 400 Single-chip microcomputer AK ₀ , AK ₁ Acknowledge signal CTRL control signal HLDA hold acknowledge signal HLDR hold request signal INTA interrupt acceptance signal INTPR interrupt processing request signal INTR interrupt request signal RQ ₀ , RQ ₁ request signal RSTB read strobe signal WSTB write strobe signal

Claims (2)

[Claims] 1. A central processing unit which stops its operation when a hold request signal is input, an internal memory consisting of ROM and RAM, and an interrupt control which transmits an interrupt request signal to the central processing unit when the interrupt request signal is input. Circuit, external interface that connects to external circuit when hold acknowledge signal is input, input interface and output circuit are all in high impedance state, selection control signal is input, hold request signal is input And whether the hold request signal is transmitted to the central processing unit or the signal is transmitted to the interrupt control circuit as an interrupt request signal according to the state of the selection control signal, and a hold acknowledge signal is transmitted to the external interface. An operation designating circuit configured to communicate to a single semiconductor substrate Single-chip microcomputer comprising above. 2. A demultiplexer for transmitting a hold request signal to one of the interrupt control circuit and the central processing unit according to the state of the selection control signal, and the operation designating circuit according to the state of the selection control signal. The single-chip microcomputer according to claim 1, further comprising a multiplexer that outputs either an acknowledge signal output by the interrupt control circuit or an acknowledge signal output by the central processing unit as a hold acknowledge signal.