JPH0816535A - Cpu system - Google Patents

Abstract

PURPOSE:To transmit data at a high speed by connecting plural CPUs to a common bus and transmitting data between CPUs. CONSTITUTION:In the CPU system which has plural CPUs la to In connected to a common bus 2 for transmission of data (DT) and address data and performs the inter-CPU communication to transmit DT from desired one of these CPUs to another CPU, a shared memory (MEM) 4 connected to the common bus 2 and a decoding means (DEC) which decodes the write address to the MEN 4 to generate an interrupt signal to the CPU corresponding to a preliminarily set address (ADD) at the time of the write to a specific address area are provided, and each CPU 1 is provided with the function which writes transmission object data in a transmission data storage area (A1) or the MEM 4 at the time of data transmission, the function which accesses a specific ADD area on the MEM determined correspondingly to the CPU or the transmission destination to write a flag at the time of the end of write, and the function which accesses the Al of the MEM 4 to read in DT at the time of receiving the interrupt signal from the DEC.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU system having an improved data transmission system between a plurality of CPUs connected by a common bus.

[0002]

2. Description of the Related Art Generally, in order to perform data transmission between CPUs (processors), SIOs must be provided to the respective CPUs.
(Serial communication input / output device), CPU on the transmission side
Parallel data from the S in the CPU on the transmitting side.
This is performed by a method in which the IO is converted to serial and output, and the receiving side receives serial data by the receiving SIO, converts the serial data into parallel data, and loads the parallel data into the receiving CPU.

However, according to this method, SIO ports are required for each CPU as many as the number of CPUs to be communicated. Therefore, in order to implement this method, there are problems such as power consumption and mounting area. Therefore, it is difficult to communicate with a large number of CPUs, and the CPU on the transmitting side must control a plurality of SIOs.

In order to solve this problem, there is also a system in which a shared memory that can be commonly accessed by each CPU is provided. In this shared memory method, data to be transmitted is written in the shared memory by the CPU on the transmission side, and the other CPUs read the shared memo to take in the data.

However, in this shared memory system, when data is fetched from the shared memory, each CPU
There is a problem in that it is not suitable for communication of data that needs to be transmitted in real time, since it is inevitable that a time delay will occur because it will be read by polling.

[0006]

As described above, the SIO
In the method described above, since it is necessary to provide a one-to-one communication path to the CPU, a large number of serial controllers (for the number of communication paths) for performing serial communication control are required.
Therefore, there are problems that the power consumption of the system is increased, the mounting area is increased, and the load of the CPU is large.

Further, in the transfer method using the shared memory, since polling is performed when reading the shared memory, a time delay after the request for reading is inevitable, so that real-time data transmission cannot be performed. There is a problem to say.

Therefore, the object of the present invention is to
Low power consumption and space saving can be achieved.
An object of the present invention is to provide a CPU system capable of transmitting data in real time without increasing the load on the CPU.

[0009]

In order to achieve the above object, the present invention is configured as follows. That is, in a CPU system that connects a plurality of CPUs to a common bus that transmits data and address data, and performs inter-CPU communication that transmits data from a desired CPU among these CPUs to another CPU, A shared memory connected to a common bus is provided, and arbitration means for arbitrating access requests to the shared memory from each CPU to give one access right, and a write address for this shared memory are decoded and specified. Decoding means for generating an interrupt signal to a CPU corresponding to a preset address at the time of writing to the address area is provided, and the CPU makes an access request to the arbitration means to the arbitration means at the time of data transmission, and the arbitration means Transmission of data to be transmitted when access is given to shared memory A function of writing to a data storage area, a function of writing a flag by accessing a specific address area of a shared memory defined corresponding to the CPU of the transmission destination when the writing is completed, and the arbitration when an interrupt signal is received from the decoding means. And a function of requesting access to the shared memory to the means and accessing the transmission data storage area of the shared memory to read data when the access right is given from the arbitration means.

[0010]

The present invention has a shared memory that can be commonly accessed by each CPU, and an area for generating an interrupt to each CPU is provided in this shared memory. Each CPU
Wants to transmit data to another CPU, acquires the access right to the shared memory, writes the data to be transmitted to the transmission data storage area in the shared memory, and transmits the CP
Write arbitrary data to the interrupt generation area in the shared memory assigned to U. The shared memory has a decoding means for decoding the interrupt generation area, and when the area is accessed, the decoding means interrupts the corresponding CPU. This is because an interrupt line is individually provided from the decoding means to each CPU, and the interrupt line to the CPU corresponding to the transmission destination is activated among the individually provided interrupt lines. Interrupted C
The PU reads and fetches data from the transmission data storage area in the shared memory.

As described above, in the present invention, the shared memory is used for data transmission, and the shared memory is the CPU of the transmission destination.
Separately, an interrupt area for giving a forced interrupt is provided, and the transmission data is written in the shared memory, and an area corresponding to the transmission destination in the forced interruption area is accessed to generate an interrupt to the transmission destination CPU. Further, since the transmission data in the shared memory is read by the interrupt processing to the transmission destination CPU, real-time information transmission can be performed. Further, since the shared memory is used, the CPU does not need to perform transmission control such as serial transmission and polling, and the load can be reduced.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention relates to a plurality of Cs connected via a bus.
In a CPU system that transmits data between PUs, each CPU has a memory that can be accessed in common, and an interrupt generation address is set in an arbitrary area in this memory.
When data is transmitted, communication between CPUs can be performed in real time, and an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an overall configuration showing an embodiment of the present invention. Reference numerals ₁₁ to 1 _n are independent CPU boards on which processors (CPUs) are mounted, 2 is a CPU bus, and 3 is an interrupt. Signal lines 4 are shared memory substrates.

The CPU bus 2 is composed of a data bus for a plurality of bits, a plurality of control buses, and an address bus for a plurality of bits.
The PU boards 1 ₁ to 1 _n and the shared memory board 4 are connected to the buses.

The shared memory board 4 is one of the CPU boards 1 ₁ to 1
It is a board that has a memory shared by _n CPUs, and is C
By being connected by PU bus 2, it is also accessible from any CPU CPU substrate ₁ 1 on to 1 _n.

The interrupt signal line 3 is connected to each of the CPU boards 1 ₁ to 1
_n is a control line connected to the shared memory board 4 and is a line for transmitting an interrupt request from the CPUs of the CPU boards 1 ₁ to 1 _n.
It arranged independently of U substrate ₁ 1 each to 1 _n. The CPU used in the present invention is, for example, a 32-bit CPU,
It is a high-speed and high-performance processor such as a 64-bit CPU, which is inexpensive and easily available in recent years and can perform processing at high speed.

[0017] In this system, of the CPU board ₁ 1 to 1 _n, the data transmitted to the CPU board 1 _n other CPU board 1 _n-1 of the CPU 7 from the CPU desired that desired shared memory substrate 4 The data to be transmitted from the CPU 7 of the CPU board 1 _n via the CPU bus 2 is written to the shared memory in, and then the writing to the CPU 7 of the destination CPU board 1 _{n-1 in} the shared memory is assigned. Access the area. As a result, an interrupt request is issued from the shared memory board 4 to the CPU corresponding to the corresponding CPU board.

CP of CPU board 1 _n-1 which received interrupt
The U 7 reads the data from a predetermined area of the shared memory on the shared memory substrate 4 to obtain the CP.
CPU of U board 1 _n to CPU 7 of CPU board 1 _n-1
Is a mechanism for completing the data transmission to.

In order to do this, the system is constructed as follows. Details will be described. FIG. 2 is a schematic diagram of a configuration showing the connection between the CPU substrate 1 _n (n = 1, 2, 3, 4, ...) And the shared memory substrate 4, 5 is an address decoder, 6 is a shared memory, 7 is a CPU, 8 is a bus arbiter.

Of these, the shared memory 6 is a data readable / writable memory having an address space of at least a predetermined capacity, and the address space is for writing and delivering transmission data as shown in FIG. divided into a transmission data area, the transmission source of the transmission destination specifying flag area each CPU board 1 ₁ to 1 _n of the CPU board 1 ₁ to 1 _n separate transmission destination is allocated in advance the address corresponding to the (interrupt destination flag area) There is.

The address decoder 5 is connected to the input side of the address bus in the CPU bus 2 and has a plurality of terminals on the output side, and outputs a signal to a predetermined output terminal preset according to the input address data. (The output terminals are activated), and the output terminals are the corresponding CPU boards 1 ₁ to 1 out of the CPU boards 1 ₁ to 1 _n.
It is connected to the interrupt signal line connected to 1 _n .

[0022] That is, the address decoder 5 to the address bus of the CPU bus 2, when the transmission destination designation flag region (interrupt destination flag area) is the address data to be accessed has appeared, corresponding CPU board 1 ₁ to 1
_It has a function of decoding the address data so that the _n interrupt signal line connection terminal is activated, and the output of the activated interrupt signal line connection terminal is the corresponding CPU board 1 as the interrupt signal INT. _The configuration is such that it is applied to the interrupt signal terminals of the CPUs ₁ to 1 _n .

Therefore, when the transmission destination designation flag area of the shared memory 6 is accessed, the CPU of the CPU board corresponding to the accessed area is interrupted, and when the interrupt occurs, the transmission data of the shared memory 6 is interrupted. By providing the write area with an interrupt processing program for reading by the processing by this interrupt, the CPU of the CPU board of the transmission destination can be made to automatically read and take in the transmission data write area of the shared memory 6. I am able to do it.

The bus arbiter 8 arbitrates for a request for a bus request, and the bus arbiter 8 is connected to the bus request line BR from each of the CPU boards 1 ₁ to 1 _n on its input side. , When a bus request signal output from each of the CPU boards 1 ₁ to 1 _{n is} received via the corresponding bus request line BR, the request for the bus request from one of the CPU boards 1 ₁ (to 1 _n ) is accepted. , The CPU board 1 ₁ (to 1
_n ) to give the CPU bus 2 access right,
Bus board signal line BR corresponding to PU substrate 1 ₁ (to 1 _n ).
Has the function of activating.

FIG. 3 is a configuration example of each CPU board ₁ 1 to 1 _n-side, the one of the CPU board ₁ 1 to 1 _n also basically has the configuration of FIG. In FIG. 3, 9 is a chip select circuit, 10 is a bus request circuit, and 11 is an ACK.
It is a control circuit.

The chip select circuit 9 outputs a chip select signal when the output address of the CPU 7 on its own CPU board indicates a preset address, and the bus request circuit 10 outputs this chip select signal. In response to the output of the address strobe terminal (AS) and the output of the data strobe terminal (DS) of the CPU 7, the bus request signal B is received.
This is a circuit that outputs R.

Address strobe terminal (AS)
Is a status signal of the CPU 7 indicating that the address data is output from the CPU 7, and the signal output of the data strobe terminal (DS) is a data output status of the CPU 7. This is a status signal of the CPU 7 for notifying that.

Therefore, the address strobe terminal (A
When the signal S) is output, the CPU 7 has notified that the address data is being output from the CPU 7 and that the address data can be fetched, and the signal output of the data strobe terminal (DS) is At some time, the CPU 7 informs that the data is being output from the CPU 7 and the data can be fetched.

The ACK control circuit 11 transfers data from the bus request signal BR provided by the bus request circuit 10, the bus grant signal provided by the bus grant (BG) line of the bus arbiter 8, and the bus timeout monitoring circuit 12 described later. Data acknowledge (DTAC) which is output and given in the completion state
K) signal (this DTACK signal is, for example, a response signal that completes a data transfer cycle due to asynchronous transfer), and a bus error (B
ERR signal as input and data acknowledge (DT)
ACK) signal output circuit, the bus request signal BR and the bus grant (BG) line are in the active state, the data acknowledge (DTACK) signal is in the acknowledge (approval) state, and the bus error (BERR) signal When there is no signal, a data acknowledge signal is output and CP
It has a function of giving a signal to the data acknowledge (DTACK) terminal of U 7 and also giving a signal to the bus error (BERR) terminal of the CPU 7 when there is a bus error (BERR) signal. This is a circuit for informing the CPU 7 of whether or not the state is possible.

FIG. 4 is a block diagram showing the structure of the shared memory substrate 4. As shown in the figure, the shared memory board 4 is a shared memory 6 of a required capacity by a readable / writable random access memory connected to an address bus and a data bus, and a bus request for each CPU board 1 _n. Bus request signal B individually derived from the circuit 10
R output line is connected to each of these bus request signals B
The CPU board 1 which has given the access right to the bus grant signal BG for giving the access right to the bus so that the bus request signal BR from the R output line is not simultaneously accessed. It is a circuit that applies arbitration to the _n bus grant signal line and performs arbitration so as to prevent contention of bus access.

Further, as described above, the address decoder 5 fetches the address data on the address bus, decodes the address, and when the address data indicates a specific address, interrupts the CPU of the corresponding CPU boards 1 ₁ to 1 _n. This is a circuit for generating the signal INT, and as this specific address, an interrupt signal generation destination is set corresponding to an interrupt area in the shared memory 6 described later.

The bus time-out monitoring circuit 12 is a circuit for limiting the time of the access right to the bus. The address strobe terminal (A
S) and the address strobe signal or the data strobe signal from the data strobe terminal (DS), a bus error signal (B
ERR) is output to the ACK control circuit 11 of each of the CPU boards 1 ₁ to 1 _n to terminate the access right by the bus.
This is a circuit to notify as an error. The bus timeout monitoring circuit 12 outputs a data acknowledge (DTACK) signal when the data transfer is completed.

The address space allocation state in the shared memory 6 will be described in some detail with reference to FIG. As shown, the shared memory 6 and transmits the data write area of address space, a flag of the interrupt to the CPU board 1 ₁ each to 1 _n (written) to a specific region in advance divided into regions in the flag area for I have been assigned.

The shared memory 6 has, for example, addresses "01", "02", "03", "0" in the address space.
Areas 4 "to" 10 "are areas for setting a transmission destination flag when the CPU of the CPU substrate 1 _n as a transmission source CPU transmits to a CPU of another CPU substrate, and the address is" 01 "when using an area represents the transmission to the transmission destination of the CPU board 1 ₁ CPU from a transmission source CPU board 1 _n of the CPU, the address is" CPU board of the transmission source when using an area of 02 "1 from _n of the CPU indicating the transmission to the transmission destination of the CPU board 1 ₂ of the CPU.

The addresses are "11", "12",
In the areas "13", "14", and "20", the CPU of the CPU board 1n-1 is the other CPU as the transmission source CPU.
An area for make a destination flags when transmitting to the substrate of the CPU, the transmission from the CPU board 1 _n-1 of the transmission source in the case of using the area of the address "11" to the CPU board 1 ₁ CPU When the area of which the address is “12” is used, the CPU board 1 _n-1 of the transmission source to the CPU board 1
That is, it indicates transmission to the _second CPU.

Next, the operation of the present system having the above configuration will be described. First, an example in which the CPU of one CPU board 1 _n-1 transmits data to the CPU of another CPU board 1 _n-2 will be described. C
When the CPU of the PU board 1 _n-1 needs to transmit data to the CPU of the CPU board 1 _n-2 , the CPU board 1 _{n of} FIG.
_{The n−1} CPU transfers data to the shared memory substrate 4. At that time, CPU of CPU board 1 _n-1
Needs to obtain the access right of the CPU bus 2, and C
The CPU 7 of the PU board 1 _n-1 generates a bus request signal. That is, the CPU substrate 1 _n-1 has the configuration shown in FIG. 3, and the address data of the transmission data writing area in the shared memory 6 in the shared memory substrate 4 and
The data to be transmitted is generated by the CPU 7 in the CPU board 1 _n-1 .
An address strobe signal (AS) is generated by timing of data generation, and a data strobe signal (DS) is generated by timing of data generation to be transmitted.

Then, when the address / data in the transmission data write area is generated, the chip select circuit 9 generates a chip select signal and supplies it to the bus request circuit 10. As a result, the bus request circuit 10 becomes operable.

The address strobe signal (A
S), the data strobe signal (DS) is given to the bus request circuit 10, and when the bus request circuit 10 receives this signal, the bus request circuit (BR) which is its output line is activated.

The bus request (BR) lines from the CPU boards 1 ₁ to 1 _n are shared memory board 4 as shown in FIG.
Connected to the input side of the bus arbiter 8 and the bus request signal from the CPU board 1n-1 is input to the bus arbiter 8 and arbitrated there. As a result of this arbitration, if ready for access CPU bus 2, arbiter 8 CPU board 1 and the bus grant line to the CPU board 1 _n-1 a (BG) to activate the _n-1
Return to.

In this way, when the bus arbiter 8 receives a bus request from the CPU board, if the CPU bus 2 can be accessed, the CP requesting the bus request will be issued.
Notify by activating the bus grant line (BG) for U board.

The CPU board 1 _n-1 in which the bus grant line (BG) has become active has acquired the access right, and thus the CPU of the CPU board 1 _n-1 having the access right.
7 is a CPU for address data and data to be transmitted
The data is sequentially output to the bus 2 and a write signal is output to access the shared memory substrate 4 for writing, and the data to be transmitted is transferred (written) to the shared memory 6 on the shared memory substrate 4.

CPU board 1 after transfer (writing)
_n-1 sets a flag in the transfer destination (interrupt destination) area according to the interrupt area table of FIG. That is,
CPU board 1 _n-2 of the data transfer destination in the shared memory 6
Flag the corresponding address area.

Access to the transfer destination (interrupt destination) area in the shared memory 6 is constantly monitored by the address decoder 5 of FIG. 4 provided on the shared memory substrate 4, and the access to the transfer destination (interrupt destination) area is performed. When the access to the CPU board 1 _n-2 occurs, the address decoder 5 activates the interrupt signal line connected to the corresponding CPU board 1 _n-2 (generation of the interrupt signal INT to the CPU board 1 _n-2 ).

CPU board 1 of this address decoder 5
_The activation of the interrupt signal line connected to _n-2 informs the CPU board 1 _n-2 which is the transfer destination CPU board that there is transfer destination data. The CPU 7 of the CPU board 1n-2, which has been interrupted by the interrupt signal INT, starts interrupt processing, and first, its own CP.
A bus request signal is generated to acquire the access right of the U bus 2.

That is, the CPU substrate 1 _n-2 also has the configuration shown in FIG. 3, and when the interrupt processing by the interrupt signal INT is started, the address indicating the address area of the shared memory substrate 4 in which the transfer data is written is written. A data and a read signal for reading the data from the CPU bus 2 are generated from the CPU 7 in the CPU board 1 _n-2 . At this time, the CPU 7 uses the address strobe signal (AS) by timing the generation of the address data. ) Occurs,
A data strobe signal (DS) is generated by timing the generation of data to be transmitted.

These address strobe signals (A
S), the data strobe signal (DS) is given to the bus request circuit 10, and when the bus request circuit 10 receives this signal, the bus request circuit (BR) which is its output line is activated.

The bus request (BR) lines from the CPU boards 1 ₁ to 1 _n are shared memory board 4 as shown in FIG.
Connected to the input side of the bus arbiter 8 and the bus request signal from the CPU board 1 _n-2 is input to the bus arbiter 8 and arbitrated there. As a result of this arbitration, if ready for access CPU bus 2, the bus arbiter 8 CPU board 1 _n-2 CPU board 1 and the bus grant line (BG) active against _n-2
Return to.

The CPU board 1 _n-2 in which the bus grant line (BG) is activated has acquired the access right, and the CPU of the CPU board 1 _n-2 having the access right is acquired.
Reference numeral 7 sequentially outputs address data for accessing the address in which the transmission data is written to the shared memory 6, together with a read signal, and is read from the shared memory 6 and sequentially output to the CPU bus 2. Capture the data to be transmitted.

In this way, when the data to be transmitted is generated, it is written in the transmission data writing area of the predetermined shared memory 6 and a flag is set in the address corresponding to the predetermined transfer destination CPU in the shared memory 6. , An address decoder is used to generate an interrupt signal for the transfer destination CPU by using the address data obtained by accessing the shared memory 6 when this flag is set, and the transfer destination CPU receiving the interrupt signal performs interrupt processing. The transmission data writing area of the shared memory 6 is accessed to read and fetch data.

As a result, the communication between the CPUs is performed by the shared memory 6
Of the shared memory 6 is immediately transmitted to the transfer destination CPU by writing to the transfer data writing area and setting a flag in the area corresponding to the transfer destination CPU defined on the shared memory 6. This is completed only by reading the data writing area, and unlike the case of serial communication control, a communication control circuit for each communication line is unnecessary, and the circuit mounting area of each CPU board is reduced accordingly. In addition to reducing power consumption, it is not necessary to control each communication control circuit, which significantly reduces the load of software on the CPU.

Further, since data transmission only requires interrupt processing for writing and reading to and from the shared memory, there is no need for a long control time such as polling. In particular, as in recent years, 32-bit micro Processor (CPU) or 64-bit microprocessor (CP
As described in U), it is easy to use a processor that operates at an extremely high speed and that can easily handle data with a long data length. Therefore, real-time data transfer is possible due to the synergistic effect of reducing the CPU load. Become.

The present invention is not limited to the above-described embodiments, and can be carried out by appropriately modifying it within the scope not changing the gist thereof. In the above-mentioned embodiments, the data to be transmitted is stored in the shared memory. An interrupt is generated from the decoder to the CPU of the transmission destination by writing the flag in the interrupt generation area in the shared memory assigned to the CPU to be written and transmitted, but it is not always necessary to write the flag in the interrupt generation area. Instead, it is sufficient if the interrupt generation area can be accessed. Therefore, a method of writing arbitrary data instead of the flag or reading the interrupt generation area may be used. Even in this case, the decoder 5 decodes the address data associated with the access of the interrupt generation area of the shared memory from the transmitting side CPU, and when the area is accessed, the interrupt line individually provided to the corresponding CPU Is activated to generate an interrupt, and the CPU having the interrupt can read the data in the shared memory.

Further, for example, in the shared memory 6, an address space is used as a transmission data writing area, and each of the CPU boards ₁₁ .
The flag area for setting (writing) an interrupt flag for every 1 _n is divided into areas in advance, so that a new interrupt area outside the forced interrupt area is provided and the flag is set here for non-urgent data transmission. Stand, each CPU board 1
_In the CPUs ₁ to 1 _n , the shared memory 6 is checked by checking the flag state of the flag area for itself in the interrupt area.
It is also possible to adopt a configuration in which the transmission data in the inside is taken in arbitrarily. This is because the number of data bits in the flag area is many, so write control is performed by the CPU on the transmission side so that the bit position is changed to set a flag, and an area for writing information that does not need to be passed in real time is defined. It can be used in the case where it can be arbitrarily taken in by the user.

[0054]

As described above in detail, the present invention has a plurality of Cs.
In order to enable data transmission between PUs in real time, a shared memory that can be commonly accessed by each CPU is provided, and an area for generating an interrupt for each CPU is provided in this shared memory. In the communication of, the transfer destination CPU is interrupted by writing to the transfer data writing area of the shared memory and accessing the area corresponding to the transfer destination CPU defined in the shared memory, and the transfer processing immediately causes the transfer. Destination C
By causing the PU to read the transmission data writing area of the shared memory, the data transmission is completed, and unlike the case of serial communication control, a communication control circuit for each communication line is not required, and each CPU is correspondingly required. The board can reduce the circuit mounting area, reduce power consumption, and eliminate the need for control of each communication control circuit, thereby significantly reducing the load of software on the CPU.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an embodiment of the present invention,
FIG. 1 is a block diagram showing a schematic system configuration in an embodiment of the present invention.

FIG. 2 is a diagram for explaining an embodiment of the present invention,
CPU board 1 _n (n = 1, 2, 3, 3 of the system of the present invention
4, ...) And the schematic diagram showing the connection between the shared memory substrate 4.

FIG. 3 is a diagram for explaining an embodiment of the present invention,
Block diagram illustrating a configuration example of each CPU board 1 ₁ to 1 _n-side of the present invention system.

FIG. 4 is a diagram for explaining an embodiment of the present invention,
The block diagram which shows the structure of the shared memory board | substrate 4 of this invention system.

FIG. 5 is a diagram for explaining an embodiment of the present invention,
The figure which shows the allocation condition of the address space of shared memory.

[Explanation of symbols]

1 ₁ to 1 _n ... CPU board 2 ... CPU bus 3 ... Interrupt signal line 4 ... Shared memory board 5 ... Address decoder 6 ... Shared memory 7 ... CPU 8 ... Bus arbiter 9 ... Chip select circuit 10 ... Bus request circuit 11 ... ACK control circuit.

Claims (4)

[Claims] 1. A plurality of CPUs are connected to a common bus for transmitting data and address data, and these CPUs are connected.
In a CPU system for performing inter-CPU communication for transmitting data from a desired CPU to another CPU, a shared memory connected to the common bus is provided, and
Decoding means for decoding a write address to the shared memory and generating an interrupt signal to a CPU corresponding to a preset address when writing to a specific address area is provided, and each CPU has data to be transmitted at the time of data transmission. To a transmission data storage area of the shared memory, a function of accessing a specific address area of the shared memory defined corresponding to the CPU of the transmission destination when the writing is finished, and a shared memory when the interrupt signal is received from the decoding means. And a function of reading the data by accessing the transmission data storage area of the CP.
U system. 2. A plurality of CPUs are connected to a common bus for transmitting data and address data, and these CPUs are connected.
In a CPU system for performing inter-CPU communication for transmitting data from a desired CPU to another CPU, a shared memory connected to the common bus is provided, and
Decoding means for decoding a write address to the shared memory and generating an interrupt signal to a CPU corresponding to a preset address when writing to a specific address area is provided, and each CPU has data to be transmitted at the time of data transmission. To a transmission data storage area of the shared memory, a function of writing a flag by accessing a specific address area of the shared memory defined corresponding to the CPU of the transmission destination when the writing is completed, and an interrupt signal from the decoding means. A CPU system having a function of reading the data by accessing the transmission data storage area of the shared memory when receiving the data. 3. A plurality of CPUs are connected to a common bus for transmitting data and address data, and these CPUs are connected.
In a CPU system for performing inter-CPU communication for transmitting data from a desired CPU to another CPU, a shared memory connected to the common bus is provided, and
Arbitration means for arbitrating access requests to the shared memory from each CPU and giving access right to one, and for CPUs corresponding to preset addresses when decoding a write address for the shared memory and writing to a specific address area. Decoding means for generating an interrupt signal is provided, and the CPU requests the shared memory to access the arbitration means during data transmission, and transmits the data to be transmitted to the shared memory when the access right is given from the arbitration means. A function of writing data in the data storage area, a function of writing specific data by accessing a specific address area of the shared memory defined in correspondence with the CPU of the transmission destination when the writing is finished, and the arbitration upon receiving an interrupt signal from the decoding means. While requesting access to the shared memory to the means, A CPU system having a function of reading the data by accessing the transmission data storage area of the shared memory when the access right is given from the arbitration means. 4. A plurality of CPUs are connected to a common bus for transmitting data and address data, and these CPUs are connected.
In a CPU system for performing inter-CPU communication for transmitting data from a desired CPU to another CPU, a shared memory connected to the common bus is provided, and
Arbitration means for arbitrating access requests to the shared memory from each CPU and giving access right to one, and for CPUs corresponding to preset addresses when decoding a write address for the shared memory and writing to a specific address area. Decoding means for generating an interrupt signal is provided, and the CPU requests the shared memory to access the arbitration means during data transmission, and transmits the data to be transmitted to the shared memory when the access right is given from the arbitration means. A function of writing to the data storage area, a function of writing a flag by accessing a specific address area of the shared memory defined corresponding to the CPU of the transmission destination when the writing is completed, and the arbitration means upon receiving an interrupt signal from the decoding means. Request for shared memory access and arbitration A CPU system having a function of accessing the transmission data storage area of the shared memory and reading data when an access right is given from the means.