JPH05166966A - Semiconductor device mounting board - Google Patents
Semiconductor device mounting boardInfo
- Publication number
- JPH05166966A JPH05166966A JP32854991A JP32854991A JPH05166966A JP H05166966 A JPH05166966 A JP H05166966A JP 32854991 A JP32854991 A JP 32854991A JP 32854991 A JP32854991 A JP 32854991A JP H05166966 A JPH05166966 A JP H05166966A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- semiconductor device
- mounting
- board
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の実装用基
板に関し、特に、半導体装置搭載用位置決め用パタ−ン
及び半田仮付け用パタ−ンを設けた実装用基板に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting board for a semiconductor device, and more particularly to a mounting board provided with a positioning pattern for mounting a semiconductor device and a temporary soldering pattern.
【０００２】[0002]
【従来の技術】封止の完了した半導体装置を実装する為
に、実装用基板が使用されている。実装用基板には各種
のものがあり、プリント配線基板はその一例をなす。プ
リント配線基板は、例えば、樹脂基板上にスクリ−ン印
刷により配線パタ−ンを配設してなり、当該基板を用い
た実装は、例えば、当該基板上に、表面実装型半導体装
置を搭載し、当該半導体装置の内部配線を外部に取出さ
せる為のアウタ−リ−ドを前記配線パタ−ンに半田付け
することにより行われる。2. Description of the Related Art A mounting substrate is used to mount a semiconductor device that has been completely sealed. There are various types of mounting boards, and a printed wiring board is one example. The printed wiring board is, for example, provided with a wiring pattern by screen printing on a resin substrate. For mounting using the substrate, for example, a surface mount semiconductor device is mounted on the substrate. An outer lead for taking out the internal wiring of the semiconductor device to the outside is soldered to the wiring pattern.
【０００３】[0003]
【発明が解決しようとする課題】しかるに、上記従来技
術では、表面実装型半導体装置を基板へ実装する際に、
手作業によって、位置決めを行ない、アウタ−リ−ドの
コ−ナ−部を仮半田付してから、ヒ−トコラムにより本
半田付を行なうので、位置合せが難しく、また位置合せ
ズレも生じ易いという問題点があった。本発明は、かか
る従来技術の有する欠点を解消し、実装時の位置合せを
容易にし、更に、位置合わせズレを防止し、半田の表面
張力による自己位置補正作用を可能とする技術を提供す
ることを目的とする。本発明の前記ならびにそのほかの
目的と新規な特徴は、本明細書の記述および添付図面か
らあきらかになるであろう。However, in the above prior art, when mounting the surface mount semiconductor device on the substrate,
Positioning is done by hand, and the outer lead corners are temporarily soldered and then main soldering is performed by the heat column. There was a problem. The present invention provides a technique that solves the drawbacks of the conventional technique, facilitates alignment during mounting, prevents misalignment, and enables a self-position correction action by the surface tension of solder. With the goal. The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.
【０００４】[0004]
【課題を解決するための手段】本願において開示される
発明のうち代表的なものの概要を簡単に説明すれば、下
記のとおりである。すなわち、本発明では、通常の電気
信号を取り出す為の配線パタ−ンとは形状、位置など形
態が異なったパタ−ンを実装用基板に設けるようにし
た。The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, in the present invention, the mounting board is provided with a pattern, such as a shape and a position, which is different from that of the wiring pattern for extracting an ordinary electric signal.
【０００５】[0005]
【作用】本発明による位置決め用パタ−ン及び半田仮付
用パタ−ンは、他の電気信号を取り出す為のパタ−ン
（配線パタ−ン）とは、形状、位置等その形態が異なっ
たものとしている。従って、位置合わせ及び半田仮付時
には、タ−ゲットの役目をなし、作業が容易となる。ま
た、パタ−ン形状を工夫することにより、半田の表面張
力が大きくなるので、合わせズレが生じた場合、アウタ
−リ−ドが半田の中心に引き寄せられて自己位置補正す
る。The pattern for positioning and the pattern for temporary soldering according to the present invention are different in shape and position from the pattern (wiring pattern) for taking out other electric signals. I am supposed to. Therefore, at the time of alignment and temporary soldering, it serves as a target and the work becomes easy. Further, since the surface tension of the solder is increased by devising the pattern shape, when the misalignment occurs, the outer lead is attracted to the center of the solder and the self-position is corrected.
【０００６】[0006]
【実施例】以下、本発明の一実施例を図面により説明す
る。図１に示すように、実装用基板１において、通常の
電気信号を取り出すための配線パタ−ン２とは形状が異
なったパタ−ン３を設ける。当該実装用基板１は、例え
ば、エポキシ樹脂などからなる樹脂基板から構成されて
いる。当該基板１の表面には、例えば、スクリ−ン印刷
により、例えばＣｕ箔よりなる配線パタ−ン２が形成さ
れている。また、当該基板１の表面には、当該配線パタ
−ン２に加えて、同様にＣｕ箔よりなり、該配線パタ−
ン２より大きな形状のパタ−ン３を設けており、当該パ
タ−ン３を位置決めパタ−ンおよび仮半田付パタ−ンと
なしてある。当該基板１に搭載される半導体装置４は、
図示例のごとく 表面実装型に構成され、また、樹脂封
止型に構成され、その図示が省略されているが、封止部
の内部には、半導体素子が内蔵され、当該素子の電極と
リ−ドフレ−ムのインナ−リ−ドとがワイヤボンディン
グされ、該リ−ドフレ−ムのアウタリ−ド５が、図に示
すように、その封止部の外部に引出されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 1, a mounting board 1 is provided with a pattern 3 having a shape different from that of a wiring pattern 2 for extracting an ordinary electric signal. The mounting substrate 1 is composed of, for example, a resin substrate made of epoxy resin or the like. On the surface of the substrate 1, a wiring pattern 2 made of, for example, a Cu foil is formed by screen printing, for example. Further, in addition to the wiring pattern 2, the surface of the substrate 1 is also made of Cu foil, and the wiring pattern is also formed.
A pattern 3 having a shape larger than the pattern 2 is provided, and the pattern 3 serves as a positioning pattern and a temporary soldering pattern. The semiconductor device 4 mounted on the substrate 1 is
Although it is configured as a surface mount type as shown in the figure and also as a resin sealing type, the illustration of which is omitted, a semiconductor element is built in the sealing portion, and electrodes and electrodes of the element are connected. -The inner frame of the lead frame is wire-bonded, and the outer lead 5 of the lead frame is drawn out to the outside of the sealing portion as shown in the figure.
【０００７】当該基板１上への半導体装置４の実装に際
し、パタ−ン３を位置決めの基準として位置合わせす
る。当該パタ−ン３は、図示のように、２カ所コ−ナ−
部に配置されている。従って、これにより半導体装置４
の当該基板１への実装時に、そのアウタ−リ−ド５と当
該基板１表面の配線パタ−ン２の位置合わせが容易とな
る。When mounting the semiconductor device 4 on the substrate 1, the pattern 3 is aligned as a positioning reference. The pattern 3 has two corners as shown in the figure.
It is located in the section. Therefore, the semiconductor device 4
It becomes easy to align the outer lead 5 and the wiring pattern 2 on the surface of the board 1 when the board is mounted on the board 1.
【０００８】上記例では、コ−ナ−部に四辺形の位置決
めおよび半仮田付パタ−ンを構成した例を示したが、本
発明では、当該パタ−ン３の形状配置などの形態を各種
のものに変更することが可能であり、図３は、パタ−ン
３の形状を十字型に構成した例を示し、また、図４は、
コ−ナ−部でなく、中央部に、四辺形の位置決めおよび
半仮田付パタ−ンを構成した例を示す。In the above example, the corner portion is provided with a quadrilateral positioning pattern and a semi-tempered pattern, but in the present invention, various shapes such as the shape of the pattern 3 are arranged. FIG. 3 shows an example in which the pattern 3 is formed in a cross shape, and FIG. 4 shows
An example in which a quadrilateral positioning and pattern with a semi-tempered pad is formed in the central portion, not in the corner portion, is shown.
【０００９】図２は、半田付実装の断面の一例を示す。
当該実装において、本発明では、上記パタ−ン３を、図
１で示すように配線パタ−ン２に比して大きく構成する
ことにより、半田６の表面張力が大きくなる為、アウタ
−リ−ド５とパタ−ン２との合わせズレが生じた場合、
アウタ−リ−ド５がパタ−ン２の中心に引き寄せられて
自己位置補正することができる。FIG. 2 shows an example of a cross section of soldering mounting.
In the mounting, according to the present invention, the surface tension of the solder 6 is increased by making the pattern 3 larger than the wiring pattern 2 as shown in FIG. If there is a misalignment between the pattern 5 and the pattern 2,
The outer lead 5 is attracted to the center of the pattern 2 so that the self-position can be corrected.
【００１０】以上本発明者によってなされた発明を実施
例にもとずき具体的に説明したが、本発明は上記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることはいうまでもない。以上の説
明では主として本発明者によってなされた発明をその背
景となった利用分野である表面実装型半導体装置に適用
した場合について説明したが、それに限定されるもので
はなく、表面実装型電子部品等に広く応用できる。The present invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. In the above description, the case where the invention made by the present inventor is mainly applied to the surface mounting type semiconductor device which is the field of application which is the background has been described, but the present invention is not limited thereto and the surface mounting type electronic component or the like Can be widely applied to.
【００１１】[0011]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。本発明によれば、半導体装置実装時
の位置合わせが容易となるので、作業効率を向上させる
ことができ、また、位置ズレが防止されることにより、
基板再生率を低減させることができる。The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows. According to the present invention, it is possible to easily perform the alignment when mounting the semiconductor device, so that it is possible to improve the work efficiency and prevent the positional deviation.
The substrate recycling rate can be reduced.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明の一実施例の平面図FIG. 1 is a plan view of an embodiment of the present invention.
【図２】本発明の一実施例の要部断面図FIG. 2 is a sectional view of an essential part of an embodiment of the present invention.
【図３】本発明のさらに他の実施例の平面図FIG. 3 is a plan view of still another embodiment of the present invention.
【図４】本発明のさらにまた他の実施例の平面図FIG. 4 is a plan view of still another embodiment of the present invention.
１・・・実装用基板 ２・・・配線パタ−ン ３・・・位置決め及び半田仮付用パタ−ン ４・・・半導体装置 ５・・・アウタ−リ−ド ６・・・半田 DESCRIPTION OF SYMBOLS 1 ... Mounting substrate 2 ... Wiring pattern 3 ... Positioning and temporary soldering pattern 4 ... Semiconductor device 5 ... Outer lead 6 ... Solder
フロントページの続き (72)発明者 小原 哲治 東京都小平市上水本町５丁目20番１号 日 立超エル・エス・アイ・エンジニアリング 株式会社内 (72)発明者 細江 英之 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所デバイス開発センタ内Front Page Continuation (72) Inventor Tetsuji Obara 5-201-1, Josui Honcho, Kodaira-shi, Tokyo Hirate Super LSI Engineering Co., Ltd. (72) Inventor Hideyuki Hosoe, Kodaira-shi, Tokyo 5-20-1 Honmachi, Hitachi, Ltd. Device Development Center
Claims (2)
配線パタ−ンを有する実装用基板において、該配線パタ
−ンとは異なった形態のパタ−ンを設け、当該パタ−ン
を半導体装置搭載用位置決め及び半田仮付け用パタ−ン
となしたことを特徴とする半導体装置の実装用基板。1. A mounting substrate having a wiring pattern for extracting an electrical signal from a semiconductor device, wherein a pattern different from the wiring pattern is provided, and the pattern is the semiconductor device. A mounting board for a semiconductor device, which has a pattern for mounting positioning and temporary soldering.
用パタ−ンを、配線パタ−ンに比して大きく構成してな
る、請求項１に記載の半導体装置の実装用基板。2. The mounting board for a semiconductor device according to claim 1, wherein the positioning pattern for mounting the semiconductor device and the temporary soldering pattern are configured to be larger than the wiring pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32854991A JPH05166966A (en) | 1991-12-12 | 1991-12-12 | Semiconductor device mounting board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32854991A JPH05166966A (en) | 1991-12-12 | 1991-12-12 | Semiconductor device mounting board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05166966A true JPH05166966A (en) | 1993-07-02 |
Family
ID=18211522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32854991A Withdrawn JPH05166966A (en) | 1991-12-12 | 1991-12-12 | Semiconductor device mounting board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05166966A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002280477A (en) * | 2001-03-16 | 2002-09-27 | Sony Corp | Circuit board |
| JP2009146969A (en) * | 2007-12-12 | 2009-07-02 | Shinko Electric Ind Co Ltd | Semiconductor package |
-
1991
- 1991-12-12 JP JP32854991A patent/JPH05166966A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002280477A (en) * | 2001-03-16 | 2002-09-27 | Sony Corp | Circuit board |
| JP2009146969A (en) * | 2007-12-12 | 2009-07-02 | Shinko Electric Ind Co Ltd | Semiconductor package |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990311 |