JPH0513760A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device having a structure wherein a short channel effect caused by making the device finner is restricted and high speed high integration is ensured. CONSTITUTION:A concave portion is provided in a gate part of a semiconductor substrate 1, and a gate electrode 8 is provided in the concave portion 5 through an oxide film 4. Further, a source region 3a and a drain region 3b are formed on a semiconductor substrate 1 surface sides of the concave portion 5, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a MOS transistor.

[0002]

2. Description of the Related Art Conventionally, MOS transistors have been miniaturized for the purpose of high speed and high integration. Since the short channel effect becomes remarkable due to this miniaturization, a structure using an LDD structure as shown in FIG. 4 is used to avoid this. A transistor using this LDD structure has a P ⁻ diffusion layer 102 on the surface layer of a semiconductor substrate 101.
Is formed, and is made of polysilicon via the oxide film 105 at the gate formation portion of the P ⁻ diffusion layer 102.
The gate 106 covered with 05 is formed, and the N ⁻ diffusion layer 104 formed by implanting low concentration ions such as As in that state is formed. Further, spacers 107 made of CVD SiO ₂ are formed on both sides of the gate 106, and then N ⁺ source / drain regions 103 are formed by implanting high concentration ions such as As in this state. An interlayer insulating film 108 is formed on the oxide film 105, and an electrode 109 is formed on the N ⁺ source / drain region 103. As described above, in the conventional example, N ⁺ source /
The impurity distribution of the drain region 103 is graded junction, and N ⁻
The diffusion layer 104 is a region for relaxing a high electric field.

[0003]

However, in the conventional technique, the number of steps for forming the above-mentioned LDD structure has been increased and has been complicated. Further, on the other hand, higher speed and higher integration are desired, and miniaturization is inevitable. The present invention has been made in view of the above points, and does not require a complicated structure such as an LDD for suppressing the short channel effect due to miniaturization or a complicated process for manufacturing the high speed and high speed. It is an object to provide a semiconductor device having a structure that enables integration.

[0004]

According to another aspect of the present invention, there is provided a semiconductor device in which a recess is provided in a gate portion of a semiconductor substrate, and a gate electrode is provided in the recess through an oxide film, and
It is characterized in that a source region and a drain region are respectively formed in the surface layer of the semiconductor substrate on both sides of the depression.

[0005]

Since the semiconductor substrate is provided with the depression and the source region and the drain region are respectively formed on the substrate surface layers on both sides of the depression, the effective channel length is smaller than the distance between the source-drain regions. become longer. Therefore,
The short channel effect can be suppressed.

[0006]

EXAMPLE FIG. 1 is a schematic sectional view of an example of the present invention.
The structure will be described with reference to the drawings. The P-type semiconductor substrate 1 is provided with a depression 5, and the N ⁺ diffusion layers 3 are formed on the surface layers of the P-type semiconductor substrate 1 on both sides of the depression 5, forming a source region 3a and a drain region 3b, respectively. Further, a gate oxide film 4 is formed on the surface of the depressed portion 5 and on the N ⁺ diffusion layer 3, and N is formed on the gate oxide film 4.
⁺ Polysilicon 6 is deposited and the N ⁺ polysilicon 6
An interlayer insulating film 7 is formed on the surface with the gate oxide film 4 interposed therebetween. Further, electrodes 8 are formed on the source region 3a and the drain region 3b, respectively.

A method of manufacturing the semiconductor device having the above structure according to the embodiment of the present invention will be described below with reference to FIG. First, SiN2 is formed on the surface of the P-type semiconductor substrate 1 by the CVD method.
After 0 is deposited, a resist 21 is formed on the SiN 20. After that, the resist 21 is opened by a well-known photolithography process, and Si of the portion where the LOCOS oxide film is formed
N20 is removed [FIG. 2 (a)].

Next, the resist 2 remaining on the SiN 20
1 is removed and selective oxidation is performed to form a LOCOS oxide film 10 [FIG. 2 (b)]. Next, after removing the SiN 20 remaining on the surface of the P-type semiconductor substrate 1, impurities such as arsenic are diffused using the LOCOS oxide film 10 as a mask to form an N ⁺ diffusion layer 3 (FIG. 2C). ].

Next, the recess 5 is formed by removing the LOCOS oxide film 10. After that, the gate oxide film 4 is formed on the surface of the P-type semiconductor substrate 1 including the depression 5 [FIG. 2 (d)]. Then, N ^{+ is formed} on the gate oxide film 4.
Polysilicon 6 is deposited, and gate oxide film 4 is formed on the surface of N ⁺ polysilicon 6. Next, an interlayer insulating film 7 is formed on the gate oxide film 4. Finally, a desired semiconductor device is formed by removing the interlayer insulating film 7 and the gate oxide film 4 at the portions where the respective electrodes are formed on the source region 3a and the drain region 3b to form the electrode 8. Figure 1].

The method of manufacturing the present invention is not limited to the method described above, and the method shown in FIG. 3 can be used.
The method will be described below with reference to FIG. First, the N ⁺ diffusion layer 3 is formed on the surface of the P-type semiconductor substrate 1 by diffusing impurities such as arsenic [FIG. 3 (a)].
Next, the thick to form a SiO ₂ film 30 on the P-type semiconductor substrate 1 on the surface, opening the SiO ₂ film 30 on its top to form a recess [FIG 3 (b)].

Next, using the SiO ₂ film 30 as a mask, the depression 5 is formed in the P-type semiconductor substrate 1 by isotropic dry etching or wet etching [FIG.
(C)]. Next, the gate oxide film 4 is formed on the surface of the P-type semiconductor substrate 1 including the depression 5 [FIG. 3 (d)]. Then, the subsequent steps are performed in the same manner as the above method.

That is, N ⁺ polysilicon 6 is deposited on the gate oxide film 4, and the gate oxide film 4 is formed on the surface of the N ⁺ polysilicon 6. Next, an interlayer insulating film 7 is formed on the gate oxide film 4. Finally, the source region 3a
A desired semiconductor device is formed by removing the interlayer insulating film 7 and the gate oxide film 4 at the portions where the respective electrodes are formed on the drain region 3b and forming the electrode 8 [FIG. 1].

[0013]

As described above, according to the present invention, the semiconductor substrate is provided with the depression and the channel of the MOS transistor is formed in the depression.
Compared to the OS structure, the effective channel length of the gate becomes longer,
The short channel effect can be suppressed. In addition, L
Does not require a complicated process for forming a DD structure,
The process can be simplified. Moreover, the MOS structure can be further miniaturized, and high speed and high integration can be realized,
Further, the chip size can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a manufacturing method according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a manufacturing method according to an embodiment of the present invention.

FIG. 4 is a schematic sectional view of a conventional example.

[Explanation of symbols]

1 ... P type semiconductor substrate 3 ... N ⁺ diffusion layer 3a ... Source region 3b ... Drain region 4 ... Gate oxide film 5 ... Depression 6 ... ..N ⁺ polysilicon 7 ... Interlayer insulating film 8 ... Electrode

Claims (1)

Claim: What is claimed is: 1. A depression is provided in a gate portion of a semiconductor substrate, a gate electrode is provided in the depression through an oxide film, and a surface of the semiconductor substrate on both sides of the depression. A semiconductor device in which a source region and a drain region are formed in each layer.