JPH0510697B2 - - Google Patents

Info

Publication number
JPH0510697B2
JPH0510697B2 JP61048124A JP4812486A JPH0510697B2 JP H0510697 B2 JPH0510697 B2 JP H0510697B2 JP 61048124 A JP61048124 A JP 61048124A JP 4812486 A JP4812486 A JP 4812486A JP H0510697 B2 JPH0510697 B2 JP H0510697B2
Authority
JP
Japan
Prior art keywords
buffer
processing request
processing
processor
control unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61048124A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62204356A (ja
Inventor
Satoshi Sugiura
Hiroyuki Egawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4812486A priority Critical patent/JPS62204356A/ja
Publication of JPS62204356A publication Critical patent/JPS62204356A/ja
Publication of JPH0510697B2 publication Critical patent/JPH0510697B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP4812486A 1986-03-04 1986-03-04 多重チャネル処理装置 Granted JPS62204356A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4812486A JPS62204356A (ja) 1986-03-04 1986-03-04 多重チャネル処理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4812486A JPS62204356A (ja) 1986-03-04 1986-03-04 多重チャネル処理装置

Publications (2)

Publication Number Publication Date
JPS62204356A JPS62204356A (ja) 1987-09-09
JPH0510697B2 true JPH0510697B2 (enExample) 1993-02-10

Family

ID=12794580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4812486A Granted JPS62204356A (ja) 1986-03-04 1986-03-04 多重チャネル処理装置

Country Status (1)

Country Link
JP (1) JPS62204356A (enExample)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6017141B2 (ja) * 1981-10-30 1985-05-01 株式会社日立製作所 多重制御装置

Also Published As

Publication number Publication date
JPS62204356A (ja) 1987-09-09

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