JPH0499373A - Semiconductor memory cell - Google Patents

Semiconductor memory cell

Info

Publication number
JPH0499373A
JPH0499373A JP2217625A JP21762590A JPH0499373A JP H0499373 A JPH0499373 A JP H0499373A JP 2217625 A JP2217625 A JP 2217625A JP 21762590 A JP21762590 A JP 21762590A JP H0499373 A JPH0499373 A JP H0499373A
Authority
JP
Japan
Prior art keywords
electrode
capacitor
semiconductor memory
cylinder
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2217625A
Other languages
Japanese (ja)
Inventor
Shinya Kawarabayashi
河原林 真也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2217625A priority Critical patent/JPH0499373A/en
Publication of JPH0499373A publication Critical patent/JPH0499373A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To increase a charge storage capacity, and to prevent difficulty of inversion of stored information even if charge leakage occurs by providing a plurality of cylinders for forming first electrodes of capacitors concentrically. CONSTITUTION:A first electrode 20 of a capacitor is formed of a disc 23 and two cylinders 24a, 24b provided concentrically on the disc 23, and a dielectric 21 and a second electrode 22 are provided on the outer surface of the electrode 20. The outer diameter of the disc 23 is set to substantially the same size and shape as those of prior art. An inner cylinder 24a is set to slightly larger inner diameter than that of a contact hole 16 of an insulating film 13, and smaller diameter than that of a conventional cylinder 24. On the other hand, the outer cylinder 24b is provided near the outer peripheral edge of the cylinder 23, and set to slightly larger inner diameter than that of the conventional cylinder 24. That is, in a capacitor, since the two cylinders 24a, 24b are provided, charge storage capacity is larger than that of prior art.

Description

【発明の詳細な説明】 (産業上の利用分野〕 本発明は、MOSトランジスタとキャパシタとで構成さ
れる半導体記憶素子(メモリセル)に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory element (memory cell) composed of a MOS transistor and a capacitor.

〔従来の技術〕[Conventional technology]

従来のこの種の半導体記憶素子を第3図に示して説明す
る。図は要部の断面図を示している。
A conventional semiconductor memory element of this type will be explained with reference to FIG. The figure shows a sectional view of the main part.

図中、10はシリコンなどの半導体基板、11.12は
半導体基板1の内部上方に隣合わせに離間して拡散形成
されかつソースを形成する不純物拡散層、ドレインを形
成する不純物拡散層、13は半導体基板10上に積層形
成された酸化膜からなる絶縁膜、14はソース・ドレイ
ンを形成する不純物拡散11i11と12との間で絶縁
膜13の内部下方に埋設形成された不純物ドープのポリ
シリコンなどからなるゲート電極であり、ゲート電極1
4とこの直下に形成されているゲート酸化膜15とでM
OSトランジスタが構成されている。
In the figure, 10 is a semiconductor substrate such as silicon, 11, 12 is an impurity diffusion layer that is diffused and formed adjacent to each other and spaced apart from each other inside the semiconductor substrate 1, and forms a source, an impurity diffusion layer that forms a drain, and 13 is a semiconductor. An insulating film made of an oxide film laminated on the substrate 10, 14 made of impurity-doped polysilicon etc. buried in the inside of the insulating film 13 between impurity diffusion 11i11 and 12 forming the source/drain. Gate electrode 1
4 and the gate oxide film 15 formed directly below M.
An OS transistor is configured.

そして、20は不純物ドープのポリシリコンなどからな
る第1′r!j、極、21は第1電極20の外表面に被
覆形成された酸化膜からなる誘電体、22は誘電体21
のさらに外表面に被覆される不純物ドープのポリシリコ
ンからなる第2電極であり、これらでキャパシタが構成
されている。
20 is the 1'r! made of impurity-doped polysilicon or the like. j, pole; 21 is a dielectric made of an oxide film coated on the outer surface of the first electrode 20; 22 is a dielectric 21;
A second electrode made of impurity-doped polysilicon is coated on the outer surface of the capacitor, and these constitute a capacitor.

なお、第1電極20は、上記MO3トランジスタの上方
において絶縁膜13上に被覆形成されかつ中央部分がコ
ンタクトホール16を通じて上記ドレイン拡散層12に
接する円板部23と、この円板部23の上面に設けられ
る単一の円筒部24とからなり、誘電体21および第2
電極22については前記第1電極20の外形にならった
形状となっている。
The first electrode 20 includes a disk portion 23 which is formed over the insulating film 13 above the MO3 transistor and whose central portion is in contact with the drain diffusion layer 12 through the contact hole 16, and an upper surface of the disk portion 23. It consists of a single cylindrical part 24 provided in the dielectric 21 and the second cylindrical part 24.
The electrode 22 has a shape that follows the outer shape of the first electrode 20.

このような構造の半導体記憶素子において、キャパシタ
の容量は、その表面積により決まる。
In a semiconductor memory element having such a structure, the capacitance of a capacitor is determined by its surface area.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところで、上記従来の半導体記憶素子では、次のような
不都合がある。
However, the conventional semiconductor memory element described above has the following disadvantages.

例えば、キャパシタに蓄積している電荷が、半導体基板
10内部にリークするといった現象が起こるが、電荷リ
ークが変電なると、キャパシタの蓄積電荷量が減少し、
ひいては情報が反転するといったことにもなりかねない
For example, a phenomenon occurs in which the charge accumulated in a capacitor leaks into the semiconductor substrate 10, but when the charge leakage is transformed, the amount of charge accumulated in the capacitor decreases.
This could even lead to information being reversed.

このような不都合を回避するには、半導体記憶素子にお
けるキャパシタ容量をできる限り大きくしておくのが望
ましいが、従来のものではその構造上容量を大きくする
にも限りがあり、上記のような電荷リークによって情報
反転するといった不都合が起こりうるのである。
In order to avoid such inconveniences, it is desirable to increase the capacitance of the capacitor in semiconductor memory elements as much as possible, but with conventional devices, there is a limit to how much capacitance can be increased due to their structure, and the above-mentioned charge Leaks can cause inconveniences such as information being reversed.

本発明はこのような事情に鑑みて創案されたもので、キ
ャパシタの占有面積が増えることをできる限り抑えなが
らも、キャパシタを大容量化することを目的としている
The present invention was devised in view of the above circumstances, and an object of the present invention is to increase the capacity of a capacitor while suppressing the increase in the area occupied by the capacitor as much as possible.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、上記目的を達成するために、MOSトランジ
スタとキャパシタとで構成される半導体記憶素子におい
て、次のような構成をとる。
In order to achieve the above object, the present invention employs the following configuration in a semiconductor memory element composed of a MOS transistor and a capacitor.

本発明の半導体記憶素子では、前記キャパシタを、 MOSトランジスタを覆う絶縁膜上に設けられかつ一部
がMOSトランジスタのソースまたはドレインを形成す
る不純物拡散層に接する円板部と、この円板部の上方に
同心状に形成される複数の筒部とからなる第1電極と、 この第1!極の外表面を覆う誘電体と、この誘電体のさ
らに外表面を覆う第2[極と、で構成していることに特
徴を有する。
In the semiconductor memory element of the present invention, the capacitor includes a disk portion provided on an insulating film covering a MOS transistor and partially in contact with an impurity diffusion layer forming a source or drain of the MOS transistor, and a disk portion of the disk portion. A first electrode consisting of a plurality of cylindrical portions formed concentrically above, and this first! It is characterized by being composed of a dielectric covering the outer surface of the pole and a second pole covering the further outer surface of the dielectric.

〔作用〕[Effect]

上記構成によると、キャパシタの第1電極を構成する筒
部を同心状に複数設けているから、その表面積が増大す
ることになり電荷蓄積容量が従来のものに比べて増える
ことになる。なお、筒部それぞれの内径を可能な限り小
さく管理すれば、従来からのキャパシタ占有面積内にお
いて複数の筒部の形成が可能となり、ひいてはメモリチ
ップの大容量化の妨げにならずに済む。
According to the above configuration, since a plurality of cylindrical portions constituting the first electrode of the capacitor are provided concentrically, the surface area thereof is increased and the charge storage capacity is increased compared to the conventional one. Note that by managing the inner diameter of each cylindrical portion to be as small as possible, it becomes possible to form a plurality of cylindrical portions within the area occupied by a conventional capacitor, and this does not hinder the increase in the capacity of the memory chip.

〔実施例〕〔Example〕

以下、本発明の一実施例を図面に基づいて詳細に説明す
る。
Hereinafter, one embodiment of the present invention will be described in detail based on the drawings.

第1図に本発明の一実施例を示している。同図において
従来例の第3図に示す部分と同一のものには同じ符号を
付しである。
FIG. 1 shows an embodiment of the present invention. In this figure, the same parts as those shown in FIG. 3 of the conventional example are given the same reference numerals.

本実施例の半導体記憶素子が、MO3I−ランジスタと
キャパシタで構成されていることは、従来例の第3図に
示すものと基本的に同しであり、また、MOSトランジ
スタの構造についても従来例と同し構造としている0本
実施例において従来例と異なる構成は、キャパシタの構
造である。
The semiconductor memory element of this example is basically the same as the conventional example shown in FIG. The structure of this embodiment, which has the same structure as that of the conventional example, differs from the conventional example in the structure of the capacitor.

以下、具体的に説明する。すなわち、キャパシタの第1
1i極20は、円板部23と、円板部23上において同
心状に設けられる二つの円筒部24a、24bとで構成
されており、この第1電極20の外表面に誘電体21お
よび第2を極22が被覆されている。そして、円板部2
3の外径寸法は従来例のものとほぼ同じ寸法形状に設定
されている。また、内側円筒部24aは、絶縁膜13の
コンタクトホール16より僅かに大きな内径寸法に設定
されていて、従来の円筒部24よりも小径になっている
。一方、外側円筒部24bは、円板部23の外周縁近傍
に設けられており、従来の円筒部24よりも若干大きな
内径寸法に設定されている。
This will be explained in detail below. That is, the first
The 1i pole 20 is composed of a disk portion 23 and two cylindrical portions 24a and 24b provided concentrically on the disk portion 23, and a dielectric 21 and a first electrode are provided on the outer surface of the first electrode 20. 2 is coated with a pole 22. And disk part 2
The outer diameter dimension of No. 3 is set to be approximately the same size and shape as that of the conventional example. Further, the inner cylindrical portion 24a is set to have an inner diameter slightly larger than the contact hole 16 of the insulating film 13, and has a smaller diameter than the conventional cylindrical portion 24. On the other hand, the outer cylindrical portion 24b is provided near the outer peripheral edge of the disk portion 23, and has an inner diameter slightly larger than that of the conventional cylindrical portion 24.

つまり、本実施例のキャパシタでは、円筒部24a、2
4bの数が二つであるため、従来のものよりも1を荷蓄
積容量が大容量となっている。しかし、キャパシタの第
11極20全体の大きさとしては従来のものとほとんど
変わらないよう各円筒部24a、24bの径寸法が管理
されている。
In other words, in the capacitor of this embodiment, the cylindrical portions 24a, 2
Since the number of 4b is two, the load storage capacity is larger than that of the conventional one. However, the diameter of each cylindrical portion 24a, 24b is controlled so that the overall size of the eleventh pole 20 of the capacitor is almost the same as that of the conventional one.

次に、上記構造の半導体記憶素子の製造方法の一例を第
2図を用いて説明する。
Next, an example of a method for manufacturing a semiconductor memory element having the above structure will be described with reference to FIG.

■ 周知の方法にてMOSトランジスタが形成された半
導体基板10上に、シリコン酸化膜からなる絶縁膜13
を積層し、絶縁膜13においてドレインを形成する不純
物拡散層12に対応する領域にコンタクトホール16を
形成する〔第2図(a)参照〕。
■ An insulating film 13 made of a silicon oxide film is placed on a semiconductor substrate 10 on which a MOS transistor is formed by a well-known method.
A contact hole 16 is formed in a region of the insulating film 13 corresponding to the impurity diffusion layer 12 forming the drain [see FIG. 2(a)].

■ この上面全面にCVD技術でもってリンなどのn型
不純物をドープしたポリシリコン膜を被覆し、このポリ
シリコン膜を異方性エツチングでパターニングすること
により、第11を極20の円板部23を得る〔第2図(
bl参照〕。
■ By coating the entire upper surface with a polysilicon film doped with n-type impurities such as phosphorus using CVD technology and patterning this polysilicon film by anisotropic etching, the 11th disk portion 20 of the pole 20 is [Figure 2 (
bl].

■ この上面全面に、所望の内側円筒部24aの高さ寸
法に対応した膜厚だけシリコン酸化膜1を積層する〔第
2図10+参照〕。
(2) A silicon oxide film 1 is laminated on the entire upper surface in a thickness corresponding to the desired height of the inner cylindrical portion 24a (see FIG. 2, 10+).

■ このシリコン酸化膜1をホトリソグラフィ技術でパ
ターニングすることにより、コンタクトホール16の大
きさに対応した円柱形状のシリコン酸化膜1を残す〔第
2図(di参照〕。
(2) By patterning this silicon oxide film 1 using photolithography, a cylindrical silicon oxide film 1 corresponding to the size of the contact hole 16 is left [see FIG. 2 (di)].

■ この上面全面に、CVD技術でもってリンなどのn
型不純物をドープしたポリシリコン膜2を被覆する〔第
2図(el参照〕。
■ The entire upper surface is coated with n such as phosphorus using CVD technology.
A polysilicon film 2 doped with type impurities is coated [see FIG. 2 (el)].

■ 異方性エツチングでポリシリコン膜2をパタニング
することにより、上記円柱形シリコン酸化膜1の外周面
を囲うポリシリコン膜2のみを残す〔第2図(fl参照
〕。この残したポリシリコン膜2が内側円筒部24aと
なる。
■ By patterning the polysilicon film 2 by anisotropic etching, only the polysilicon film 2 surrounding the outer peripheral surface of the above-mentioned cylindrical silicon oxide film 1 is left [see Fig. 2 (fl)].This remaining polysilicon film 2 is the inner cylindrical portion 24a.

■ この上面全面にシリコン酸化膜3を形成し、さらに
、その上面全面にSOG (スピンオングラス法)で酸
化膜成分を有する適当な溶剤を塗布してアニールするこ
とにより、所望の外側円筒部24bの高さ寸法に対応し
た膜厚の酸化膜4を形成する〔第2図(幻参照〕。
■ A silicon oxide film 3 is formed on the entire upper surface, and a suitable solvent containing an oxide film component is applied to the entire upper surface by SOG (spin-on glass method) and annealed to form the desired outer cylindrical portion 24b. An oxide film 4 having a thickness corresponding to the height dimension is formed [see FIG. 2 (illustration)].

■ この後、酸化膜4の上面からエッチバックすること
により、内側円筒部24aの上面を露出させる〔第2図
01参照〕。
(2) Thereafter, by etching back the top surface of the oxide film 4, the top surface of the inner cylindrical portion 24a is exposed (see FIG. 2).

■ シリコン酸化膜3および酸化膜4をホトリソグラフ
ィ技術でパターニングすることにより、内側円筒部24
aの周囲のシリコン酸化膜3および酸化膜4のみを円筒
形に残して、円板部23の外周縁部分と絶縁膜13の表
面とを露出させる〔第2図(1)参照〕。
■ By patterning the silicon oxide film 3 and the oxide film 4 using photolithography technology, the inner cylindrical part 24 is formed.
Only the silicon oxide film 3 and oxide film 4 around a are left in a cylindrical shape, and the outer peripheral edge portion of the disk portion 23 and the surface of the insulating film 13 are exposed [see FIG. 2 (1)].

[相] この上面全面に、上記■と同様、CVD技術で
もってリンなどのn型不純物をドープしたポリシリコン
l!5を被覆する〔第2図01参照〕。
[Phase] This entire upper surface is made of polysilicon l! doped with n-type impurities such as phosphorus using CVD technology, similar to the above (■). 5 [see Figure 2 01].

0 異方性エツチングでポリシリコン膜5をパタニング
することにより、上記■にて残した円筒形のシリコン酸
化膜3および酸化膜4の周囲のポリシリコン膜5のみを
円筒形に残す〔第2図(kl参照〕、この残したポリシ
リコン膜5が外側円筒部24bとなる。
0 By patterning the polysilicon film 5 by anisotropic etching, only the cylindrical silicon oxide film 3 and the polysilicon film 5 around the oxide film 4 left in step (3) are left in a cylindrical shape [Fig. (See kl) This remaining polysilicon film 5 becomes the outer cylindrical portion 24b.

■ 適当なウェットエツチングでもって内側円筒部24
a内の円柱形のポリシリコン膜1および内側円筒部24
aと外側円筒部24bとで囲まれる円筒形のシリコン酸
化膜3および酸化膜4を除去し、内側円筒部24aおよ
び外側円筒部24bを完全に露出させる〔第2図(1)
参照〕。
■ Inner cylindrical part 24 with appropriate wet etching
cylindrical polysilicon film 1 and inner cylindrical portion 24 in a
The cylindrical silicon oxide film 3 and the oxide film 4 surrounded by the inner cylindrical part 24a and the outer cylindrical part 24b are removed to completely expose the inner cylindrical part 24a and the outer cylindrical part 24b [FIG. 2 (1)]
reference〕.

■ この後、第1電極20を構成する内側円筒部24a
、外側円筒部24bおよび円板部23の外表面に熱酸化
膜からなる誘電体21およびリンなどのn型不純物をド
ープしたポリシリコン膜からなる第2を極22を被覆形
成することにより、第1図に示す構造となる。
■ After this, the inner cylindrical part 24a that constitutes the first electrode 20
By forming a dielectric 21 made of a thermal oxide film and a second electrode 22 made of a polysilicon film doped with an n-type impurity such as phosphorus on the outer surfaces of the outer cylindrical part 24b and the disk part 23, the second electrode 22 is formed. The structure is shown in Figure 1.

なお、上記実施例では、キャパシタを構成する第1電極
20に二つの円筒部24a、24bを備えた構造を例に
挙げているが、円筒部を二つ以上としたものも本発明に
含む。
In the above embodiments, the first electrode 20 constituting the capacitor is provided with two cylindrical portions 24a and 24b, but the present invention also includes structures having two or more cylindrical portions.

〔発明の効果〕〔Effect of the invention〕

以上のように、本発明の半導体記憶素子では、キャパシ
タの形状を工夫して表面積を従来のものよりも大きくす
ることにより、その電荷蓄積容量を従来に比べて増大し
たから、電荷リークが発生しても記憶しである情報が反
転するといった不都合の発生を防止することができて、
信転性の向上に貢献できる。
As described above, in the semiconductor memory element of the present invention, the shape of the capacitor is devised to make the surface area larger than that of the conventional one, thereby increasing the charge storage capacity compared to the conventional one, so that charge leakage does not occur. It is possible to prevent the occurrence of inconveniences such as the information being reversed when it is memorized.
It can contribute to improving credibility.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は本発明の一実施例にかかり、第1
図は半導体記憶素子の縦断面図、第2図(11〜ft+
は第1図の半導体記憶素子の製造工程を示す工程図であ
る。 第3図は従来例の半導体記憶素子を示す縦断面図である
。 11・・・不純物拡散層   12・・・不純物拡散層
13・・・絶縁膜      16・・・コンタクトホ
ール20・・・第1電極     21・・・誘電体2
2・・・第2′W1極    23・・・円板部24a
・・・内側円筒部   24b・・・外側円筒部第 4a / 図
FIG. 1 and FIG. 2 show one embodiment of the present invention;
The figure is a vertical cross-sectional view of a semiconductor memory element, and FIG.
2 is a process diagram showing the manufacturing process of the semiconductor memory element shown in FIG. 1. FIG. FIG. 3 is a longitudinal sectional view showing a conventional semiconductor memory element. 11... Impurity diffusion layer 12... Impurity diffusion layer 13... Insulating film 16... Contact hole 20... First electrode 21... Dielectric 2
2... 2nd'W1 pole 23... Disc part 24a
...Inner cylindrical part 24b...Outer cylindrical part 4a/Figure

Claims (1)

【特許請求の範囲】[Claims] (1)MOSトランジスタとキャパシタで構成される半
導体記憶素子であって、 前記キャパシタが、 MOSトランジスタを覆う絶縁膜上に設けられかつ一部
がMOSトランジスタのソースまたはドレインを形成す
る不純物拡散層に接する円板部と、この円板部の上方に
同心状に形成される複数の筒部とからなる第1電極と、 この第1電極の外表面を覆う誘電体と、 この誘電体のさらに外表面を覆う第2電極と、で構成さ
れていることを特徴とする半導体記憶素子。
(1) A semiconductor memory element composed of a MOS transistor and a capacitor, the capacitor being provided on an insulating film covering the MOS transistor and partially in contact with an impurity diffusion layer forming the source or drain of the MOS transistor. a first electrode consisting of a disk portion and a plurality of cylindrical portions formed concentrically above the disk portion; a dielectric covering an outer surface of the first electrode; and a further outer surface of the dielectric. a second electrode covering the semiconductor memory element.
JP2217625A 1990-08-18 1990-08-18 Semiconductor memory cell Pending JPH0499373A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2217625A JPH0499373A (en) 1990-08-18 1990-08-18 Semiconductor memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2217625A JPH0499373A (en) 1990-08-18 1990-08-18 Semiconductor memory cell

Publications (1)

Publication Number Publication Date
JPH0499373A true JPH0499373A (en) 1992-03-31

Family

ID=16707219

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2217625A Pending JPH0499373A (en) 1990-08-18 1990-08-18 Semiconductor memory cell

Country Status (1)

Country Link
JP (1) JPH0499373A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04215470A (en) * 1990-12-14 1992-08-06 Sharp Corp Manufacture of semiconductor memory
JPH04249363A (en) * 1991-01-30 1992-09-04 Samsung Electron Co Ltd High integrated semiconductor memory device and manufacture thereof
JPH06169068A (en) * 1992-11-30 1994-06-14 Nec Corp Semiconductor memory cell and its manufacture
JPH06326268A (en) * 1993-04-20 1994-11-25 Hyundai Electron Ind Co Ltd Capacitor of dram cell and preparation thereof
US5382816A (en) * 1992-07-03 1995-01-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having vertical transistor with tubular double-gate
US5389568A (en) * 1992-10-29 1995-02-14 Samsung Electronics Co., Ltd. Method of making a dynamic random access memory device
US5512768A (en) * 1994-03-18 1996-04-30 United Microelectronics Corporation Capacitor for use in DRAM cell using surface oxidized silicon nodules
US5939747A (en) * 1996-11-13 1999-08-17 Oki Electric Industry Co., Ltd. Capacitor produced in a semiconductor device
KR100362181B1 (en) * 1995-06-30 2003-03-03 주식회사 하이닉스반도체 A method for forming cylindrical storage node in semiconductor device
JP2006319315A (en) * 2005-04-14 2006-11-24 Elpida Memory Inc Capacitor and its manufacturing method

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04215470A (en) * 1990-12-14 1992-08-06 Sharp Corp Manufacture of semiconductor memory
JPH04249363A (en) * 1991-01-30 1992-09-04 Samsung Electron Co Ltd High integrated semiconductor memory device and manufacture thereof
US5382816A (en) * 1992-07-03 1995-01-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having vertical transistor with tubular double-gate
US5480838A (en) * 1992-07-03 1996-01-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device having vertical transistor with tubular double-gate
US5389568A (en) * 1992-10-29 1995-02-14 Samsung Electronics Co., Ltd. Method of making a dynamic random access memory device
JPH06169068A (en) * 1992-11-30 1994-06-14 Nec Corp Semiconductor memory cell and its manufacture
JPH06326268A (en) * 1993-04-20 1994-11-25 Hyundai Electron Ind Co Ltd Capacitor of dram cell and preparation thereof
US5512768A (en) * 1994-03-18 1996-04-30 United Microelectronics Corporation Capacitor for use in DRAM cell using surface oxidized silicon nodules
KR100362181B1 (en) * 1995-06-30 2003-03-03 주식회사 하이닉스반도체 A method for forming cylindrical storage node in semiconductor device
US5939747A (en) * 1996-11-13 1999-08-17 Oki Electric Industry Co., Ltd. Capacitor produced in a semiconductor device
JP2006319315A (en) * 2005-04-14 2006-11-24 Elpida Memory Inc Capacitor and its manufacturing method

Similar Documents

Publication Publication Date Title
JPH0430573A (en) Semiconductor memory device
JPS6235668A (en) Semiconductor memory device
JP3222944B2 (en) Method for manufacturing capacitor of DRAM cell
JPH0496363A (en) Semiconductor storage device
JPH0499373A (en) Semiconductor memory cell
JP2593524B2 (en) Method for manufacturing semiconductor device
JPS6155258B2 (en)
JPH0221653A (en) Semiconductor device and manufacture thereof
JPS6358958A (en) Semiconductor storage device
JPH01143350A (en) Semiconductor memory
JPH0328828B2 (en)
JPS61199657A (en) Semiconductor memory
JPS6156444A (en) Semiconductor device
JP3214615B2 (en) Semiconductor storage device
JPH0329186B2 (en)
JP3354333B2 (en) Semiconductor storage device
JPS6110271A (en) Semiconductor device
JPH01220856A (en) Semiconductor device
JPS627152A (en) Semiconductor memory
JP2827377B2 (en) Semiconductor integrated circuit
JPH04234165A (en) Semiconductor memory
JPS59112646A (en) Semiconductor memory device
JPH0499372A (en) Semiconductor device and manufacture thereof
JPH04393B2 (en)
JPS63278276A (en) Mos-type semiconductor device