KR100362181B1 - A method for forming cylindrical storage node in semiconductor device - Google Patents
A method for forming cylindrical storage node in semiconductor device Download PDFInfo
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- KR100362181B1 KR100362181B1 KR1019950019089A KR19950019089A KR100362181B1 KR 100362181 B1 KR100362181 B1 KR 100362181B1 KR 1019950019089 A KR1019950019089 A KR 1019950019089A KR 19950019089 A KR19950019089 A KR 19950019089A KR 100362181 B1 KR100362181 B1 KR 100362181B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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Abstract
Description
본 발명은 반도체 소자 제조 공정 중 전하저장전극 형성방법에 관한 것으로, 특히 실린더형 전하저장전극 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a charge storage electrode in a semiconductor device manufacturing process, and more particularly to a method for forming a cylindrical charge storage electrode.
잘 알려진 바와 같이 캐패시터의 정전용량(capacitance)은 캐패시터 유전막의 두께에 반비례하고, 전하저장전극의 표면적 및 캐패시터 유전막의 유전률에 비례하는데, 반도체 장치가 고집적화됨에 따라 캐패시터의 정전용량을 증가시키기 위하여 다양한 기술의 개발이 요구되고 있다.As is well known, the capacitance of a capacitor is inversely proportional to the thickness of the capacitor dielectric film and is proportional to the surface area of the charge storage electrode and the dielectric constant of the capacitor dielectric film. Various techniques are used to increase the capacitance of the capacitor as semiconductor devices become highly integrated. Development is required.
이와 같은 과제를 해결하고자 캐패시터의 전하저장전극을 단순 스택 구조와 같은 2차원 구조에서 실린더(cylinder) 구조, 지느러미(fin) 구조, 풀무(bellows) 구조 등의 다양한 3차원 구조의 전하저장 전극이 제시되어 전하저장 전극의 표면적을 확보하는 기술이 제시되는데, 그 중 실린더 구조의 전하저장 전극이 적용되고 있다.To solve this problem, charge storage electrodes of capacitors are presented in various three-dimensional structures, such as cylinder structure, fin structure, bellows structure, in two-dimensional structure such as simple stack structure. Therefore, a technique for securing the surface area of the charge storage electrode is proposed, and among them, a cylinder-type charge storage electrode is applied.
제 1A 도 내지 제 1F 도는 종래 기술에 따른 실린더형 전하저장 전극 형성 공정을 도시한 도면으로써, 이하 이를 참조하여 설명하기로 한다.1A to 1F illustrate a cylindrical charge storage electrode forming process according to the prior art, which will be described below with reference to the drawings.
종래에는 먼저, 제 1A 도에 도시된 바와 같이 소정의 하부공정이 완료된 실리콘 기판(1) 상부에 층간절연산화막(2)을 증착한 후 전하저장전극 콘택 마스크인 감광막 패턴(3)을 형성한다.Conventionally, first, as shown in FIG. 1A, an interlayer insulating oxide film 2 is deposited on a silicon substrate 1 on which a predetermined lower process is completed, and then a photoresist pattern 3, which is a charge storage electrode contact mask, is formed.
다음으로, 제 1B 도에 도시된 바와 같이 감광막 패턴(3)을 식각장벽으로 산화막(2)을 선택식각하여 콘택홀을 형성한 후 감광막 패턴(3)을 제거하고 스페이서용 산화막(4)을 증착한다.Next, as illustrated in FIG. 1B, the oxide film 2 is selectively etched using the photoresist pattern 3 as an etch barrier to form a contact hole, and then the photoresist pattern 3 is removed and the oxide film 4 for the spacer is deposited. do.
계속하여, 제 1C 도에 도시된 바와 같이 산화막(4)을 스페이서 식각하여 산화막 스페이서(4')를 형성한 후 전체 구조 표면을 따라 콘택홀이 완전히 매립되도록 제1폴리실리콘막(5)을 형성한다. 이어서, 제1폴리실리콘막(5) 상부에 희생산화막(6)을 형성한 후 전하저장 전극 마스크인 감광막 패턴(7)을 형성한다.Subsequently, as shown in FIG. 1C, the oxide film 4 is spacer-etched to form the oxide film spacer 4 ′, and then the first polysilicon film 5 is formed to completely fill the contact holes along the entire structure surface. do. Subsequently, after the sacrificial oxide film 6 is formed on the first polysilicon film 5, the photoresist pattern 7, which is a charge storage electrode mask, is formed.
다음으로, 제 1D 도에 도시된 바와 같이 제 1C 도에서 형성된 감광막패턴(7)을 식각 마스크로 하여 희생산화막(6) 및 제1폴리실리콘막(5)를 차례로 선택식각하여 패터닝한 후 전체구조 상부에 제2폴리실리콘막(8)를 증착한다.Next, as shown in FIG. 1D, the sacrificial oxide layer 6 and the first polysilicon layer 5 are sequentially etched and patterned using the photoresist pattern 7 formed in FIG. The second polysilicon film 8 is deposited on top.
다음으로, 제 1E 도에 도시된 바와 같이 제2폴리실리콘막(8)을 스페이서 식각하여 희생산화막(6) 패턴 측벽에 제2폴리실리콘막(8) 스페이서를 형성한다. 이때, 제2폴리실리콘막이 과도식각(over etch)되어 최종적인 전하저장전극의 높이 손실(height loss)을 가져오게 된다.Next, as shown in FIG. 1E, the second polysilicon film 8 is spacer-etched to form the second polysilicon film 8 spacer on the sidewalls of the sacrificial oxide film 6 pattern. At this time, the second polysilicon film is overetched to bring about a height loss of the final charge storage electrode.
마지막으로, 제 1F 도에 도시된 바와 같이 희생산화막(6)을 제거하여 제1폴리실리콘막(5) 및 제2폴리실리콘막(8) 스페이서로 이루어지는 실리더형 전하저장 전극 형성 공정을 완료한다.Finally, as shown in FIG. 1F, the sacrificial oxide film 6 is removed to complete the process of forming the cylinder type charge storage electrode including the spacers of the first polysilicon film 5 and the second polysilicon film 8. .
그러나, 상기와 같이 이루어지는 종래 기술에 따른 실린더형 전하저장전극 형성 방법은 전하저장전극의 실린더 높이에 따라 캐패시터의 정전 용량이 결정됨에 따라, 반도체 소자가 고집적화되면서 그만큼 실린더의 높이는 높아질수 밖에 없고, 그로 인하여 후속 공정의 어려움이 커지는 문제점이 대두되고 있다.However, in the method of forming the cylindrical charge storage electrode according to the related art, the capacitance of the capacitor is determined according to the height of the cylinder of the charge storage electrode, and as the semiconductor device becomes highly integrated, the height of the cylinder is inevitably increased. Due to this, a problem of increasing difficulty of subsequent processes is emerging.
본 발명은 실린더 내부에 돌출부를 형성하여 실린더의 표면적을 크게함으로써 캐패시터의 정전용량을 증대시킬 수 있는 실린더형 전하저장전극 형성 방법을 제공하는데 그 목적이 있다.It is an object of the present invention to provide a method of forming a cylindrical charge storage electrode that can increase the capacitance of a capacitor by forming a protrusion inside the cylinder to increase the surface area of the cylinder.
제 1A 도 내지 제 1F 도는 종래 기술에 따른 실린더형 전하저장 전극 형성 공정도.1A to 1F show a process for forming a cylindrical charge storage electrode according to the prior art.
제 2A 도 내지 제 2E 도는 본 발명의 일실시예에 따른 실린더형 전하저장전극 형성 공정도.2A through 2E are flow charts for forming a cylindrical charge storage electrode according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 실리콘 기판 22 : 층간절연산화막21 silicon substrate 22 interlayer dielectric oxide film
24' : 산화막 스페이서 25 : 제1폴리실리콘막24 ': oxide film spacer 25: first polysilicon film
27 : 제2폴리실리콘막 스페이서27: second polysilicon film spacer
상기 목적을 달성하기 위한 본 발명은, 소정의 하부공정이 완료된 실리콘 기판상에 층간절연막을 형성하는 제1 단계; 상기 층간절연막상에 전하저장전극 콘택마스크인 감광막 패턴을 형성하는 제2 단계; 상기 감광막 패턴을 경화시키기 위한 베이킹을 실시하는 제3 단계; 상기 제3 단계를 마친 상기 감광막 패턴의 측벽에 절연막 스페이서를 형성하는 동시에 상기 실리콘 기판이 노출되도록 상기 층간절연막을 선택식각하여 전하저장전극용 콘택홀을 형성하는 제4 단계; 상기 감광막 패턴을 제거하는 제5 단계; 상기 제5 단계가 완료된 결과물의 상부에 제1전도막 및 희생막을 차례로 적층 형성하는 제6 단계; 상기 희생막 및 상기 제1전도막을 단위 전하저장전극별로 패터닝하는 제7 단계; 패터닝된 상기 희생막 및 상기 제1전도막 측벽에 제2전도막 스페이서를 형성하는 제8 단계; 및 상기 희생막을 제거하는 제9 단계를 포함하여 이루어진다.The present invention for achieving the above object, the first step of forming an interlayer insulating film on the silicon substrate is a predetermined lower process is completed; Forming a photoresist pattern, which is a charge storage electrode contact mask, on the interlayer insulating film; Performing a baking step to cure the photosensitive film pattern; A fourth step of forming a contact hole for a charge storage electrode by selectively forming an insulating film spacer on the sidewall of the photoresist pattern after completing the third step and selectively etching the interlayer insulating film to expose the silicon substrate; A fifth step of removing the photoresist pattern; A sixth step of sequentially stacking a first conductive film and a sacrificial film on top of the finished product of the fifth step; A seventh step of patterning the sacrificial layer and the first conductive layer for each unit charge storage electrode; An eighth step of forming a second conductive film spacer on sidewalls of the patterned sacrificial film and the first conductive film; And a ninth step of removing the sacrificial layer.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
제 2A 도 내지 제 2E 도는 본 발명의 일실시예에 따른 반도체 소자의 실린더형 전하저장전극 형성 공정을 도시한 공정도이다.2A through 2E are process diagrams illustrating a process of forming a cylindrical charge storage electrode of a semiconductor device according to an embodiment of the present invention.
본 발명은 먼저, 제 2A 도에 도시된 바와 같이 소정의 하부공정이 완료된 실리콘 기판(21) 상부에 층간절연산화막(22)을 증착한 후 전하저장전극 콘택 마스크인 감광막 패턴(23)을 형성한다. 이어서, 감광막 패턴(23)을 식각장벽으로 하여 층간절연산화막(22)의 일부 두께를 선택식각한 후 320 ~ 350℃ 정도의 고온에서 베이킹을 실시하여 감광막 패턴(23)을 경화시킨다.First, as shown in FIG. 2A, an interlayer insulating oxide film 22 is deposited on a silicon substrate 21 on which a predetermined lower process is completed, and then a photoresist pattern 23 as a charge storage electrode contact mask is formed. . Subsequently, a portion of the interlayer dielectric oxide film 22 is selectively etched using the photoresist pattern 23 as an etch barrier, and then baking is performed at a high temperature of about 320 to 350 ° C. to cure the photoresist pattern 23.
다음으로, 제 2B 도에 도시된 바와 같이 전체 구조 표면을 따라플라즈마(Plasma) 화학기상증착(Chemical Vapor Deposition, CVD)법으로 스페이서용 산화막(24)을 형성한다. 이때, 증착온도는 감광막 패턴(23) 베이킹 시의 온도 보다 낮은 150 ∼ 175℃ 정도의 저온을 유지한다.Next, as shown in FIG. 2B, an oxide film 24 for spacers is formed by a plasma chemical vapor deposition (CVD) method along the entire structure surface. At this time, the deposition temperature is maintained at a low temperature of about 150 ~ 175 ℃ lower than the temperature at the time of baking the photosensitive film pattern (23).
다음으로, 제 2C 도에 도시된 바와 같이 스페이서용 산화막(24)을 비등방성 전면식각하여 경화된 감광막 패턴(23) 및 층간절연산화막(22)의 부분식각된 부위 측벽에 산화막 스페이서(24')를 형성하고 계속해서 층간절연산화막(22)를 식각하여 실리콘 기판(21)의 일부가 노출되도록 전하저장전극용 콘택홀을 형성한다. 이때, 전하저장전극용 콘택홀의 크기는 산화막 스페이서(24')에 의해 미세한 크기로 형성 가능하다.Next, as shown in FIG. 2C, the oxide spacer 24 ′ is formed on sidewalls of the photoresist pattern 23 and the partially etched portion 22 of the interlayer dielectric oxide layer 22, which are cured by anisotropically etching the spacer oxide film 24. Next, the interlayer dielectric oxide film 22 is etched to form a contact hole for the charge storage electrode so that a part of the silicon substrate 21 is exposed. In this case, the size of the contact hole for the charge storage electrode may be formed to a minute size by the oxide spacer 24 ′.
다음으로, 제 2D 도에 도시된 바와 같이 경화된 감광막 패턴(23)을 제거한 후 전하저장전극용 콘택홀이 매립되도록 전체구조 상부에 제1폴리실리콘막(25)을 형성한다. 이어서, 전체 구조 상부에 희생산화막(26)을 형성한 후 희생산화막(26) 및 제1폴리실리콘막(25)을 차례로 선택식각하여 전하저장전극 영역이 정의된 패턴을 형성한다.Next, after removing the cured photoresist pattern 23 as shown in FIG. 2D, the first polysilicon layer 25 is formed on the entire structure to fill the contact holes for the charge storage electrodes. Subsequently, after the sacrificial oxide layer 26 is formed on the entire structure, the sacrificial oxide layer 26 and the first polysilicon layer 25 are sequentially etched to form a pattern in which the charge storage electrode region is defined.
계속하여, 제 2E 도에 도시된 바와 같이 전체구조 상부에 제2폴리실리콘막을 증착한 후 비등방성 전면식각을 수행하여 전하저장전극 영역이 정의된 패턴 측벽에 제2폴리실리콘막 스페이서(27)를 형성한다. 이어서, 희생산화막(26)을 제거하여 실린더형 전하저장전극 형성공정을 완료한다.Subsequently, as shown in FIG. 2E, the second polysilicon film is deposited on the entire structure, and then anisotropic front etching is performed to form the second polysilicon film spacer 27 on the sidewall of the pattern where the charge storage electrode region is defined. Form. Subsequently, the sacrificial oxide film 26 is removed to complete the cylindrical charge storage electrode forming process.
이렇듯 본 발명은, 상기 종래 기술에 따른 실린더형 전하저장전극 내부에 산화막 스페이서를 이용한 돌출부를 형성하여 전하저장전극의 표면적을 증가시키게됨에 따라 캐패시터의 정전용량을 증가시킬 수 있다.As such, the present invention can increase the surface area of the charge storage electrode by forming a protrusion using an oxide spacer in the cylindrical charge storage electrode according to the prior art, thereby increasing the capacitance of the capacitor.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 전하저장전극의 표면적을 증가시키는 효과가 있고, 이에 따라 캐패시터의 정전용량을 증대시켜 반도체 소자의 신뢰성 및 고집적화를 향상시키는 효과가 있다.The present invention has the effect of increasing the surface area of the charge storage electrode, thereby increasing the capacitance of the capacitor has the effect of improving the reliability and high integration of the semiconductor device.
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KR1019950019089A KR100362181B1 (en) | 1995-06-30 | 1995-06-30 | A method for forming cylindrical storage node in semiconductor device |
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KR1019950019089A KR100362181B1 (en) | 1995-06-30 | 1995-06-30 | A method for forming cylindrical storage node in semiconductor device |
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JPH0311762A (en) * | 1989-06-09 | 1991-01-21 | Matsushita Electron Corp | Semiconductor memory device |
JPH0499373A (en) * | 1990-08-18 | 1992-03-31 | Mitsubishi Electric Corp | Semiconductor memory cell |
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JPH0311762A (en) * | 1989-06-09 | 1991-01-21 | Matsushita Electron Corp | Semiconductor memory device |
JPH0499373A (en) * | 1990-08-18 | 1992-03-31 | Mitsubishi Electric Corp | Semiconductor memory cell |
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