KR0148332B1 - Multi-layer storage electrode fabrication method of capacitor - Google Patents
Multi-layer storage electrode fabrication method of capacitorInfo
- Publication number
- KR0148332B1 KR0148332B1 KR1019950019358A KR19950019358A KR0148332B1 KR 0148332 B1 KR0148332 B1 KR 0148332B1 KR 1019950019358 A KR1019950019358 A KR 1019950019358A KR 19950019358 A KR19950019358 A KR 19950019358A KR 0148332 B1 KR0148332 B1 KR 0148332B1
- Authority
- KR
- South Korea
- Prior art keywords
- polysilicon
- storage electrode
- charge storage
- forming
- capacitor
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000003860 storage Methods 0.000 title claims abstract description 23
- 239000003990 capacitor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 239000010410 layer Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 12
- 239000011229 interlayer Substances 0.000 claims description 7
- 230000004888 barrier function Effects 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 6
- 239000012895 dilution Substances 0.000 claims description 5
- 238000010790 dilution Methods 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 229910000077 silane Inorganic materials 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술 분야1. TECHNICAL FIELD OF THE INVENTION
반도체 소자 제조 방법.Semiconductor device manufacturing method.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
종래의 스택형이나 핀형이나 실린더형의 캐패시터는 높은 캐패시턴스의 전하저장 전극을 형성하려 하였지만 공정이 길고 복잡하고 또한 공정을 실시하기 어려웠고 캐패시턴스의 증감을 조절하기 어렵다는 문제점이 있었다.Conventional stack type, pin type or cylindrical type capacitors have tried to form a high capacitance charge storage electrode, but the process was long, complicated, difficult to perform the process, and it was difficult to control the increase and decrease of the capacitance.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
다층구조의 폴리실리콘막을 형성시 여러번의 마스크 형성과 식각공정을 하나로 단순화시켜 간단한 공정으로 높은 캐패시턴스를 갖고, 캐패시턴스를 조절할 수 있는 캐패시터의 다층 전하저장 전극을 제조하고자 함.When forming a polysilicon film with a multi-layer structure, it is intended to manufacture a multi-layer charge storage electrode of a capacitor which has a high capacitance and a capacitance can be controlled by a simple process by simplifying a plurality of mask formation and etching processes into one.
4. 발명의 중요한 용도4. Important uses of the invention
캐패시터의 다층 전하저장 전극의 형성에 주로 이용됨.Mainly used for forming multi-layer charge storage electrodes of capacitors.
Description
제1a도 내지 1e도는 본 발명의 캐패시터의 다층 전하저장 전극 형성 방법에 따른 공정도.1a to 1e is a process chart according to the method for forming a multi-layer charge storage electrode of the capacitor of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 층간 절연막1 semiconductor substrate 2 interlayer insulating film
3 : 접합부(junction) 4 : 제1폴리실리콘3: junction 4: first polysilicon
5 : 제1희생산화막 6 : 제2폴리실리콘5: first rare production film 6: second polysilicon
7 : 제2희생산화막 8,10 : 포토레지스트 패턴7: second rare production film 8,10: photoresist pattern
9 : 제3폴리실리콘9: third polysilicon
본 발명은 일반적으로 반도체 소자 제조 방법에 관한 것으로서 특히 간단한 공정으로 전하저장 전극의 표면적을 넓혀 캐패시턴스(Capacitance)를 높인 캐패시터(Capacitor)의 다층전하저장 전극(Storage Electrode)를 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a storage electrode of a capacitor having a large capacitance by increasing the surface area of the charge storage electrode in a simple process.
반도체 소자가 고집적화됨에 따라 캐패시터가 차지할 수 있는 공간은 줄어들고 있다. 종래의 핀(Fin)형이나 실린더(Cylinder)형의 캐패시터는 높은 캐패시턴스의 전하저장 전극을 형성하려 하였지만 공정이 길고 복잡하고 또한 공정을 실시하기 어려웠다. 특히 종래의 핀(Fin)형 캐패시터는 유전층을 형성하기 전에 파티클(particle)을 제거하기 위해 메가소닉(megasonic)을 사용할 때 구조가 견고하지 못해 전극의 손상을 가져올 수 있고 또한 캐패시턴스의 증감을 조절하기 어렵다는 문제점이 있었다.As semiconductor devices are highly integrated, the space occupied by capacitors is decreasing. Conventional fin or cylinder type capacitors have attempted to form a high capacitance charge storage electrode, but the process is long, complex, and difficult to perform. In particular, conventional fin-type capacitors are not rigid when the megasonic is used to remove particles before the dielectric layer is formed, which can lead to electrode damage and to control the increase and decrease of capacitance. There was a difficult problem.
따라서, 전술한 바와 같은 문제점을 해걸하기 위해 안출된 본 발명은 다층 구조의 폴리실리콘막을 형성시 여러번의 마스크 형성과 식각공정을 하나로 단순화시켜 간단한 공정으로 높은 캐패시턴스를 갖고, 캐패시턴스의 증감을 조절할 수 있고 견고한 캐패시터의 다층 전하저장 전극을 형성하는 방법에 관한 것이다.Therefore, the present invention devised in order to solve the problems as described above has a high capacitance in a simple process, it is possible to control the increase and decrease of the capacitance by simplifying a number of mask formation and etching processes when forming a multi-layer polysilicon film in one A method of forming a multilayer charge storage electrode of a rigid capacitor.
본 발명에 따른 캐패시터의 다층 전하저장 전극 형성 방법은, 반도체 기판상에 층간 절연막이 형성되고 접합부 영역에 제1 콘택홀이 형성된 구조 상에 도핑된 제1폴리실리콘을 증착하는 단계와, 전하저장 전극의 모양 형성을 용이하게 하기위한 제1희생 산화막을 증착하는 단계와, 도핑되 제2폴리실리콘을 증착하는 단계와, 전하저장 전극의 모양 형성을 용이하게 하기 위한 제2희생 산화막을 증착하는 단계와, 상기 제1콘택홀 양쪽의 상기 층간 절연막 상부에 상기 제1 및 제2폴리실리콘을 연결하기 위한 제2콘택홀을 형성하기 위한 제1포토레지스트 패턴를 형성하는 단계와, 상기 제1포토레지스트를 식각배리어로 이용하여 상기 제2희생산화막, 상기 제2폴리실리콘 및 상기 제1희생 산화막을 식각하여 제2콘택홀을 형성하는 단계와, 잔류 포토레지스트를 제거하고 도핑된 제3폴리실리콘을 증착하는 단계와, 전하저장 전극을 정의하기 위한 제2포토레지스트 패턴을 형성하는 단계와, 상기 제2포토레지스트 패턴을 식각배리어로 이용하여 상기 제3폴리실리콘, 상기 제1희생 산화막, 상기 제2폴리실리콘, 상기 제2희생 산화막 및 상기 제1폴리실리콘을 식각하는 단계와, 상기 제2 및 제1희생 산화막의 일부 또는 전부를 습식식각하여 제거하는 단계를 포함하는 것을 특징으로 한다.A method of forming a multilayer charge storage electrode of a capacitor according to the present invention includes depositing a doped first polysilicon on a structure in which an interlayer insulating film is formed on a semiconductor substrate and a first contact hole is formed in a junction region; Depositing a first sacrificial oxide film for facilitating the shape of the substrate, depositing a doped second polysilicon, depositing a second sacrificial oxide film for facilitating the shape of the charge storage electrode; Forming a first photoresist pattern on the interlayer insulating layer on both sides of the first contact hole to form a second contact hole for connecting the first and second polysilicons; and etching the first photoresist. Forming a second contact hole by etching the second rare metallization film, the second polysilicon, and the first sacrificial oxide film using a barrier; Depositing the doped third polysilicon, forming a second photoresist pattern for defining a charge storage electrode, and using the second photoresist pattern as an etching barrier, the third polysilicon; Etching the first sacrificial oxide film, the second polysilicon, the second sacrificial oxide film, and the first polysilicon; and removing some or all of the second and first sacrificial oxide films by wet etching. Characterized in that.
이제 본 발명의 캐패시터의 다층 전하저장 전극 형성 방법의 실시예에 대하여 첨부도면을 참조하여 상세하게 살펴보게 된다. 먼저 한 실시예에 대하여 살펴보면, 제1a도에 도시된 바와 같이 반도체 기판(1)상에 층간 절연막이 형성되고 접합부(3) 영역에 콘택홀이 형성된 구조 상에 저압 화학기상증착(LP-CVD) 방식으로 약 580℃ 내지 630℃의 온도에서 실란(SiH4)가스를 사용하여 900Å 내지 1100Å의 도핑된 제1폴리실리콘(4)을 증착한다. 다음으로 제1b에 도시된 바와 같이 테트라-에틸-오소-실리케이트(TEOS ; Tetra-Ethyl-ortho-Silicate)와 산소(O2)의 혼합가스를 이용하여 저압 화학기상증착(LP-CVD) 방식으로 약 650℃ 내지 750℃ 의 온도에서 약900Å 내지 1100Å의 제1희생산화막(5)을 증착한다. 그리고 상기 제1폴리실리콘(4)을 증착한 방법과 같은 방법으로 도핑된 제2폴리실리콘(6)을 증착한다. 그리고 상기 제1희생산화막(5) 증착한 방법과 같은 방법으로 제2희생산화막(7)을 증착한다. 다음으로 제1c도에 도시된 바와 같이 상기 접합부(3)의 양쪽에 상기 층간 절연막 상에 콘택홀을 형성하기 위한 포토레지스트 패턴(8)을 형성한다. 그리고 상기 포토레지스트 패턴(8)을 식각베리어로 이용하여 상기 제2희생산화막, 상기 제2폴리실리콘 및 상기 제1희생산화막(5)을 식각한다. 다음으로 제1d도에 도시된 바와 같이 잔류 포토레지스트를 제거하고 도핑된 제3폴리실리콘(9)을 증착한다.그리고 캐패시터의 전하저장 전극을 정의하기 위한 포토레지스터(10) 패턴을 형성하고 상기 포토레지스트 패턴(10)을 식각배리어로 이용하여 상기 제3폴리실리콘, 상기 제2산화막, 상기 제2폴리실리콘, 상기 제1희생산화막 및 제1폴리실리콘을 식각한다. 마지막으로 제1e도에 도시된 바와 같이 산화막 부식액(BOE ; Buffered Oxide Echant)또는 불산(HF)을 사용하여 상기 제1 및 제2산화막을 제거한다. 다음으로 본 발명의 다른 실시예를 상세하게 살펴보면 전술한 바와 같은 공정을 수행시 제1, 제2 및 제2폴리실리콘을 약 1100Å 내지 1300Å로 두껍게 증착한다. 그리고 제1,제2 및 제3폴리실리콘을 층착하는 각 단계 후에 산소(O2)가스와 수소(H2)가스를 사용하여 약 600℃내지 900℃의 고온에서 급속산화 시키므로써 폴리실리콘의 그레인(grain) 경계선을 따라 산화제가 침투하게 한다. 다음으로 상기 급속산화 공정에서 생긴 산화막을 제거하여 그레인 표면 모양으로 인해 폴리실리콘층의 표면적을 넓힌다.이 때 급속산화되는 폴리실리콘의 두께는 약 100Å 내지 300Å이다.An embodiment of a method of forming a multilayer charge storage electrode of a capacitor of the present invention will now be described in detail with reference to the accompanying drawings. First, as shown in FIG. 1A, low-pressure chemical vapor deposition (LP-CVD) is formed on a structure in which an interlayer insulating film is formed on the semiconductor substrate 1 and a contact hole is formed in the junction region 3. And doped first polysilicon 4 of 900 kPa to 1100 kPa using a silane (SiH 4 ) gas at a temperature of about 580 ° C to 630 ° C. Next, as shown in FIG. 1B, the mixture was mixed with tetra-ethyl-ortho-silicate (TEOS) and oxygen (O 2) to low pressure chemical vapor deposition (LP-CVD). The first rare product film 5 of about 900 Pa to 1100 Pa is deposited at a temperature of 650 ° C to 750 ° C. Then, the doped second polysilicon 6 is deposited in the same manner as the first polysilicon 4 is deposited. The second dilution film 7 is deposited in the same manner as the first dilution film 5 is deposited. Next, as shown in FIG. 1C, photoresist patterns 8 for forming contact holes on the interlayer insulating film are formed on both sides of the junction 3. The second rare production film, the second polysilicon, and the first rare production film 5 are etched using the photoresist pattern 8 as an etching barrier. Next, as shown in FIG. 1d, the residual photoresist is removed and the doped third polysilicon 9 is deposited. A photoresist 10 pattern is formed to define the charge storage electrode of the capacitor and the photoresist is formed. The third polysilicon, the second oxide film, the second polysilicon, the first dilution film and the first polysilicon are etched using the resist pattern 10 as an etching barrier. Finally, as shown in FIG. 1e, the first and second oxide layers are removed using an oxide corrosion solution (BOE; Buffered Oxide Echant) or hydrofluoric acid (HF). Next, when another embodiment of the present invention is described in detail, the first, second and second polysilicon are deposited to a thickness of about 1100 kW to 1300 kW when the process as described above is performed. After each step of depositing the first, second and third polysilicon, oxygen (O 2 ) gas and hydrogen (H 2 ) gas were rapidly oxidized at a temperature of about 600 ° C. to 900 ° C. It allows the oxidant to penetrate along the grain boundaries. Next, the oxide film generated in the rapid oxidation process is removed to increase the surface area of the polysilicon layer due to the grain surface shape. At this time, the thickness of the polysilicon rapidly oxidized is about 100 kPa to 300 kPa.
반도체 소자 제조시, 전술한 바와 같은 본 발명에 따라 다층 폴리실리콘 전하저장 전극을 형성하므로서 구조적으로 견고하면서도 공정이 간단하고 표면적을 크게 증대시킬 수 있다. 그리고 희생산화막의 제거하는 정도에 따라 전하저장 전극의 캐패시턴스의 증감을 조절할 수 있다.When manufacturing a semiconductor device, according to the present invention as described above, by forming a multi-layer polysilicon charge storage electrode, it is structurally robust, the process is simple and the surface area can be greatly increased. The capacitance of the charge storage electrode can be increased or decreased according to the degree of removal of the sacrificial oxide film.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| KR1019950019358A KR0148332B1 (en) | 1995-06-30 | 1995-06-30 | Multi-layer storage electrode fabrication method of capacitor |
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| KR1019950019358A KR0148332B1 (en) | 1995-06-30 | 1995-06-30 | Multi-layer storage electrode fabrication method of capacitor |
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| KR970004005A KR970004005A (en) | 1997-01-29 |
| KR0148332B1 true KR0148332B1 (en) | 1998-10-15 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100630667B1 (en) * | 2000-08-25 | 2006-10-02 | 삼성전자주식회사 | Method of manufacturing capacitor for semiconductor device |
-
1995
- 1995-06-30 KR KR1019950019358A patent/KR0148332B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100630667B1 (en) * | 2000-08-25 | 2006-10-02 | 삼성전자주식회사 | Method of manufacturing capacitor for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970004005A (en) | 1997-01-29 |
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