JPH04215470A - Manufacture of semiconductor memory - Google Patents
Manufacture of semiconductor memoryInfo
- Publication number
- JPH04215470A JPH04215470A JP2402443A JP40244390A JPH04215470A JP H04215470 A JPH04215470 A JP H04215470A JP 2402443 A JP2402443 A JP 2402443A JP 40244390 A JP40244390 A JP 40244390A JP H04215470 A JPH04215470 A JP H04215470A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- capacitor
- polycrystalline silicon
- silicon film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 56
- 230000002093 peripheral effect Effects 0.000 claims abstract description 44
- 239000003990 capacitor Substances 0.000 claims abstract description 41
- 239000012535 impurity Substances 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract 2
- 229910052710 silicon Inorganic materials 0.000 claims abstract 2
- 239000010703 silicon Substances 0.000 claims abstract 2
- 239000010408 film Substances 0.000 claims description 92
- 238000000034 method Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 15
- 239000003518 caustics Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 claims description 2
- 238000003860 storage Methods 0.000 abstract description 24
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000006731 degradation reaction Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 26
- 229910052681 coesite Inorganic materials 0.000 description 13
- 229910052906 cristobalite Inorganic materials 0.000 description 13
- 239000000377 silicon dioxide Substances 0.000 description 13
- 235000012239 silicon dioxide Nutrition 0.000 description 13
- 229910052682 stishovite Inorganic materials 0.000 description 13
- 229910052905 tridymite Inorganic materials 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910019213 POCl3 Inorganic materials 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000007790 solid phase Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】この発明は、半導体メモリ素子の
製造方法に関し、より詳しくは、スタック型ＤＲＡＭ（
ダイナミック・ランダム・アクセス・メモリ）の製造方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more specifically, to a method for manufacturing a semiconductor memory device, and more particularly, to a method for manufacturing a semiconductor memory device.
Dynamic random access memory).
【０００２】0002
【従来の技術】高集積化の先端を走るＤＲＡＭは、３年
毎に４倍の割合で記憶容量が増大しており、今後、１６
Ｍｂ，６４Ｍｂ，２５６Ｍｂと順次増加していくと予想
される。このような集積度の向上を図る上で、ＤＲＡＭ
の記憶単位であるメモリセルを縮小して行く必要がある
。メモリセルを縮小する際、放射線によるソフトエラー
を防止すると共に十分なＳ／Ｎ比を確保するためには、
メモリセル内の電荷蓄積容量はある最低値以上を保たね
ばならない。このため、キャパシタをＭＯＳトランジス
タ上に形成して、面積利用効率を上げたいわゆるスタッ
ク型メモリセルが有望となっている。[Prior Art] The storage capacity of DRAM, which is at the forefront of highly integrated technology, is increasing at a rate of four times every three years.
It is expected that the number will increase sequentially to Mb, 64 Mb, and 256 Mb. In order to improve the degree of integration, DRAM
It is necessary to reduce the size of the memory cell, which is the unit of storage. When downsizing memory cells, in order to prevent soft errors caused by radiation and ensure a sufficient S/N ratio,
The charge storage capacity within a memory cell must be maintained above a certain minimum value. For this reason, a so-called stacked memory cell in which a capacitor is formed on a MOS transistor to improve area utilization efficiency has become promising.
【０００３】しかしながら、このスタック型メモリセル
はセル面積の縮小に伴ってキャパシタ面積が減少するた
め、蓄積電荷容量が急激に減少するという問題がある。
この問題を解決するために、本出願人は先に、限られた
セル面積でもって蓄積電荷容量を増大できる半導体メモ
リ素子を提案した（特願平１−１５８０２８号）。この
半導体メモリ素子は、図７に示すように、半導体基板１
１の表面に形成されたトランジスタＴ上に、このトラン
ジスタＴのソース領域１５に一方の電極（蓄積電極）１
０がつながるキャパシタＣを積層してメモリセルが構成
されている。上記キャパシタＣの蓄積電極１０は、柱状
（カップ状でも良い）をなす主部６と、この主部６の側
壁６ａの外周近傍を離間してリング状に取り巻く外周部
７と、上記主部６の端部と外周部７の端部とを一体に連
結する底部８とからなっている。上記主部６は多結晶シ
リコン膜からなり、底部８はこの多結晶シリコン膜を一
部残してエッチングして形成されている。一方、外周部
７は主部６の膜厚と比較して薄い多結晶シリコン膜から
なっている。上記キャパシタＣの他方の電極（上部電極
）２５は、絶縁膜２４を挟んで上記電極１０の主部６，
外周部７および底部８に各々対向する部分からなってい
る。なお、１２は選択酸化法で形成したＳｉＯ２からな
る素子分離領域、１３は熱酸化法で形成したＳｉＯ２か
らなるゲート絶縁膜、１４は燐（Ｐ）ドープ多結晶Ｓｉ
からなるゲート電極（ワード線）、１５，１６はそれぞ
れ砒素（Ａｓ）イオン注入によって形成したＮ（＋）型
のソース領域，ドレイン領域、１５ａ，１６ａは燐イオ
ン注入によって形成したＬＤＤ（ライトリ・ドープト・
ドレイン）構造をなすＮ−領域、１７と１８はそれぞれ
キャパシタ下の層間絶縁膜であるＳｉＯ２膜とＳｉ３Ｎ
４膜、１９と２７はコンタクトホール、２６はビット線
下の層間絶縁膜、２８はトランジスタＴのドレイン領域
１６につながるビット線を示している。この半導体メモ
リ素子は、限られたセル面積でもってキャパシタＣの下
部電極１０と上部電極２０との対向面積を増大させて大
容量化することができ、したがって、１６Ｍｂあるいは
それ以上に高集積化する場合にも、必要とされる最低値
以上の電荷蓄積容量を確保することができる。However, this stacked memory cell has a problem in that the capacitor area decreases as the cell area decreases, so that the storage charge capacity rapidly decreases. In order to solve this problem, the present applicant previously proposed a semiconductor memory device that can increase the storage charge capacity with a limited cell area (Japanese Patent Application No. 1-158028). This semiconductor memory element has a semiconductor substrate 1 as shown in FIG.
On the transistor T formed on the surface of the transistor T, one electrode (storage electrode) 1 is placed in the source region 15 of the transistor T.
A memory cell is constructed by stacking capacitors C connected to each other. The storage electrode 10 of the capacitor C includes a main part 6 having a columnar shape (or a cup shape), an outer peripheral part 7 surrounding the outer periphery of the side wall 6a of the main part 6 in a ring shape, and a peripheral part 7 surrounding the main part 6 in a ring shape. It consists of a bottom part 8 that integrally connects the end part of the outer peripheral part 7 with the end part of the outer peripheral part 7. The main portion 6 is made of a polycrystalline silicon film, and the bottom portion 8 is formed by etching a portion of the polycrystalline silicon film. On the other hand, the outer peripheral portion 7 is made of a polycrystalline silicon film that is thinner than the main portion 6 . The other electrode (upper electrode) 25 of the capacitor C is connected to the main portion 6 of the electrode 10 with an insulating film 24 in between.
It consists of parts facing the outer peripheral part 7 and the bottom part 8, respectively. Note that 12 is an element isolation region made of SiO2 formed by selective oxidation, 13 is a gate insulating film made of SiO2 formed by thermal oxidation, and 14 is a phosphorus (P)-doped polycrystalline Si.
15 and 16 are N(+) type source and drain regions respectively formed by arsenic (As) ion implantation, and 15a and 16a are LDD (lightly doped) gate electrodes formed by phosphorus ion implantation.・
17 and 18 are the SiO2 film and Si3N interlayer insulating film under the capacitor, respectively.
4, 19 and 27 are contact holes, 26 is an interlayer insulating film below the bit line, and 28 is a bit line connected to the drain region 16 of the transistor T. This semiconductor memory element can have a large capacity by increasing the opposing area between the lower electrode 10 and the upper electrode 20 of the capacitor C with a limited cell area, and can therefore be highly integrated to 16 Mb or more. In this case, it is possible to ensure a charge storage capacity greater than the required minimum value.
【０００４】上記キャパシタＣの蓄積電極１０を形成す
る場合、材料として用いる多結晶Ｓｉに不純物をドープ
して導電率を高める必要がある。そこで、これまでは、
蓄積電極１０を構成する上記主部６，外周部７および底
部８を全て形成した後に不純物拡散を行っていた。その
際、相当量の不純物を拡散して、蓄積電極１０全体の導
電性を確保していた。[0004] When forming the storage electrode 10 of the capacitor C, it is necessary to dope impurities into the polycrystalline Si used as the material to increase the conductivity. Therefore, until now,
After the main portion 6, outer peripheral portion 7, and bottom portion 8 constituting the storage electrode 10 were all formed, impurity diffusion was performed. At that time, a considerable amount of impurities was diffused to ensure the conductivity of the entire storage electrode 10.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、蓄積電
極１０全体の導電性を確保するために必要な量の不純物
拡散を行うと、上記主部６の膜厚と比較して上記外周部
７は膜厚が薄い（０．１μｍ程度）ため、主部６が導電
性を確保できたときには、外周部７の体積不純物濃度が
必要以上に多く成り過ぎてしまう。この結果、外周部７
は、高濃度になった粒界の移動により表面が突起の急峻
な形状になる。このため、この上に成膜するキャパシタ
用絶縁膜２４の電気的特性に悪影響を及ぼし、リーク電
流や絶縁破壊寿命等を劣化させるという問題がある。[Problems to be Solved by the Invention] However, when the impurity is diffused in the amount necessary to ensure the conductivity of the entire storage electrode 10, the outer peripheral portion 7 becomes thinner than the thickness of the main portion 6. Since the thickness is thin (approximately 0.1 μm), even when the main portion 6 can ensure conductivity, the volumetric impurity concentration of the outer peripheral portion 7 becomes excessively large than necessary. As a result, the outer peripheral portion 7
In this case, the surface becomes steeply protruded due to movement of highly concentrated grain boundaries. Therefore, there is a problem that the electrical characteristics of the capacitor insulating film 24 formed thereon are adversely affected, and leakage current and dielectric breakdown life are deteriorated.
【０００６】そこで、この発明の目的は、柱状またはカ
ップ状をなす主部と、この主部側壁の外周近傍を離間し
て取り巻く外周部と、上記主部の端部と外周部の端部と
を一体に連結する底部とからなる蓄積電極全体の導電性
を確保しつつ、上記外周部の体積不純物濃度が必要以上
に高くならないようにでき、したがってキャパシタ用絶
縁膜の電気的特性の劣化を抑制することができる半導体
メモリ素子の製造方法を提供することにある。[0006] Accordingly, an object of the present invention is to provide a main part having a columnar or cup shape, an outer peripheral part that surrounds the outer peripheral part of the side wall of the main part at a distance, and an end of the main part and an end of the outer peripheral part. While ensuring the electrical conductivity of the entire storage electrode consisting of the bottom part that connects the capacitors together, it is possible to prevent the volumetric impurity concentration in the outer peripheral part from becoming higher than necessary, thus suppressing the deterioration of the electrical characteristics of the capacitor insulating film. An object of the present invention is to provide a method for manufacturing a semiconductor memory device that can perform the following steps.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、この発明の半導体メモリ素子の製造方法は、半導体
基板表面に形成されたトランジスタと上記トランジスタ
の端子に一方の電極がつながるキャパシタとからなるメ
モリセルを複数個有し、上記キャパシタの上記一方の電
極が、柱状またはカップ状をなす主部と、この主部の側
壁の外周近傍を離間して取り巻く外周部と、上記主部の
端部と外周部の端部とを一体に連結する底部とからなり
、上記キャパシタの他方の電極が絶縁膜を挟んで上記一
方の電極の各部に対向する半導体メモリ素子の製造方法
であって、上記半導体基板表面に上記トランジスタを形
成した後、上記キャパシタの一方の電極材料として上記
基板上に第１の多結晶シリコン膜を形成する工程と、上
記第１の多結晶シリコン膜に所定濃度の不純物をドープ
して導電率を高める工程と、上記一方の電極の主部を形
成すべき領域の周囲の上記第１の多結晶シリコン膜を薄
膜の部分を残して除去して、上記主部の側壁を形成する
工程と、多結晶シリコンに対して選択的にエッチング可
能な材料からなり、上記主部側壁の外周を密着して取り
巻く外周側壁を形成する工程と、上記第１の多結晶シリ
コン膜よりも膜厚が薄い第２の多結晶シリコン膜を上記
半導体基板上に堆積する工程と、上記第２の多結晶シリ
コン膜に所定濃度の不純物をドープして導電率を高める
工程と、この第２の多結晶シリコン膜を反応性イオンエ
ッチング法により加工して、上記外周側壁を密着して取
り巻くと共に端部が上記第１の多結晶シリコン膜の上記
薄膜の部分に連結する外周部を形成する工程と、上記外
周部の周囲の上記薄膜の部分を除去して底部を形成する
工程と、上記外周側壁を腐食剤によって除去する工程と
を有し、この一方の電極の上にキャパシタ用の絶縁膜お
よび他方の電極を順次形成するようにしたことを特徴と
している。[Means for Solving the Problems] In order to achieve the above object, the method for manufacturing a semiconductor memory element of the present invention includes a transistor formed on the surface of a semiconductor substrate and a capacitor whose one electrode is connected to a terminal of the transistor. The capacitor has a plurality of memory cells, and the one electrode of the capacitor has a columnar or cup-shaped main part, an outer circumferential part that surrounds the outer circumference of the side wall of the main part at a distance, and an end of the main part. A method for manufacturing a semiconductor memory element, wherein the other electrode of the capacitor faces each part of the one electrode with an insulating film interposed therebetween, After forming the transistor on the surface of the semiconductor substrate, forming a first polycrystalline silicon film on the substrate as a material for one electrode of the capacitor, and doping impurities at a predetermined concentration in the first polycrystalline silicon film. doping to increase conductivity, and removing the first polycrystalline silicon film around the area where the main part of the one electrode is to be formed, leaving only a thin film part, to form the sidewall of the main part. a step of forming an outer peripheral side wall that is made of a material that can be selectively etched with respect to polycrystalline silicon and tightly surrounds the outer periphery of the main portion side wall; a step of depositing a second polycrystalline silicon film with a thin film thickness on the semiconductor substrate; a step of doping the second polycrystalline silicon film with impurities at a predetermined concentration to increase the conductivity; processing the polycrystalline silicon film by a reactive ion etching method to form an outer peripheral portion closely surrounding the outer peripheral side wall and having an end connected to the thin film portion of the first polycrystalline silicon film; , a step of removing a portion of the thin film around the outer periphery to form a bottom portion, and a step of removing the outer periphery side wall with a corrosive agent, and an insulating film for a capacitor and an insulating film for a capacitor on one of the electrodes. It is characterized in that the other electrode is formed sequentially.
【０００８】[0008]
【作用】この発明の半導体メモリ素子の製造方法は、キ
ャパシタの一方の電極（蓄積電極）を構成する主部（お
よび底部）と外周部とをそれぞれ別々に不純物を拡散し
ている。したがって、上記主部と外周部とが最適の体積
不純物濃度になるようにそれぞれの膜厚に応じて不純物
の拡散量を変えることができる。このようにした場合、
上記外周部の体積不純物濃度が必要以上に高くなること
はない。したがって、高濃度粒界の移動によって上記外
周部の形状が損なわれる現象は回避される。したがって
、この上に成膜されるキャパシタ用絶縁膜の電気的特性
が劣化しなくなる。In the method of manufacturing a semiconductor memory element of the present invention, impurities are separately diffused into the main part (and bottom part) and the outer peripheral part of one electrode (storage electrode) of the capacitor. Therefore, the amount of diffusion of impurities can be changed depending on the thickness of each film so that the main portion and the outer peripheral portion have an optimum volumetric impurity concentration. If you do this,
The volumetric impurity concentration in the outer periphery does not become higher than necessary. Therefore, the phenomenon in which the shape of the outer peripheral portion is damaged due to movement of the high concentration grain boundary is avoided. Therefore, the electrical characteristics of the capacitor insulating film formed thereon will not deteriorate.
【０００９】[0009]
【実施例】以下、この発明の半導体メモリ素子の製造方
法を実施例により詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The method for manufacturing a semiconductor memory device according to the present invention will be explained in detail below using examples.
【００１０】図１乃至図６は一実施例の半導体メモリ素
子の製造方法を工程順に示している。なお、図７に示し
た半導体メモリ素子と同一形状のものを作製するが、メ
モリセルを構成するトランジスタＴや素子分離領域１２
等は簡単化するため図示していない。FIGS. 1 to 6 show a method of manufacturing a semiconductor memory device according to an embodiment in the order of steps. Note that although a semiconductor memory element having the same shape as the semiconductor memory element shown in FIG.
etc. are not shown for simplicity.
【００１１】■まず、図１に示すように、Ｐ型Ｓｉ基板
１１上に上記トランジスタＴを形成した後、キャパシタ
下の層間絶縁膜としてＳｉＯ２膜１７とＳｉ３Ｎ４膜１
８とをＣＶＤ（化学気相成長）法により順次堆積する。
このＳｉＯ２膜１７，Ｓｉ３Ｎ４膜１８にコンタクトホ
ール１９を開口した後、メモリセルを構成するキャパシ
タＣの蓄積電極１０の材料として第１の多結晶Ｓｉ膜２
０を全面に堆積する。そして、ＰＯＣｌ３を拡散源とし
た固相熱拡散法により、上記多結晶Ｓｉ膜２０に不純物
として所定濃度の燐をドープする。■First, as shown in FIG. 1, after forming the transistor T on a P-type Si substrate 11, a SiO2 film 17 and a Si3N4 film 1 are formed as an interlayer insulating film under the capacitor.
8 and 8 are sequentially deposited by CVD (chemical vapor deposition). After opening contact holes 19 in the SiO2 film 17 and Si3N4 film 18, a first polycrystalline Si film 2 is formed as a material for the storage electrode 10 of the capacitor C constituting the memory cell.
Deposit 0 on the entire surface. Then, the polycrystalline Si film 20 is doped with phosphorus at a predetermined concentration as an impurity by a solid phase thermal diffusion method using POCl3 as a diffusion source.
【００１２】■次に、図２に示すように、ＳｉＯ２膜２
１を全面に堆積する。リソグラフィ手法によってＳｉＯ
２膜２１上にレジストを設け、このレジストをマスクと
して、反応性イオンエッチング法によって、上記ＳｉＯ
２膜２１を矩形の電極形状に加工する。上記レジストを
除去した後、上記加工後のＳｉＯ２膜２１をマスクとし
て、上記多結晶Ｓｉ膜２０を薄膜の部分２０ｂを残して
エッチングして除去する。この第１の多結晶Ｓｉ膜２０
のうち厚膜の部分（まったくエッチングしなかった部分
）は、図７に示した蓄積電極１０の主部６に相当してい
る。■Next, as shown in FIG.
1 is deposited on the entire surface. SiO by lithographic techniques
A resist is provided on the 2 film 21, and using this resist as a mask, the SiO2 film is etched by reactive ion etching.
The two films 21 are processed into a rectangular electrode shape. After removing the resist, using the processed SiO2 film 21 as a mask, the polycrystalline Si film 20 is etched away leaving the thin film portion 20b. This first polycrystalline Si film 20
The thick film portion (the portion that was not etched at all) corresponds to the main portion 6 of the storage electrode 10 shown in FIG.
【００１３】■次に、減圧気相成長（ＬＰＣＶＤ）法に
よってＳｉＯ２膜を全面に堆積して、工程■で形成した
多結晶Ｓｉ膜２０の側壁２０ａ（断差部）の周囲の上記
ＳｉＯ２膜を反応性イオンエッチング法によって除去す
る。このようにして、図３に示すように、上記多結晶Ｓ
ｉ膜２０の側壁２０ａに上記ＳｉＯ２膜からなる外周側
壁２２を形成する。なお、外周側壁２２の材料としてＳ
ｉＯ２膜を用いているが、多結晶Ｓｉに対して選択的に
エッチング可能であれば他の材料を用いても良い。[0013] Next, a SiO2 film is deposited on the entire surface by a low pressure chemical vapor deposition (LPCVD) method, and the SiO2 film around the side wall 20a (offset part) of the polycrystalline Si film 20 formed in step (2) is removed. Removed by reactive ion etching. In this way, as shown in FIG.
On the side wall 20a of the i film 20, an outer peripheral side wall 22 made of the SiO2 film is formed. In addition, as the material of the outer peripheral side wall 22, S
Although an iO2 film is used, other materials may be used as long as they can be selectively etched with respect to polycrystalline Si.
【００１４】■次に、図４に示すように、上記多結晶Ｓ
ｉ膜２０よりも膜厚が薄い第２の多結晶Ｓｉ膜２３を全
面に堆積する。そして、ＰＯＣｌ３を拡散源とした固相
熱拡散法により、上記多結晶Ｓｉ膜に不純物として燐を
ドープする。ここで、ドープする燐の濃度は、この多結
晶Ｓｉ膜２３の抵抗率が上記工程■で不純物拡散した多
結晶Ｓｉ２０の膜とほぼ同じになるように設定する。す
なわち、多結晶Ｓｉ膜２３が多結晶Ｓｉ膜２０に比べて
膜厚が薄い分だけ、工程■の燐ドープよりも不純物の拡
散量を少なくする。■Next, as shown in FIG. 4, the polycrystalline S
A second polycrystalline Si film 23, which is thinner than the i-film 20, is deposited over the entire surface. Then, the polycrystalline Si film is doped with phosphorus as an impurity by a solid phase thermal diffusion method using POCl3 as a diffusion source. Here, the concentration of phosphorus to be doped is set so that the resistivity of this polycrystalline Si film 23 is approximately the same as that of the polycrystalline Si film 20 into which impurities were diffused in step (2) above. That is, since the polycrystalline Si film 23 is thinner than the polycrystalline Si film 20, the amount of impurity diffusion is made smaller than in the phosphorus doping in step (2).
【００１５】■次に、反応性イオンエッチング法によっ
て、上記多結晶Ｓｉ膜２３と上記多結晶Ｓｉ膜２０のう
ち残存した薄膜の部分２０ｂとを上記断差部を除いて完
全にエッチングして除去する。このようにして、図５に
示すように、多結晶Ｓｉからなり、上記外周側壁２２を
密接して取り巻くと共に下部が上記薄膜の部分２０ｂに
連結するリング状多結晶Ｓｉ膜２３ａを形成する。この
多結晶Ｓｉ膜２３ａは、図７に示した蓄積電極１０の外
周部７に相当している。同時に、この多結晶Ｓｉ膜２３
の外側の領域の上記薄膜の部分２０ｂを除去することに
よって、上記蓄積電極１０の底部８をも形成する。[0015] Next, by reactive ion etching, the polycrystalline Si film 23 and the remaining thin film portion 20b of the polycrystalline Si film 20 are completely etched and removed except for the difference portion. do. In this way, as shown in FIG. 5, a ring-shaped polycrystalline Si film 23a made of polycrystalline Si closely surrounds the outer peripheral side wall 22 and whose lower part is connected to the thin film portion 20b. This polycrystalline Si film 23a corresponds to the outer peripheral portion 7 of the storage electrode 10 shown in FIG. At the same time, this polycrystalline Si film 23
The bottom part 8 of the storage electrode 10 is also formed by removing the portion 20b of the thin film in the outer region.
【００１６】■次に、弗化水素酸を含有するエッチング
液を用いて、上記外周側壁２２およびＳｉＯ２膜２１を
除去する。その後、図６に示すように、キャパシタ絶縁
膜２４を形成し、キャパシタＣの他方の電極として、上
記蓄積電極１０の各部に対向し、複数のメモリセルの共
通配線となるプレート電極２５を形成する。キャパシタ
絶縁膜２４は、ＬＰＣＶＤ（減圧化学気相成長法）によ
りＳｉ３Ｎ４膜を成長した後、熱酸化法によりこのＳｉ
３Ｎ４膜表面を酸化して形成する。すなわち、ＳｉＯ２
／Ｓｉ３Ｎ４二層膜とする。また、プレート電極２５は
、燐ドープ多結晶Ｓｉを材料として形成する。(2) Next, the outer peripheral side wall 22 and the SiO2 film 21 are removed using an etching solution containing hydrofluoric acid. Thereafter, as shown in FIG. 6, a capacitor insulating film 24 is formed, and a plate electrode 25 is formed as the other electrode of the capacitor C, facing each part of the storage electrode 10 and serving as a common wiring for a plurality of memory cells. . The capacitor insulating film 24 is formed by growing a Si3N4 film by LPCVD (low pressure chemical vapor deposition), and then growing this Si by thermal oxidation.
It is formed by oxidizing the surface of the 3N4 film. That is, SiO2
/Si3N4 double layer film. Further, the plate electrode 25 is formed of phosphorus-doped polycrystalline Si.
【００１７】このように、この製造方法は、この蓄積電
極１０を構成する多結晶Ｓｉ膜２０，２３の膜厚に応じ
てそれぞれ不純物拡散を最適の拡散量で行っているので
、蓄積電極１０の導電性を確保しつつ高濃度粒界の移動
を防止できる。したがって、外周部７の形状が損なわれ
るのを防止して、キャパシタ絶縁膜２４の電気的特性の
劣化を抑制することができる。As described above, in this manufacturing method, since the impurity diffusion is carried out at the optimum diffusion amount depending on the film thickness of the polycrystalline Si films 20 and 23 constituting the storage electrode 10, the storage electrode 10 is It is possible to prevent movement of high concentration grain boundaries while ensuring conductivity. Therefore, the shape of the outer peripheral portion 7 can be prevented from being damaged, and deterioration of the electrical characteristics of the capacitor insulating film 24 can be suppressed.
【００１８】なお、この実施例は、工程■，工程■にお
いて多結晶Ｓｉ膜２０，２３への不純物拡散を、いずれ
もＰＯＣｌ３を拡散源とした固相熱拡散法により行った
が、これに限られるものではない。それぞれイオン打ち
込みによるドーピング法を採用しても良い。Note that in this example, impurity diffusion into the polycrystalline Si films 20 and 23 in steps (1) and (2) was carried out by the solid phase thermal diffusion method using POCl3 as the diffusion source. It's not something you can do. A doping method by ion implantation may be adopted for each.
【００１９】[0019]
【発明の効果】以上より明らかなように、この発明の半
導体メモリ素子の製造方法は、半導体基板表面に形成さ
れたトランジスタと上記トランジスタの端子に一方の電
極がつながるキャパシタとからなるメモリセルを複数個
有し、上記キャパシタの上記一方の電極が、柱状または
カップ状をなす主部と、この主部の側壁の外周近傍を離
間して取り巻く外周部と、上記主部の端部と外周部の端
部とを一体に連結する底部とからなり、上記キャパシタ
の他方の電極が絶縁膜を挟んで上記一方の電極の各部に
対向する半導体メモリ素子の製造方法であって、上記半
導体基板表面に上記トランジスタを形成した後、上記キ
ャパシタの一方の電極材料として上記基板上に第１の多
結晶シリコン膜を形成する工程と、上記第１の多結晶シ
リコン膜に所定濃度の不純物をドープして導電率を高め
る工程と、上記一方の電極の主部を形成すべき領域の周
囲の上記第１の多結晶シリコン膜を薄膜の部分を残して
除去して、上記主部の側壁を形成する工程と、多結晶シ
リコンに対して選択的にエッチング可能な材料からなり
、上記主部側壁の外周を密着して取り巻く外周側壁を形
成する工程と、上記第１の多結晶シリコン膜よりも膜厚
が薄い第２の多結晶シリコン膜を上記半導体基板上に堆
積する工程と、上記第２の多結晶シリコン膜に所定濃度
の不純物をドープして導電率を高める工程と、この第２
の多結晶シリコン膜からなり、上記外周側壁を密着して
取り巻くと共に端部が上記第１の多結晶シリコン膜の上
記薄膜の部分に連結する外周部を形成する工程と、上記
外周部の周囲の領域の上記薄膜の部分を除去して底部を
形成する工程と、上記外周側壁を腐食剤によって除去す
る工程とを有し、この一方の電極の上にキャパシタ用の
絶縁膜および他方の電極を順次形成するようにしたので
、上記外周部の体積不純物濃度を必要以上に高くするこ
となく、蓄積電極全体の導電性を確保することができる
。したがって、上記外周部の表面で高濃度粒界の移動に
よって形状が損なわれる現象を回避でき、上記キャパシ
タ用の絶縁膜の電気的特性の劣化を抑制することができ
る。Effects of the Invention As is clear from the above, the method for manufacturing a semiconductor memory device according to the present invention is capable of manufacturing a plurality of memory cells each consisting of a transistor formed on the surface of a semiconductor substrate and a capacitor having one electrode connected to the terminal of the transistor. The one electrode of the capacitor has a main part having a columnar or cup shape, an outer peripheral part that surrounds the outer peripheral part of the side wall of the main part at a distance, and an end part of the main part and an outer peripheral part. and a bottom part integrally connected to the end part, and the other electrode of the capacitor faces each part of the one electrode with an insulating film interposed therebetween, the method comprising: After forming the transistor, there is a step of forming a first polycrystalline silicon film on the substrate as one electrode material of the capacitor, and doping the first polycrystalline silicon film with impurities at a predetermined concentration to improve conductivity. removing the first polycrystalline silicon film around the region where the main portion of the one electrode is to be formed, leaving only a thin film portion to form a side wall of the main portion; forming an outer peripheral side wall that is made of a material that can be selectively etched with respect to polycrystalline silicon and tightly surrounds the outer periphery of the main portion side wall; and a first polycrystalline silicon film that is thinner than the first polycrystalline silicon film. a step of depositing a second polycrystalline silicon film on the semiconductor substrate; a step of doping the second polycrystalline silicon film with impurities at a predetermined concentration to increase the conductivity;
forming an outer peripheral part made of a polycrystalline silicon film, closely surrounding the outer peripheral side wall and having an end connected to the thin film portion of the first polycrystalline silicon film; a step of removing the thin film portion of the region to form a bottom portion, and a step of removing the outer circumferential side wall with a corrosive agent, and sequentially forming an insulating film for a capacitor on the one electrode and the other electrode. With this structure, the conductivity of the entire storage electrode can be ensured without increasing the volumetric impurity concentration in the outer peripheral portion more than necessary. Therefore, it is possible to avoid a phenomenon in which the shape is damaged due to the movement of high-concentration grain boundaries on the surface of the outer peripheral portion, and it is possible to suppress deterioration of the electrical characteristics of the insulating film for the capacitor.
【図１】 この発明の一実施例の半導体メモリ素子の
製造方法を説明する工程図である。FIG. 1 is a process diagram illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.
【図２】 この発明の一実施例の半導体メモリ素子の
製造方法を説明する工程図である。FIG. 2 is a process diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention.
【図３】 この発明の一実施例の半導体メモリ素子の
製造方法を説明する工程図である。FIG. 3 is a process diagram illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.
【図４】 この発明の一実施例の半導体メモリ素子の
製造方法を説明する工程図である。FIG. 4 is a process diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention.
【図５】 この発明の一実施例の半導体メモリ素子の
製造方法を説明する工程図である。FIG. 5 is a process diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention.
【図６】 この発明の一実施例の半導体メモリ素子の
製造方法を説明する工程図である。FIG. 6 is a process diagram illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.
【図７】 本出願人が先に提案した半導体メモリ素子
の構造を示す断面図である。FIG. 7 is a cross-sectional view showing the structure of a semiconductor memory device previously proposed by the applicant.
１０ 蓄積電極
１１ Ｐ型Ｓｉ基板
１７，２１ ＳｉＯ２膜
１８ Ｓｉ３Ｎ４膜
２０ 第１の多結晶Ｓｉ膜（主部）２０ａ 側壁
２０ｂ 薄膜の部分（底部）
２２ 外周側壁
２３ 第２の多結晶Ｓｉ膜
２３ａ リング状多結晶Ｓｉ膜（外周部）２４
キャパシタ絶縁膜
２５ プレート電極
Ｃ キャパシタ10 Storage electrode 11 P-type Si substrate 17, 21 SiO2 film 18 Si3N4 film 20 First polycrystalline Si film (main part) 20a Side wall 20b Thin film part (bottom) 22 Outer peripheral side wall 23 Second polycrystalline Si film 23a Ring Polycrystalline Si film (outer periphery) 24
Capacitor insulating film 25 Plate electrode C Capacitor
Claims (1)
スタと上記トランジスタの端子に一方の電極がつながる
キャパシタとからなるメモリセルを複数個有し、上記キ
ャパシタの上記一方の電極が、柱状またはカップ状をな
す主部と、この主部の側壁の外周近傍を離間して取り巻
く外周部と、上記主部の端部と外周部の端部とを一体に
連結する底部とからなり、上記キャパシタの他方の電極
が絶縁膜を挟んで上記一方の電極の各部に対向する半導
体メモリ素子の製造方法であって、上記半導体基板表面
に上記トランジスタを形成した後、上記キャパシタの一
方の電極材料として上記基板上に第１の多結晶シリコン
膜を形成する工程と、上記第１の多結晶シリコン膜に所
定濃度の不純物をドープして導電率を高める工程と、上
記一方の電極の主部を形成すべき領域の周囲の上記第１
の多結晶シリコン膜を薄膜の部分を残して除去して、上
記主部の側壁を形成する工程と、多結晶シリコンに対し
て選択的にエッチング可能な材料からなり、上記主部側
壁の外周を密着して取り巻く外周側壁を形成する工程と
、上記第１の多結晶シリコン膜よりも膜厚が薄い第２の
多結晶シリコン膜を上記半導体基板上に堆積する工程と
、上記第２の多結晶シリコン膜に所定濃度の不純物をド
ープして導電率を高める工程と、この第２の多結晶シリ
コン膜からなり、上記外周側壁を密着して取り巻くと共
に端部が上記第１の多結晶シリコン膜の上記薄膜の部分
に連結する外周部を形成する工程と、上記外周部の周囲
の上記薄膜の部分を除去して底部を形成する工程と、上
記外周側壁を腐食剤によって除去する工程とを有し、こ
の一方の電極の上にキャパシタ用の絶縁膜および他方の
電極を順次形成するようにしたことを特徴とする半導体
メモリ素子の製造方法。1. A plurality of memory cells each comprising a transistor formed on a surface of a semiconductor substrate and a capacitor having one electrode connected to a terminal of the transistor, the one electrode of the capacitor having a columnar or cup shape. the other side of the capacitor; A method for manufacturing a semiconductor memory element in which an electrode faces each part of the one electrode with an insulating film interposed therebetween, the transistor being formed on the surface of the semiconductor substrate, and then forming a material on the substrate as one electrode material of the capacitor. a step of forming a first polycrystalline silicon film; a step of doping the first polycrystalline silicon film with impurities at a predetermined concentration to increase its conductivity; Surrounding the above first
removing the polycrystalline silicon film leaving only a thin film portion to form the sidewall of the main portion; forming an outer peripheral side wall that tightly surrounds the semiconductor substrate; depositing a second polycrystalline silicon film thinner than the first polycrystalline silicon film on the semiconductor substrate; A step of doping a silicon film with impurities at a predetermined concentration to increase its conductivity, and a second polycrystalline silicon film that tightly surrounds the outer peripheral side wall and whose end portions are similar to those of the first polycrystalline silicon film. forming an outer peripheral portion connected to the thin film portion; removing a portion of the thin film around the outer peripheral portion to form a bottom portion; and removing the outer peripheral side wall with a corrosive agent. . A method of manufacturing a semiconductor memory element, characterized in that an insulating film for a capacitor and the other electrode are sequentially formed on the one electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2402443A JP2644381B2 (en) | 1990-12-14 | 1990-12-14 | Method for manufacturing semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2402443A JP2644381B2 (en) | 1990-12-14 | 1990-12-14 | Method for manufacturing semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04215470A true JPH04215470A (en) | 1992-08-06 |
| JP2644381B2 JP2644381B2 (en) | 1997-08-25 |
Family
ID=18512266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2402443A Expired - Fee Related JP2644381B2 (en) | 1990-12-14 | 1990-12-14 | Method for manufacturing semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2644381B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04249363A (en) * | 1991-01-30 | 1992-09-04 | Samsung Electron Co Ltd | High integrated semiconductor memory device and manufacture thereof |
| JPH07130873A (en) * | 1993-11-01 | 1995-05-19 | Nec Corp | Manufacture of semiconductor device |
| JPH09199680A (en) * | 1996-01-17 | 1997-07-31 | Nec Corp | Semiconductor device and manufacture of the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0499373A (en) * | 1990-08-18 | 1992-03-31 | Mitsubishi Electric Corp | Semiconductor memory cell |
-
1990
- 1990-12-14 JP JP2402443A patent/JP2644381B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0499373A (en) * | 1990-08-18 | 1992-03-31 | Mitsubishi Electric Corp | Semiconductor memory cell |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04249363A (en) * | 1991-01-30 | 1992-09-04 | Samsung Electron Co Ltd | High integrated semiconductor memory device and manufacture thereof |
| JPH07130873A (en) * | 1993-11-01 | 1995-05-19 | Nec Corp | Manufacture of semiconductor device |
| JPH09199680A (en) * | 1996-01-17 | 1997-07-31 | Nec Corp | Semiconductor device and manufacture of the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2644381B2 (en) | 1997-08-25 |
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