JPH08236716A - Method of fabrication of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To realize stable operation of a MISFET of a peripheral circuit part in a semiconductor integrated circuit constructed with a memory array part and the peripheral circuit part. CONSTITUTION: An oxidized silicon film 9 and a polycrystalline silicon film 8 located at a memory array part are processed in order to form a gate electrode 11 of a memory cell selecting MISFET, and thereafter an n type semiconductor region 12 and a bit line 17 are formed successively, and then an information storing capacitor device composed of a lower electrode (a polycrystalline silicon film 21 and a polycrystalline silicon film 24), a dielectric film 25 and an upper electrode (a polycrystalline silicon film 26) is formed. Then. the dielectric film 25, an oxidized silicon film 18, an oxidized silicon film 14 and the oxidized silicon film 9 located at an upper layer of the polycrystalline silicon film 8 of a peripheral circuit part are etched in succession, and thereafter the polycrystalline silicon fi lm 8 is processed to form a gate electrode of a MISFET of the peripheral circuit part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device manufacturing technique, and more particularly to a DRAM (Dynamic Random Acce
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having an ss memory).

[0002]

2. Description of the Related Art In one of semiconductor integrated circuit devices, a memory cell is a memory cell selecting MISFET (Metal Insulator).
There is a DRAM including a semiconductor field effect transistor) and an information storage capacitive element. But DR
With the increase in the capacity of the AM, the miniaturization of the memory cell is advanced, the amount of accumulated charge of the information storage capacitive element is decreased, and the information retention characteristic is deteriorated.

Therefore, in the information storage capacitive element of DRAM of 4 Mbit or more, the storage electrode has a three-dimensional structure of a stacked type to increase its surface area,
The amount of accumulated charge is increased. However, in the peripheral circuit section and the memory cell array section in which a plurality of laminated information storage capacitive elements are arranged in parallel, the height of the information storage capacitive element is about the same as the height of the information storage capacitive element on the upper surface of the interlayer insulating film that covers them. There will be a difference.

This height difference causes a decrease in the dimensional accuracy of the photoresist in the photolithography for forming the wiring layer, and thus it is necessary to allow a sufficient depth of focus. However, in order to obtain an acceptable photolithic dimension, simply extrapolating from the trend of optical lithography technology, for example, 256 Mbit DRAM is ± 0.25 μm.
The following depth of focus is required, which is actually the resolution limit.

Therefore, in order to improve the dimensional accuracy, the recess array method is adopted in the DRAM having the laminated information storage capacitive element. In this method, memory cells are arranged in a recessed area formed on a semiconductor substrate to reduce the height difference between the upper surface of an interlayer insulating film covering the memory cell array portion and the peripheral circuit portion, and allow the height difference from the depth of focus of photolithography. It should be within the range.

In the method of manufacturing a DRAM by the recess array method, first, a recessed region is formed in a region where a memory cell is formed, then a field insulating film and a gate insulating film are sequentially formed on the surface of the semiconductor substrate, and then, , A polycrystalline silicon film and a silicon oxide film are sequentially deposited on a semiconductor substrate.

Next, the silicon oxide film and the polycrystalline silicon film are sequentially processed to form a memory cell selecting MISFET in the memory cell array section and a MISF in the peripheral circuit section.
After forming the gate electrode of ET, a low concentration source is formed on the semiconductor substrate of the memory cell array section and the peripheral circuit section,
Forming a drain region;

Next, after forming sidewalls on the side walls of the gate electrodes of the memory cell array portion and the peripheral circuit portion, high-concentration source and drain regions are formed on the semiconductor substrate of the peripheral circuit portion. Thereafter, a laminated information storage capacitor element is formed in the memory cell array portion, and then an interlayer insulating film is formed on the semiconductor substrate.

In addition, Press Journal, "Monthly Semiconductor World (Semiconductor World) 199"
July 3rd Edition "P79-P83, 256MDRAM applying double cylindrical type information storage capacitor element to recess array
Is described.

[0010]

The present inventor has found the following problems in developing the recess array type DRAM.

(1) In the recess array, the memory cell selecting MISFET in the memory cell array section and the M in the peripheral circuit section are arranged.
When the ISFET is formed, a difference in height has already occurred between the memory cell array portion and the peripheral circuit portion. Therefore, in optical lithography for forming the gate electrode, the memory cell array portion and the peripheral circuit portion have different depths of focus, and M
In ISFET, it is difficult to obtain the minimum processing size of the gate electrode.

(2) After forming the memory cell selecting MISFET of the memory cell array section and the MISFET of the peripheral circuit section, the information storage capacitive element is formed in the memory cell array section. However, since the information storage capacitive element has a stack-type storage electrode having a three-dimensional structure, the manufacturing process of the information storage capacitive element is complicated and the heat treatment time for the semiconductor substrate becomes long. .

For this reason, impurities in the source and drain regions of the MISFET are diffused more than necessary, and particularly in the MISFET of the peripheral circuit portion having a narrow operating voltage range, a short channel effect is prominent, which lowers the yield of DRAM. It becomes one of the factors.

An object of the present invention is to provide a MIS of a peripheral circuit portion in a DRAM having a laminated information storage capacitor element.
It is to provide a technique capable of realizing stable operation of an FET.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0016]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the method of manufacturing a semiconductor integrated circuit device according to the present invention uses the memory cell selection M of the memory cell array portion.
When forming the ISFET and the MISFET of the peripheral circuit portion, first, a gate insulating film is formed on the surface of the semiconductor substrate,
Next, after depositing a conductive film on the semiconductor substrate, the conductive film located in the memory cell array portion is processed,
The gate electrode of the memory cell selecting MISFET is formed. After that, a laminated information storage capacitor is formed in the memory cell array portion, and then the insulating film located above the conductive film of the peripheral circuit portion is removed, and then the conductive material located in the peripheral circuit portion is removed. The film is processed to form the gate electrode of the MISFET in the peripheral circuit section.

[0018]

According to the above-mentioned means, the gate electrode of the MISFET for memory cell selection in the memory cell array section and the gate electrode of the MISFET in the peripheral circuit section are processed in different manufacturing steps. The optimum processing size can be obtained.

Further, since the source and drain regions of the MISFET of the peripheral circuit portion are formed after the information storage capacitive element of the memory cell array portion is formed, the main heat history applied to the MISFET of the peripheral circuit portion is This is due to heat treatment at a low temperature for a short time, which is performed when forming the wiring layer. Therefore, diffusion of impurities in the source and drain regions of the MISFET in the peripheral circuit portion is suppressed, and the short channel effect can be suppressed.

[0020]

Embodiments of the present invention will now be described in detail with reference to the drawings.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) DR which is an embodiment of the present invention
A method for manufacturing the AM will be described with reference to FIGS.

First, the silicon oxide film 2 is formed on the semiconductor substrate 1.
After the silicon nitride film 3 and the silicon nitride film 3 are sequentially formed, the silicon nitride film 3 in the region to be the memory cell array portion is removed. Subsequently, as shown in FIG. 1, LOCO is formed on the surface of the semiconductor substrate 1 by selective oxidation using the silicon nitride film 3 as a mask.
After forming the S (Local Oxidation of Silicon) oxide film 4, the silicon nitride film 3, the silicon oxide film 2 and the LOCOS oxide film 4 on the semiconductor substrate 1 are removed.
A recessed region is formed in the memory cell array portion.

Next, as shown in FIG. 2, a p-type well 5, an n-type well (not shown), and a field insulating film 6 are sequentially formed on the main surface of the semiconductor substrate 1 by a known method, and then heat is applied. Oxidation treatment is performed to form a gate insulating film 7 on the surface of the semiconductor substrate 1, and then CVD (Chemical Vap) is performed on the semiconductor substrate 1.
or polycrystalline silicon film 8 and silicon oxide film 9 are sequentially deposited by the (or Deposition) method.

Next, as shown in FIG.
Using 0 as a mask, the silicon oxide film 9 and the polycrystalline silicon film 8 in the memory cell array portion are sequentially etched,
The gate electrode 11 of the memory cell selecting MISFET is formed. At this time, the silicon oxide film 9 and the polycrystalline silicon film 8 in the peripheral circuit portion are not etched.

Next, after removing the photoresist 10, the silicon oxide film 9 and the gate electrode 11 are used as a mask,
Ions of n-type impurities (phosphorus, for example) are implanted into the semiconductor substrate 1 to form n-type semiconductor regions (source and drain regions) 12 of the memory cell selecting MISFET in the memory cell array portion as shown in FIG.

After that, the silicon oxide film deposited by the CVD method on the semiconductor substrate 1 is subjected to RIE (Reactive Ion Etching).
Then, the sidewalls 13 are formed on the sidewalls of the silicon oxide film 9 in the memory cell array portion and the gate electrode 11 of the memory cell selecting MISFET.

Next, as shown in FIG. 5, after depositing a silicon oxide film 14 on the semiconductor substrate 1 by the CVD method, for example, chemical mechanical polishing (Chemical Mechanical Polishing) is performed.
The surface of the silicon oxide film 14 is flattened by the CMP method.

Next, the silicon oxide film 14 is etched by using a patterned photoresist (not shown) as a mask, and a MIS for selecting a memory cell in the memory cell array portion.
A contact hole 15 reaching one of the n-type semiconductor regions 12 of the FET is formed. After that, a polycrystalline silicon film (not shown) is deposited on the semiconductor substrate 1, and then the polycrystalline silicon film is etched by using the photoresist 16 as a mask to form the bit lines 17.

Next, after removing the photoresist 16,
As shown in FIG. 6, a silicon oxide film 1 is formed on the semiconductor substrate 1.
8 is deposited by the CVD method, and then this silicon oxide film 1 is deposited.
After flattening the surface of 8, the silicon nitride film 19 is deposited on the semiconductor substrate 1.

Next, using the patterned photoresist (not shown) as a mask, the silicon nitride film 19 and the silicon oxide film 18 in the memory cell array portion are sequentially etched, and as shown in FIG.
A contact hole 20 for connecting the other n-type semiconductor region 12 of the FET and a storage electrode formed later is formed.

Next, a polycrystalline silicon film 21 and a silicon oxide film 22 are sequentially deposited on the semiconductor substrate 1 by the CVD method, and then the silicon oxide film 22 and the polycrystalline silicon film 21 are sequentially etched using the photoresist 23 as a mask. By doing so, a part of the lower electrode of the storage electrode is formed.

Next, after removing the photoresist 23, as shown in FIG. 8, a polycrystalline silicon film 24 is formed on the semiconductor substrate 1.
Then, the polycrystalline silicon film 24 is deposited on the RI.
Etching is performed by the E method to leave the polycrystalline silicon film 24 on the sidewalls of the silicon oxide film 22 and the polycrystalline silicon film 21.

Then, the silicon oxide film 22 is removed by, for example, wet etching using a hydrofluoric acid solution, and the polycrystalline silicon film 21 and the polycrystalline silicon film 2 are removed.
The lower electrode of the cylindrical storage electrode of 4 is formed.

Next, after removing the silicon nitride film 19 with a hot phosphoric acid solution, a silicon nitride film (not shown) is subjected to CV.
As shown in FIG. 9, a dielectric film 25 made of a silicon oxide film and a silicon nitride film is deposited on the surface of the lower electrode of the storage electrode by depositing it on the semiconductor substrate 1 by the D method and subsequently performing an oxidation treatment. Form.

After that, a polycrystalline silicon film 26 is deposited on the semiconductor substrate 1, and the polycrystalline silicon film 26 is etched by using a patterned photoresist (not shown) as a mask to form an upper portion which is a plate electrode of a storage electrode. Form electrodes.

Next, as shown in FIG. 10, a photoresist 27 is formed on the semiconductor substrate 1 of the memory cell array portion,
Using this as a mask, the dielectric film 25, the silicon oxide film 18, the silicon oxide film 14 and the silicon oxide film 9 in the peripheral circuit portion are sequentially etched. At this time, the polycrystalline silicon film 8 located below the silicon oxide film 9 is used as an etching stopper.

Next, the n-type MISFET of the peripheral circuit portion is formed. First, as shown in FIG.
Is used as a mask to process the polycrystalline silicon film 8 to form the gate electrode 29 of the n-type MISFET on the p-type well 5 in the peripheral circuit section, and then again using the photoresist 28 as a mask to form the p-type well 5 in the peripheral circuit section. Then, an n-type impurity (eg, phosphorus) is ion-implanted into the n-type semiconductor region (source / drain region) 30.

Next, after removing the photoresist 28, as shown in FIG. 12, the silicon oxide film deposited on the semiconductor substrate 1 by the CVD method is etched by the RIE method,
A sidewall 31 is formed on the sidewall of the gate electrode 29 of the n-type MISFET in the peripheral circuit section.

Thereafter, using the gate electrode 29 and the side wall 31 formed on the side wall thereof as a mask, n-type impurities (for example, arsenic) are ion-implanted into the p-type well 5, and n
Form an n-type high-concentration semiconductor region (source / drain region) 32 of the MISFET.

Subsequently, although not shown, a p-type MISFET for the peripheral circuit section is formed by the same manufacturing method as the n-type MISFET for the peripheral circuit section described above. That is, the polycrystalline silicon film 8 is processed, and the p-type M is formed on the n-type well of the peripheral circuit section.
After forming the gate electrode of the ISFET, p is added to the n-type well.
A p-type semiconductor region (source and drain regions) is formed by ion-implanting a type impurity (for example, boron). Then
After forming a sidewall on the side wall of the gate electrode of the p-type MISFET, p-type impurities are ion-implanted into the n-type well to form a p-type high-concentration semiconductor region (source, drain region) of the p-type MISFET.

When forming the p-type high-concentration semiconductor region, a photoresist is formed on the gate electrode in order to prevent the implantation of p-type impurities into the gate electrode of the p-type MISFET, and the photoresist and the gate electrode are separated from each other. Using the sidewall formed on the sidewall as a mask, p-type impurities are ion-implanted into the n-type well.

Next, as shown in FIG. 13, the semiconductor substrate 1
An interlayer insulating film 33 is deposited on the interlayer insulating film 33, and the surface of the interlayer insulating film 33 is flattened by, for example, the CMP method. After that, the metal wiring layer 34 and the MISFE of the peripheral circuit portion formed later are formed.
In order to form a contact hole 35 for connecting the T or the bit line 17 of the memory cell array portion, using a patterned photoresist (not shown) as a mask,
The interlayer insulating film 33 is etched.

Next, after depositing a metal film (not shown) made of, for example, an aluminum alloy film or tungsten silicide on the semiconductor substrate 1, this metal film is used as a mask with a patterned photoresist (not shown). Then, the metal wiring layer 34 is formed, and finally the surface of the semiconductor substrate 1 is covered with the passivation film 36, whereby the DRAM of this embodiment is completed.

As described above, in this embodiment, the gate electrode 1 of the memory cell selecting MISFET in the memory cell array portion is
1 and the gate electrode 29 of the MISFET of the peripheral circuit part are processed by different manufacturing processes, so that DR in the recess array
Even if AM is formed, optimum processing dimensions can be obtained in the gate electrode of each MISFET.

Further, since the gate electrode of the MISFET and the semiconductor region of the peripheral circuit section are formed after the memory cell selecting MISFET and the information storage capacitive element of the memory cell array section are formed, the MISFE of the peripheral circuit section is formed.
The heat treatment step applied to T can be reduced, and the short channel effect of the MISFET in the peripheral circuit section can be suppressed.

(Embodiment 2) DR which is an embodiment of the present invention
A method of manufacturing the AM will be described with reference to FIGS. 14 and 15.

First, similarly to the DRAM manufacturing method described in the first embodiment, the memory cell selecting MISFET, the bit line 17, and the information storing capacitive element in the memory cell array portion are formed. Then, as shown in FIG. 14, a photoresist 37 is formed on the semiconductor substrate 1 of the memory cell array portion, and using this as a mask, the dielectric film 2 of the peripheral circuit portion is formed.
5, silicon oxide film 18, silicon oxide film 14, silicon oxide film 9, polycrystalline silicon film 8 and gate insulating film 7
Are sequentially etched.

Next, after removing the photoresist 37,
As shown in FIG. 15, the gate insulating film 38 is formed on the surface of the semiconductor substrate 1 in the peripheral circuit portion by performing the thermal oxidation process, and then the polycrystalline silicon film 39 is formed on the semiconductor substrate 1.
Are deposited by the CVD method.

Next, the polycrystalline silicon film 39 is processed by using the photoresist 40 as a mask, and the n-type MIS of the peripheral circuit portion is processed.
The gate electrode of the FET or p-type MISFET is formed. After that, as in the first embodiment, M of the peripheral circuit section is
The DRAM of the second embodiment is completed by forming the sidewalls and semiconductor regions of the ISFET, the interlayer insulating film, the metal wiring layer and the passivation film.

As described above, according to the method of manufacturing the DRAM of the second embodiment, the thickness of the gate insulating film and the thickness of the gate electrode of the memory cell selecting MISFET in the memory cell array section and the MISFET in the peripheral circuit section are set respectively. Since it can be set arbitrarily, control of the operating characteristics of the MISFET becomes easy.

The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above-mentioned embodiment, the method of manufacturing the DRAM formed in the recess array has been described, but the present invention can be applied to the DRAM not using the recess array.

Further, in the above-mentioned embodiment, the capacitor over-position in which the information storage capacitive element is arranged above the bit line
Although the method of manufacturing the DRAM having the memory cell of the bit line (Capacitor Over Bitline; COB) structure has been described, the present invention can be applied to the DRAM having the memory cell in which the bit line is arranged above the information storage capacitive element.

Further, in the above embodiment, the DR having the memory cell using the cylindrical storage electrode as the information storage capacitor element is provided.
Although the method of manufacturing the AM has been described, the method is not limited to the cylindrical type, and can be applied to, for example, a DRAM having a memory cell using a fin type or a simple stacked type storage electrode.

Further, in the above-mentioned embodiment, the two-layer film consisting of the silicon oxide film and the silicon nitride film is used as the dielectric film of the information storage capacitive element, but a high dielectric film such as a tantalum oxide film, a PZT film or the like is used. You may use the laminated film of these films.

Further, although the polycrystalline silicon film is used for the gate electrode of the MISFET in the above embodiment, a laminated film of a silicide film (for example, tungsten silicide) and a polycrystalline silicon film may be used.

Further, in the above embodiment, the silicon oxide film is used as the insulating film located in contact with the gate electrode of the memory cell selecting MISFET in the memory cell array portion. However, an insulating film other than the silicon oxide film, for example, a nitride film is used. A stacked film of a silicon film or a silicon oxide film and a silicon nitride film may be used.

[0059]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

According to the present invention, the MISFE of the peripheral circuit section is
At T, the optimum processing size of the gate electrode can be obtained, and further, diffusion of impurities in the source and drain regions of the MISFET in the peripheral circuit portion can be suppressed, and the short channel effect can be suppressed. Part of M
A stable operation of the ISFET can be realized.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a manufacturing process of a DRAM which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts of a semiconductor substrate showing a manufacturing process of a DRAM which is an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a manufacturing process of a DRAM which is an embodiment of the present invention.

FIG. 4 is a cross-sectional view of essential parts of a semiconductor substrate showing a manufacturing process of a DRAM which is an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a manufacturing process of a DRAM which is an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a manufacturing process of a DRAM which is an embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a manufacturing process of a DRAM which is an embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a manufacturing process of a DRAM which is an embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate showing the manufacturing process of the DRAM which is an embodiment of the present invention;

FIG. 10 is a main-portion cross-sectional view of the semiconductor substrate showing the manufacturing process of the DRAM which is an embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate showing the manufacturing process of the DRAM which is an embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate showing the manufacturing process of the DRAM which is an embodiment of the present invention;

FIG. 13 is a main-portion cross-sectional view of the semiconductor substrate showing the manufacturing process of the DRAM which is an embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate showing the manufacturing process of the DRAM which is another embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate showing the manufacturing process of the DRAM which is another embodiment of the present invention;

[Explanation of symbols]

 1 semiconductor substrate 2 silicon oxide film 3 silicon nitride film 4 LOCOS oxide film 5 p-type well 6 field insulating film 7 gate insulating film 8 polycrystalline silicon film 9 silicon oxide film 10 photoresist 11 gate electrode 12 n-type semiconductor region (source, drain) Area) 13 Sidewall 14 Silicon oxide film 15 Contact hole 16 Photoresist 17 Bit line 18 Silicon oxide film 19 Silicon nitride film 20 Contact hole 21 Polycrystalline silicon film 22 Silicon oxide film 23 Photoresist 24 Polycrystalline silicon film 25 Dielectric film 26 Multi Crystal silicon film 27 Photoresist 28 Photoresist 29 Gate electrode 30 n-type semiconductor region (source / drain region) 31 Sidewall 32 n-type high-concentration semiconductor region (source / drain region) 33 Isolation Film 34 metal wiring layer 35 contact holes 36 a passivation film 37 a photoresist 38 gate insulating film 39 a polycrystalline silicon film 40 photoresist

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tsuneo Ono 2326 Imai, Ome City, Tokyo, Hitachi, Ltd. Device Development Center (72) Inventor Ejizaki Yuji 2350 Miuramura, Miuramura, Inashiki-gun, Ibaraki Japan Textiles・ Instruments Co., Ltd. (72) Inventor Shunichi Sukegawa 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Nihon Textus Instruments Co., Ltd.

Claims (9)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device comprising a memory cell array part and a peripheral circuit part, wherein a first gate insulating film is formed on a surface of a semiconductor substrate,
Next, a step of depositing a first conductive film on the semiconductor substrate, a step of processing the first conductive film located in the memory cell array portion to form a gate electrode of a MISFET for memory cell selection, the memory Forming a stacked information storage capacitor element in the cell array section, removing an insulating film located above the first conductive film of the peripheral circuit section, and the first located in the peripheral circuit section A method of manufacturing a semiconductor integrated circuit device, comprising a step of processing a conductive film to form a gate electrode of a MISFET in the peripheral circuit section. 2. A method of manufacturing a semiconductor integrated circuit device comprising a memory cell array part and a peripheral circuit part, wherein a first gate insulating film is formed on a surface of a semiconductor substrate,
Next, a step of depositing a first conductive film on the semiconductor substrate, a step of processing the first conductive film located in the memory cell array portion to form a gate electrode of a MISFET for memory cell selection, the memory A step of forming a laminated information storage capacitive element in the cell array part, an insulating film located above the first conductive film of the peripheral circuit part, the first conductive film located in the peripheral circuit part, and A step of sequentially removing the first gate insulating film located in the peripheral circuit section, and a second step on the surface of the semiconductor substrate of the peripheral circuit section.
Forming a gate insulating film, and then forming a second conductive film on the semiconductor substrate, processing the second conductive film located in the peripheral circuit portion, and then forming the MIS of the peripheral circuit portion.
A method of manufacturing a semiconductor integrated circuit device, comprising the step of forming a gate electrode of an FET. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first conductive film located in the peripheral circuit section is etched when the insulating film in the peripheral circuit section is removed. Used as a stopper for a semiconductor integrated circuit device. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the second conductive film formed in the memory cell array portion forms a part of a plate electrode of the information storage capacitive element. A method of manufacturing a semiconductor integrated circuit device, comprising: 5. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the first conductive film and the second conductive film are provided.
2. A method of manufacturing a semiconductor integrated circuit device, wherein the conductive films have different thicknesses. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the memory cell array portion is formed in a recessed region provided in the semiconductor substrate. A method for manufacturing a semiconductor integrated circuit device, comprising: 7. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first conductive film or the second conductive film is a polycrystalline silicon film or a polycrystalline silicon film. A method of manufacturing a semiconductor integrated circuit device, which is a laminated film of a crystalline silicon film and a silicide film. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the memory cells forming the memory cell array section include one information storage capacitor and one memory cell. A method of manufacturing a semiconductor integrated circuit device, which is a DRAM cell including a memory cell selecting MISFET. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the information storage capacitive element is a cylindrical type, a fin type, or a simple stacked type. Of a semiconductor integrated circuit device having a dynamic structure.