JPH10178160A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a memory cell finer and also to realize fast operation of a DRAM for a DRAM, provided with a memory cell of COB(capacitor over bit line) structure. SOLUTION: For a pillar-like polycrystal line silicon film 1, which connects an accumulating electrode 25 of information accumulation capacitance element and an n-type semiconductor region 17 of MISFET(metal insulator semiconductor filed effect transistor) for memory selection, a bit-line compressing a tungsten film 23 and an adhesive layer 22 is formed by self-matching. The bit-line and a part of a sidewall of the bit-line are covered with a silicon oxide film 24 of low dielectric constant and a silicon oxide film 20, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a so-called COB.
The present invention relates to a technology effective when applied to a DRAM (Dynamic Random Access Memory) having a memory cell having a (Capacitor Over Bitline) structure.

[0002]

2. Description of the Related Art In recent years, large-capacity DRAMs have been designed so that the information storage capacitor is replaced with a memory cell selection M in order to compensate for the decrease in the amount of charge stored in the information storage capacitor accompanying the miniaturization of memory cells.
ISFET (Metal Insulator Semiconductor Field Ef
fect Transistor).

[0003] Among the stacked memory cells, a capacitor over bit line (COB) structure in which an information storage capacitive element is arranged above a bit line for directly transmitting information of a memory cell to a sense amplifier in a peripheral circuit section. In the memory cell of (1), since the underlying step of the storage electrode of the information storage capacitor is flattened by the bit line, the load on the process when forming the information storage capacitor can be reduced. It has features such as being able to obtain a high signal-to-noise (S / N) ratio because it is shielded by the information storage capacitive element.

[0004]

By the way, the above COB
In the memory cell having the structure, after the bit line is formed, the storage electrode of the information storage capacitor and the memory cell selecting MISF are formed.
A connection hole for connecting the ET to the semiconductor region is formed. However, as DRAMs become more highly integrated, memory cells are miniaturized, and it is difficult to secure a margin for alignment between bit lines and the connection holes in layout design.

For example, in a 256 Mbit DRAM, the pitch of a bit line having a line width of 0.25 μm is 0.6.
μm, the space between adjacent bit lines is 0.35μ
m. If a connection hole having a diameter of 0.30 μm is arranged in this space, the allowance for the alignment between the bit line and the connection hole is 0.0 per side.
25 μm, which is an unrealizable value.

SUMMARY OF THE INVENTION An object of the present invention is to provide a DRAM having a memory cell having a COB structure, which is capable of realizing miniaturization of the memory cell and, at the same time, realizing high-speed operation of the DRAM.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) a semiconductor integrated circuit device according to the present invention includes a bit line connected to one semiconductor region of a memory cell selection MISFET and directly transmitting information of a memory cell to a sense amplifier of a peripheral circuit portion; A DRAM having a capacitor-over-bit line structure memory cell having a columnar electrode connecting the other semiconductor region of the MISFET and the storage electrode of the information storage capacitor; and A side surface or a part of the side surface is covered with a silicon nitride film, a side wall or a part of the side wall of the bit line is covered with a first silicon oxide film, and the bit line is covered with a second silicon oxide film. .

(2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a step of forming a plug electrode in a first connection hole for connecting one semiconductor region of a memory cell selecting MISFET to a bit line is provided. And the memory cell selecting MI
Forming a columnar electrode in a second connection hole connecting the other semiconductor region of the SFET and the storage electrode, and processing the exposed portion of the upper side surface of the columnar electrode to be thin, and then forming the columnar electrode. Covering the exposed portion of the side surface with a silicon nitride film, depositing a first silicon oxide film on the semiconductor substrate, forming a groove in the first silicon oxide film above the plug electrode, Forming the bit line in the trench, covering the bit line with a second silicon oxide film, and simultaneously exposing the top of the columnar electrode; and storing the storage electrode in contact with the top of the columnar electrode. Forming an information storage capacitive element comprising a dielectric film and a plate electrode.

(3) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a step of forming a plug electrode in a first connection hole for connecting one semiconductor region of a memory cell selecting MISFET to a bit line is provided. And the memory cell selecting MI
Forming a silicon nitride film on the inner wall of a second connection hole connecting the other semiconductor region of the SFET and the storage electrode, and then forming a columnar electrode in the second connection hole; Forming a groove in the first silicon oxide film above the plug electrode after depositing the first silicon oxide film, and then forming a bit line in the groove; Covering the silicon oxide film and exposing the top of the columnar electrode at the same time, and forming a storage electrode, a dielectric film and an information storage capacitor composed of a plate electrode in contact with the top of the columnar electrode. Have.

According to the above-described means, the bit line can be formed by self-alignment with the pillar-shaped electrode connecting the other semiconductor region of the memory cell selection MISFET and the storage electrode of the information storage capacitor. Further, since the bit line and the side wall or a part of the side wall of the bit line are covered with the silicon oxide film having a low relative dielectric constant, the parasitic capacitance of the bit line can be suppressed.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIG. 1A is a cross-sectional view of a main part of a semiconductor substrate showing a memory cell of a DRAM according to an embodiment of the present invention, and FIG. FIG. 5 is a cross-sectional view of a main part of a semiconductor substrate parallel to a word line forming a gate electrode of a memory cell selection MISFET at line A ′.

A bit line is formed by embedding an adhesive layer 22 and a tungsten film 23 in a groove 21 provided in a silicon oxide film 20.
One n-type semiconductor region 1 of a memory cell selecting MISFET formed in a p-type well 2 via a plug electrode 12 constituted by a polycrystalline silicon film embedded in
3 is connected. The upper part of the bit line and part of the side wall are covered with the silicon oxide film 24 and the silicon oxide film 20, respectively.

The storage electrode 25 of the information storage capacitance element is connected to a memory cell selection formed in the p-type well 2 via a columnar polycrystalline silicon film (columnar electrode) 16 standing in the second connection hole 15. N-type semiconductor region 17 of the other MISFET
The side surface of the columnar polycrystalline silicon film 16 adjacent to the bit line is protected by a silicon nitride film 19.

Next, a method of manufacturing the memory cell of the DRAM according to the first embodiment will be described with reference to FIGS. 2A to 14 are cross-sectional views corresponding to FIG. 1A, and FIG. 2B is a cross-sectional view corresponding to FIG.

First, as shown in FIG. 2, p ^- type silicon single crystal is formed on a main surface of a semiconductor substrate 1 by a known method.
Mold well 2, field insulating film 3, and gate insulating film 4
Are sequentially formed.

Next, sequentially deposited polycrystalline silicon film 5 phosphorus (P) is introduced on the semiconductor substrate 1, a tungsten silicide (WSi _x) film 6, a silicon oxide film (not shown) and the silicon nitride film 7 I do. Thereafter, the silicon nitride film 7 using a photoresist as a mask, the silicon oxide film, by sequentially etching the laminated film made WSi _x film 6 and the polycrystalline silicon film 5, WSi _x film 6
For memory cell selection consisting of silicon and polycrystalline silicon film 5
The gate electrode of the ISFET is formed.

[0020] Although using the WSi _x film 6 on top of the gate electrode, other metal silicide films such as molybdenum silicide (MoSi _x) film, a titanium silicide (TiSi _x) film or a tantalum silicide (TaS
i _x) film or the like may be used.

Next, by performing thermal oxidation treatment on the semiconductor substrate 1 to form a thin silicon oxide film on the side wall of the WSi _x film 6 and the polycrystalline silicon film 5 constituting the gate electrode (not shown). Thereafter, the silicon nitride film deposited on the semiconductor substrate 1 is processed by anisotropic etching such as RIE (Reactive Ion Etching) to form a sidewall spacer 8 on the side wall of the gate electrode of the memory cell selecting MISFET. I do. Next, the semiconductor substrate 1
After forming a planarized silicon oxide film 9 thereon, a silicon nitride film 10 is deposited on the semiconductor substrate 1.

Next, as shown in FIG. 3, using a photoresist as a mask, the silicon nitride film 10, the silicon oxide film 9
Then, by sequentially etching the insulating film of the same layer as the gate insulating film 4, the first connection hole 11 is formed on the p-type well 2 to which the bit line is connected later.

Next, a polycrystalline silicon film with P introduced on the semiconductor substrate 1 is formed by CVD (Chemical Vapor Depositio).
n) After the deposition by the method, the first
A plug electrode 12 is formed in the connection hole 11 of FIG. 1, and then a silicon oxide film 14 is deposited on the semiconductor substrate 1. In addition,
From the polycrystalline silicon film forming the plug electrode 12, P
Diffusion into the mold well 2 forms one n-type semiconductor region 13 of the memory cell selecting MISFET.

Next, as shown in FIG. 4, the silicon oxide film 14, the silicon nitride film 1
The second connection hole 15 is formed in the p-type well 2 to which the storage electrode is to be connected later by sequentially etching the insulating film of the same layer as the silicon oxide film 9 and the gate insulating film 4. Next, a polycrystalline silicon film 16 into which P is introduced is deposited on the semiconductor substrate 1 by a CVD method, the surface thereof is flattened, and then a silicon nitride film 18 is deposited on the semiconductor substrate 1. Note that the polycrystalline silicon film 16
Is diffused into the p-type well 2 to form the other n-type semiconductor region 17 of the memory cell selecting MISFET.

Next, as shown in FIG. 5, the silicon nitride film 18 and the polycrystalline silicon film 16 are sequentially etched using the photoresist as a mask to form the columnar polycrystalline silicon film 16. Next, the exposed upper side surface of the pillar-shaped polycrystalline silicon film 16 is thinned by isotropic etching (FIG. 6), and then a silicon nitride film 19 is deposited again on the semiconductor substrate 1 (FIG. 7). ).

Next, as shown in FIG. 8, after the silicon nitride film 19 is left only on the upper side surface of the pillar-shaped polycrystalline silicon film 16 by anisotropic etching, as shown in FIG. Silicon oxide film 2 planarized on substrate 1
0 is formed.

Next, as shown in FIG. 10, a groove 21 is formed by sequentially etching the silicon oxide film 20 and the silicon oxide film 14 in a region where a bit line is to be formed later, and then, as shown in FIG. Then, an adhesive layer 22 and a tungsten film 23 are sequentially deposited on the semiconductor substrate 1.
Note that the adhesive layer 22 is formed of, for example, a laminated film including a titanium nitride film and a titanium film.

Next, as shown in FIG. 12, the tungsten film 23 and the adhesive layer 22 are sequentially processed by etch-back, and are left only in the groove 21, so that the bit line composed of the tungsten film 23 and the adhesive layer 22 is supported. It is formed by self-alignment with the polycrystalline silicon film 16 in a shape.

Next, as shown in FIG.
After the silicon oxide film 24 is deposited thereon, as shown in FIG. 14, the surface of the silicon oxide film 24 is flattened, and at the same time, the tops of the pillar-shaped polycrystalline silicon films 16 are exposed.

Thereafter, a storage electrode 25, a dielectric film 26 and a plate electrode 27a which are in contact with the top of the columnar polycrystalline silicon film 16 are formed.
a, sidewall spacers 28 composed of a silicon oxide film on the side walls of dielectric film 26 and storage electrode 25
Is formed, and then the plate electrode 27b is formed, whereby the DRAM of FIG. 1 is completed. The storage electrode 25 and the plate electrodes 27a and 27b have metal electrodes,
For example, ruthenium (Ru) is used and the dielectric film 2
6, (Ba, Sr) TiO 2 having a high dielectric constant formed by, for example, MOCVD (Metal Organic CVD).
_Three films are used.

Although a part of the side wall of the bit line is covered with the silicon oxide film 20 in the first embodiment, the side wall of the bit line may be entirely covered with the silicon oxide film 20.

Next, a method of manufacturing the direct peripheral circuit according to the first embodiment will be described. 15 to 18 are cross-sectional views of a main part of a semiconductor substrate showing a method of manufacturing a direct peripheral circuit. Among semiconductor elements formed in the direct peripheral circuit, an n-channel MISFET formed on a p-type well 2 is shown. Only shows.

FIG. 15 is a sectional view of a main part of the semiconductor substrate 1 in the manufacturing process shown in FIG. In the memory cell portion, the top and upper side surfaces of the pillar-shaped polycrystalline silicon film 16 are covered with a silicon nitride film 18 and a silicon nitride film 19.
, And a silicon oxide film 20 is deposited thereon. In the direct peripheral circuit portion, after the silicon oxide film 20 is deposited, the n-channel type MI
Part of the first-layer wiring connected to the n-type semiconductor region 29 of the SFET is formed.

That is, at the same time as the gate electrode of the memory cell selecting MISFET of the memory cell, the gate electrode of the n-channel MISFET in the peripheral circuit portion is formed, and then the photoresist and the n-channel MISFET are formed.
The n-type semiconductor region 29 of the n-channel MISFET is formed by ion-implanting an n-type impurity, for example, P into the p-type well 2 using the gate electrode as a mask.

Next, a silicon oxide film 2 is formed on the semiconductor substrate 1.
Then, the silicon oxide film 20, the silicon oxide film 14, the silicon nitride film 10, the silicon oxide film 9, and the insulating film in the same layer as the gate electrode are sequentially etched to directly deposit the n-channel MISFET in the peripheral circuit portion. N
A third connection hole 30 is formed on the mold semiconductor region 29.

Next, after sequentially depositing an adhesive layer 31 and a tungsten film 32 on the semiconductor substrate 1, the tungsten film 32 and the adhesive layer 31 are sequentially processed by etch-back and embedded in the third connection hole 30. By
A part of a first-layer wiring including the tungsten film 32 and the adhesive layer 31 is formed.

Next, as shown in FIG. 16, simultaneously with forming the groove 21 in the memory cell, the silicon oxide film 20 and the silicon oxide film 14 are also sequentially etched in the direct peripheral circuit portion, thereby forming the tungsten film 32 and the adhesive film. The groove 2 is in contact with a part of the first-layer wiring composed of the layer 31.
Form one. Thereafter, the adhesive layer 2 is again formed on the semiconductor substrate 1.
2 and a tungsten film 23 are sequentially deposited.

Next, as shown in FIG. 17, the tungsten film 23 and the adhesive layer 22 are sequentially processed by etch-back, and are left only in the groove 21. Thereby, a bit line composed of the tungsten film 23 and the adhesive layer 22 is formed in the memory cell, and the tungsten film 3 is formed directly in the peripheral circuit portion.
2 and wiring consisting of adhesive layer 31 and tungsten film 23
The first layer wiring of the peripheral circuit portion is directly formed by the wiring composed of the adhesive layer 22 and the wiring.

Thereafter, as shown in FIG. 18, after depositing a silicon oxide film 24 on the semiconductor substrate 1, the surface thereof is flattened and, at the same time, the top of the columnar polycrystalline silicon film 16 of the memory cell is exposed. Let it.

As described above, according to the first embodiment, the bit line can be formed by self-alignment with the pillar-shaped polycrystalline silicon film 16, and furthermore, the bit line can be formed on the bit line and on the side wall of the bit line. Since the portion is covered with the silicon oxide film having a low relative dielectric constant, the parasitic capacitance of the bit line can be suppressed.

(Embodiment 2) FIGS. 19 to 2 show a method of manufacturing a memory cell of a DRAM according to another embodiment of the present invention.
3 will be described.

First, in the same manufacturing method as in the first embodiment, as shown in FIG.
After forming the FET, a silicon oxide film 9 and a silicon nitride film 10 are sequentially deposited on the semiconductor substrate 1. After this,
A first connection hole 11 is formed on the p-type well 2 to which a bit line is to be connected later, and a plug electrode 12 made of a polycrystalline silicon film is formed in the first connection hole 11.

Next, as shown in FIG.
After a silicon oxide film 33 is deposited thereon, the silicon oxide film 33 and the silicon nitride film 1 are
The fourth connection hole 34 is formed on the p-type well 2 to which the storage electrode is to be connected later by sequentially etching the insulating film of the same layer as the silicon oxide film 9 and the gate insulating film 4.

Next, as shown in FIG.
After depositing a polycrystalline silicon film 35 with P introduced thereon by the CVD method, the fourth connection hole 3 is etched back.
4 is filled with a polycrystalline silicon film 35 and then the silicon oxide film 33 is removed to form a columnar polycrystalline silicon film 35 (FIG. 21).

Next, as shown in FIG. 22, the upper exposed side surface of the pillar-shaped polycrystalline silicon film 35 is thinned by isotropic etching, and then the silicon nitride film 36 is formed on the semiconductor substrate 1. Then, the silicon nitride film 36 is left only on the upper side surface of the pillar-shaped polycrystalline silicon film 35 by anisotropic etching.

Next, as shown in FIG.
A planarized silicon oxide film 37 is formed thereon. Thereafter, the memory cell is completed in the same manner as in the manufacturing method described in the first embodiment (FIGS. 10 to 14).

(Embodiment 3) FIGS. 24 to 2 show a method of manufacturing a memory cell of a DRAM according to another embodiment of the present invention.
6 will be described.

First, as shown in FIG. 19 of the second embodiment, after a memory cell selecting MISFET and a plug electrode 12 made of a polycrystalline silicon film are formed, a p-type well to which a storage electrode is later connected is formed. A fourth connection hole 34 is formed on 2.

Next, as shown in FIG.
After depositing the silicon nitride film 38 thereon, the silicon nitride film 38 is left only on the inner wall of the fourth connection hole 34 by anisotropic etching (FIG. 25).

Next, as shown in FIG.
After a polycrystalline silicon film 39 with P introduced thereon is deposited by a CVD method, the fourth connection hole 3 is etched back.
In step 4, a pillar-shaped polycrystalline silicon film 39 is formed. Thereafter, the manufacturing method described in the first embodiment (FIGS. 9 to 1)
The memory cell is completed as in 4).

As described above, according to the third embodiment, the number of manufacturing steps can be reduced by leaving the silicon oxide film 33 in which the fourth connection hole 34 is formed and using it as an interlayer insulating film. Can be.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0053]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, in a DRAM having a memory cell having a COB structure, a memory cell selecting M
Since the bit line can be formed by self-alignment with the columnar electrode connecting the semiconductor region of the ISFET and the storage electrode of the information storage capacitor element, the memory cell can be miniaturized, By covering the side wall of the bit line or a part of the side wall with an insulating film having a low relative dielectric constant, the parasitic capacitance of the bit line can be suppressed.
High-speed operation of the DRAM can be realized.

(2) According to the present invention, the DRA
In the manufacturing method of M, since a groove for easily securing the etching selectivity is formed and the bit line is buried in this groove, the process margin is increased.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to an embodiment of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to another embodiment of the present invention;

FIG. 20 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to another embodiment of the present invention;

FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

FIG. 22 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to another embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

FIG. 24 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to another embodiment of the present invention;

FIG. 25 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 p-type well 3 field insulating film 4 gate insulating film 5 polycrystalline silicon film 6 tungsten silicide film 7 silicon nitride film 8 sidewall spacer (silicon nitride film) 9 silicon oxide film 10 silicon nitride film 11 first connection Hole 12 Plug electrode 13 N-type semiconductor region 14 Silicon oxide film 15 Second connection hole 16 Polycrystalline silicon film (support electrode) 17 N-type semiconductor region 18 Silicon nitride film 19 Silicon nitride film 20 Silicon oxide film 21 Groove 22 Adhesion Layer 23 Tungsten film 24 Silicon oxide film 25 Storage electrode 26 Dielectric film 27a Plate electrode 27b Plate electrode 28 Sidewall spacer (silicon oxide film) 29 n-type semiconductor region 30 Third connection hole 31 Adhesive layer 32 Tungsten film 33 Silicon oxide Membrane 34 4 of the connection hole 35 a polycrystalline silicon film 36 a silicon-silicon film 37 a silicon oxynitride film 38 nitride film 39 a polycrystalline silicon film

Claims (10)

[Claims] 1. A semiconductor integrated circuit device having a DRAM provided with a memory cell having a structure in which a capacitor is formed above a bit line, comprising: a MISFE for selecting a memory cell.
A bit line, which is connected to one semiconductor region of T and transmits the information of the memory cell directly to the sense amplifier of the peripheral circuit portion, is connected to the other semiconductor region of the MISFET for memory cell selection and the storage electrode of the information storage capacitor. A columnar electrode, at least a part of a side surface of the columnar electrode is covered with a first insulating film, and at least a part of a side wall of the bit line is covered with a second insulating film. A semiconductor integrated circuit device, wherein the line is covered with a third insulating film. 2. The semiconductor integrated circuit device according to claim 1, wherein said first insulating film serves as a stopper layer when etching said second insulating film. 3. The semiconductor integrated circuit device according to claim 1, wherein a relative dielectric constant of said second insulating film and said third insulating film is lower than a relative dielectric constant of said first insulating film. A semiconductor integrated circuit device characterized by the above-mentioned. 4. The semiconductor integrated circuit device according to claim 1, wherein said first insulating film is a silicon nitride film, and said second insulating film and said third insulating film are silicon oxide films. Semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 1, wherein the pillar-shaped electrode in a portion covered with the first insulating film is more than a pillar-shaped electrode in a portion not covered with the first insulating film. A semiconductor integrated circuit device characterized by being thin. 6. The semiconductor integrated circuit device according to claim 1, wherein the first-layer wiring disposed in the direct peripheral circuit portion is the same as a first conductive film connected to a semiconductor substrate and the bit line. A semiconductor integrated circuit device, comprising: a second conductive film formed of a single conductive film, wherein the second conductive film is in contact with an upper sidewall of the first conductive film. 7. A method for manufacturing a semiconductor integrated circuit device having a DRAM having a memory cell having a structure in which a capacitor is formed above a bit line, comprising: (a) one of a semiconductor region of a MISFET for selecting a memory cell; Forming a plug electrode in the first connection hole connecting the bit line;
(B) forming a columnar electrode in a second connection hole connecting the other semiconductor region of the memory cell selecting MISFET to a storage electrode; (c) exposing a side surface on the upper side of the columnar electrode After processing the thinner, covering the exposed portion of the side surface of the columnar electrode with a first insulating film,
(D) forming a groove in the second insulating film above the plug electrode after depositing a second insulating film on the semiconductor substrate, and then forming the bit line in the groove; e)
A step of covering the bit lines with a third insulating film and simultaneously exposing the tops of the columnar electrodes; (f) an information storage capacitor comprising a storage electrode, a dielectric film and a plate electrode in contact with the tops of the columnar electrodes; A method of manufacturing a semiconductor integrated circuit device, comprising: forming an element. 8. A method of manufacturing a semiconductor integrated circuit device having a DRAM having a memory cell having a structure in which a capacitor is formed above a bit line, comprising: (a) one of a semiconductor region of a memory cell selecting MISFET; Forming a plug electrode in the first connection hole connecting the bit line;
(B) After forming a first insulating film on the inner wall of a second connection hole connecting the other semiconductor region of the memory cell selection MISFET and the storage electrode, a columnar electrode is formed in the second connection hole. (C) depositing a second insulating film on the semiconductor substrate, forming a groove in the second insulating film above the plug electrode, and then forming the bit line in the groove. Forming; (d) covering the bit line with a third insulating film and simultaneously exposing the top of the columnar electrode;
(E) forming an information storage capacitance element comprising a storage electrode, a dielectric film, and a plate electrode in contact with the top of the columnar electrode. 9. A method of manufacturing a semiconductor integrated circuit device having a DRAM having a memory cell having a structure in which a capacitor is formed above a bit line, comprising: (a) one semiconductor region of a memory cell selecting MISFET; Forming a plug electrode in the first connection hole connecting the bit line;
(B) forming a columnar electrode in a second connection hole connecting the other semiconductor region of the memory cell selecting MISFET to a storage electrode; (c) exposing a side surface on the upper side of the columnar electrode After processing the thinner, covering the exposed portion of the side surface of the columnar electrode with a first insulating film,
(D) forming a first conductive film directly forming a part of the first layer wiring of the peripheral circuit portion after depositing the second insulating film on the semiconductor substrate and connecting to the semiconductor substrate;
(E) After forming a groove in the second insulating film above the plug electrode and in the second insulating film around the first conductive film in the direct peripheral circuit portion, the bit is formed in the groove. Forming a second conductive film that forms another part of the line and the first layer wiring of the direct peripheral circuit part; (f) covering the bit line with a third insulating film, A semiconductor integrated circuit, comprising: a step of exposing a top of the electrode; and (g) a step of forming a storage element for information storage comprising a storage electrode, a dielectric film and a plate electrode in contact with the top of the columnar electrode. Device manufacturing method. 10. A method of manufacturing a semiconductor integrated circuit device having a DRAM having a memory cell having a structure in which a capacitor is formed above a bit line, comprising: (a) one of a semiconductor region of a memory cell selecting MISFET; Forming a plug electrode in a first connection hole connecting the bit line; and (b) forming a plug electrode in the second connection hole connecting the other semiconductor region of the memory cell selecting MISFET and the storage electrode. Forming a columnar electrode in the second connection hole after forming the first insulating film, and (c) depositing the second insulating film on the semiconductor substrate and then directly forming the first layer of the peripheral circuit portion. Forming a first conductive film that forms a part of an eye wiring and is connected to the semiconductor substrate; and (d) the second insulating film above the plug electrode and the first conductive film of the direct peripheral circuit portion. The first layer around the conductive film After forming a groove in the insulating film, the first bit line and the first peripheral circuit portion of the direct peripheral circuit portion are formed in the groove.
Forming a second conductive film constituting another portion of the wiring of the layer, (e) covering the bit line with a third insulating film,
At the same time, a step of exposing the top of the pillar-shaped electrode, and (f) a step of forming a storage element for storage of information, a dielectric film, and a plate electrode in contact with the top of the pillar-shaped electrode. Of manufacturing a semiconductor integrated circuit device.