JP2769664B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a structure of a portion where an upper wiring layer is electrically connected to a lower wiring layer which is a part of a cell plate, and manufacturing of the structure. It is about the method.

[0002]

2. Description of the Related Art In recent years, the demand for semiconductor storage devices has been rapidly expanding due to the remarkable spread of information devices such as computers. Further, functionally, a memory having a large-scale storage capacity and capable of high-speed operation is required. Along with this, technology development related to high integration and high-speed response or high reliability of semiconductor memory devices is being promoted.

[0003] Of the semiconductor memory devices, DRAMs (Dynamic Random A) are available which can randomly input and output stored information.
ccess Memory). Generally, a DRAM includes a memory cell array, which is a storage area for storing a large amount of storage information, and peripheral circuits necessary for input / output with the outside.

FIG. 34 is a block diagram showing a configuration of a general DRAM. In FIG. 34, a DRAM 1000
Includes a memory cell array 1100 for storing a data signal of storage information, a row and column address buffer 1200 for externally receiving an address signal for selecting a memory cell constituting a unit storage circuit, Row decoder 8300 and column decoder 1 for designating a memory cell by decoding
400, a sense refresh amplifier 1500 for amplifying and reading a signal stored in a designated memory cell, a data-in buffer 1600 and a data-out buffer 1700 for data input / output, and a clock generator 1800 for generating a clock signal. And

A memory cell array 1100 occupying a large area on a semiconductor chip is formed by arranging a plurality of memory cells for storing unit storage information in a matrix. FIG. 35 shows an equivalent circuit diagram of four bits of the memory cells constituting the memory cell array 1100. The illustrated memory cell has one MOS (Metal Ox
1 shows a so-called 1-transistor 1-capacitor type memory cell including a transistor 1900 and one capacitor 2000 connected thereto. Since this type of memory cell has a simple structure, it is easy to improve the degree of integration of the memory cell array, and is widely used in large-capacity DRAMs.

The memory cells of a DRAM can be classified into several types according to the structure of a capacitor. FIG. 36 is a sectional structural view of a memory cell having a typical stacked type capacitor, which is shown in, for example, Japanese Patent Publication No. 60-2784. Referring to FIG. 36, the memory cell includes one transfer gate transistor and one stacked type capacitor (hereinafter, referred to as a stacked type capacitor).

The transfer gate transistor includes source / drain regions 5a and 5b formed on the main surface of silicon substrate 1, and a source / drain region 5a and a source / drain region.
A gate electrode (word line) 7 formed on the main surface of the silicon substrate between the drain region 5b.
The stacked type capacitor is electrically connected to the source / drain region 5b and extends over the field oxide film 3; a dielectric film 11 formed on the surface of the storage node 9; And a cell plate 13 formed on the surface of the cell.

The interlayer insulating film 1 covers the transfer gate transistor and the stacked type capacitor.
7 are formed. The bit line 1 is formed on the interlayer insulating film 17.
5 are formed. A through hole is formed in the interlayer insulating film 17, and the bit line 15 is electrically connected to the source / drain region 5a via the through hole.

The feature of this stacked type capacitor is that, by extending the main part of the capacitor to the upper part of the gate electrode or the upper part of the field oxide film, the facing area between the electrodes of the capacitor is increased to secure the capacitor capacity. That is.

In general, the capacitance of a capacitor is proportional to the area between the electrodes and is inversely proportional to the thickness of the dielectric layer. Therefore, from the viewpoint of increasing the capacitance of the capacitor, it is desirable to increase the area between the electrodes of the capacitor. on the other hand,
With the high integration of DRAMs, the memory cell size has been significantly reduced. Accordingly, the area occupied by the capacitor also tends to be reduced. However, the amount of charge stored in a 1-bit memory cell cannot be reduced from the viewpoint of stable operation and reliability of a DRAM as a storage device. In order to satisfy these conflicting constraints, various improvements have been proposed for the structure of the capacitor, which can reduce the planar occupation area of the capacitor and increase the opposing area between the electrodes.

FIG. 37 is a sectional structural view of a memory cell described in Japanese Patent Application No. 2-89869. The storage node 23 of this memory cell capacitor is
3a, and a vertical wall portion 23b extending vertically above the main surface of the silicon substrate 21. In this capacitor, the standing wall portion 23b makes it possible to increase the capacitance of the capacitor without increasing the planar occupation area of the capacitor.

The structure of the memory cell will be specifically described. Source / drain regions 25a, 25b, 25c are formed on the main surface of silicon substrate 21 with a space therebetween. The base portion 23a is electrically connected to the source / drain region 25c. On the surface of storage node 23, a dielectric film 27 is formed. A cell plate 29 is formed on the surface of the dielectric film 27.

On the main surface of the silicon substrate 21, gate electrodes 31a and 31b are formed with a space therebetween. The gate electrodes 31a and 31b are covered with an insulating film 33. Reference numeral 35 denotes a field oxide film.

An interlayer insulating film 37 is formed on the cell plate 29.
Are formed. A wiring film 39 is formed on the interlayer insulating film 37.
Are formed at intervals. The wiring film 39 is a protective film 41
Covered with. A method for manufacturing this memory cell will be described below.

As shown in FIG. 38, a field oxide film 35 is formed on the main surface of the silicon substrate 21. The field oxide film 35 is formed using the LOCOS method.

Next, as shown in FIG. 39, after forming a gate oxide film 43 by a thermal oxidation method or the like, gate electrodes 31a, 31b, 31c and 31d made of polycrystalline silicon are selectively formed. Further, the insulating film 33 is formed around the gate electrodes 31a to 31d by twice the deposition process of the oxide film and the etching process. Further, impurities are implanted into the main surface of the silicon substrate 21 by ion implantation using the insulating film 33 as a mask, and the source / drain regions 25a,
5b and 25c are formed.

Further, as shown in FIG. 40, a refractory metal film is deposited and patterned into a predetermined shape. Thereby, a bit line 45 electrically connected to the source / drain region 25b is formed. The periphery of the bit line 45 is covered with an insulating film 47.

Further, as shown in FIG. 41, a polycrystalline silicon film 49 is formed on the entire main surface of the silicon substrate 21 by using the CVD method.

Further, as shown in FIG. 42, an insulating film 51 is formed on the polycrystalline silicon film 49.

As shown in FIG. 43, a resist 53 is applied on the surface of the insulating film 51, and is patterned into a predetermined shape by using a lithography method.

As shown in FIG. 44, the insulating film 51 is selectively removed by etching using the resist 53 as a mask.

As shown in FIG. 45, after removing the resist 53, a polycrystalline silicon film 55 is formed by a CVD method.

As shown in FIG. 46, the polycrystalline silicon film 5
A thick resist 57 is applied so that 5 is completely covered. Then, the resist 57 is etched back to expose the polycrystalline silicon film 55 covering the upper surface of the insulating film 51.

As shown in FIG. 47, the exposed polycrystalline silicon film 55 is etched, and subsequently, the insulating layer 51 is removed by self-alignment. Thereby, the polycrystalline silicon film 55 becomes the standing wall portion 23b.

As shown in FIG. 48, only the exposed portion of the polycrystalline silicon film 49 is removed in a self-aligned manner by using anisotropic etching. Thereby, the polycrystalline silicon film 49
Becomes the base portion 23a. After that, the resist 57 is removed.

As shown in FIG. 49, the storage node 2
On the surface of No. 3, a dielectric film 27 made of a silicon nitride film is formed.

As shown in FIG. 50, a cell plate 2 made of a polycrystalline silicon film is formed over the entire main surface of the silicon substrate 21.
9 is formed.

As shown in FIG. 51, an interlayer insulating film 37 is formed on the cell plate 29. Then, as shown in FIG. 37, a wiring film 39 made of aluminum is formed on the interlayer insulating film 37, and the wiring film 39 is covered with a protective film 41. Thus, the manufacture of the memory cell is completed.

[0029]

By the way, in the state shown in FIG. 51, the area other than the memory cell forming area is
In the state shown in FIG. The position indicated by A is a memory cell formation region. In order to electrically connect the cell plate 29 and the upper wiring film, a part of the cell plate 29 extends over the interlayer insulating film 65. A part of the cell plate 29 is called a lower wiring film 30. Gate electrodes 31e and 31f are formed in the memory cell formation region. On the other hand, 63
Is a MOS transistor. MOS transistor 63
Has source / drain regions 61a and 61b. The dielectric film 27 of the capacitor is formed on the entire surface of the silicon substrate 21 as shown in FIG. Incidentally, reference numeral 59 denotes an impurity region. An electrical connection method between the lower wiring film 30 and the wiring film formed in the upper layer will be described below.

As shown in FIG. 53, a resist 69 is applied on the interlayer insulating film 37, and the resist 69 is subjected to a predetermined patterning. Interlayer insulating film 3 using resist 69 as a mask
7, 65 are selectively removed using anisotropic etching to form through holes 67a, 67b, 67c, 67d.

As shown in FIG. 54, the resist 69 is removed, and a tungsten film 71 is formed on the interlayer insulating film 37 by using the CVD method. When the aspect ratio of the through hole (hole depth / opening size of the hole) becomes large, the through hole cannot be completely filled by sputtering, so the CVD method is used. Tungsten film 71 is also formed in the through hole, and is electrically connected to lower wiring film 30, impurity region 59, and source / drain regions 61a and 61b.

The entire surface of the tungsten film 71 is etched using pseudo anisotropic etching with anisotropy: isotropy of 2: 1 to remove the tungsten remaining in the through holes 67a, 67b, 67c and 67d. The step portion (not shown) of the interlayer insulating film 37 uses the pseudo anisotropic etching.
This is to prevent tungsten from remaining on the substrate. Since the thickness of the tungsten film 71 cannot be formed uniformly and the etching rate varies depending on the position of the semiconductor devices arranged on the wafer, the tungsten film 71 on the interlayer insulating film 37 is located in a certain region as shown in FIG. Is removed, the tungsten film 71a may still remain in other regions.

In order to remove the tungsten film 71a remaining on the interlayer insulating film 37, a tungsten film 71
Is etched. By this etching, as shown in FIG. 56, a part of the tungsten film 71 in the through hole 67b is etched away in the through hole 67b. In the shallow through hole 67a, the tungsten film 71 is completely removed by etching.
Further, a part of the lower wiring film 30 is also etched. FIG. 57 shows a state in which an aluminum film is formed on the interlayer insulating film 37 by using sputtering in this state and predetermined patterning is performed. As can be seen from FIG. 57, the electrical connection between the lower wiring film 30 and the wiring film 39 formed in the through hole 67a is defective.

The present invention has been made to solve such a conventional problem. An object of the present invention is to provide a semiconductor memory device capable of ensuring electrical connection between an upper wiring layer and a lower wiring layer which is a part of a cell plate.

Another object of the present invention is to provide a method of manufacturing a semiconductor memory device capable of ensuring electrical connection between an upper wiring layer and a lower wiring layer which is a part of a cell plate.

[0036]

According to a first aspect of the present invention, a semiconductor substrate having a main surface, an impurity region formed on the main surface, and an impurity region are formed so as to be electrically connected to the impurity region. A memory in which a memory cell including a storage node having a portion extending upward with respect to the surface, a dielectric layer formed on the surface of the storage node, and a cell plate formed on the surface of the dielectric layer is formed. A cell formation region is provided. According to a first aspect of the present invention, a first interlayer insulating layer formed on a main surface and at a position separated from a memory cell formation region;
Between the lower wiring layer, which is formed below the upper surface of the first interlayer insulating layer and is a part of the cell plate, between the interlayer insulating layer and the memory cell forming region and the first interlayer insulating layer; A second interlayer insulating layer formed and having a through hole exposing the lower wiring layer; an upper wiring layer formed on the second interlayer insulating layer and electrically connected to the lower wiring layer via the through hole; It has.

A second aspect of the present invention is a method for manufacturing a semiconductor memory device. According to a second aspect of the present invention, a step of forming a first interlayer insulating layer on a main surface of a semiconductor substrate having a memory cell formation region on the main surface and at a position distant from the memory cell formation region; Forming a storage node having a portion extending upward with respect to the main surface on the formation region, forming a dielectric layer on the surface of the storage node, and forming a cell plate on the surface of the dielectric layer Forming a lower wiring layer, which is a part of the cell plate, in a region between the memory cell formation region and the first interlayer insulating layer and below the upper surface of the first interlayer insulating layer; Forming a second interlayer insulating layer on the main surface;
Selectively removing the interlayer insulating layer by etching to form a through hole reaching the lower wiring layer in a region between the memory cell forming region and the first interlayer insulating layer; Forming a conductive layer on the second interlayer insulating layer, etching the conductive layer while leaving the conductive layer in the through-hole,
Forming an upper wiring layer electrically connected to the conductive layer in the through hole.

[0038]

The electrical connection between the cell plate and the upper wiring layer is achieved by electrically connecting the lower wiring layer and the upper wiring layer which are part of the cell plate.

According to a first aspect of the present invention, a lower wiring layer is formed between a memory cell forming region and a first interlayer insulating layer and below an upper surface of the first interlayer insulating layer. Then, a through hole used for electrically connecting the lower wiring layer and the upper wiring layer is formed between the memory cell forming region and the first interlayer insulating layer. For this reason, the depth of the through hole can be increased as compared with the case where the through hole is formed on the first interlayer insulating layer. Since the depth of the through hole is large, the thickness of the conductive layer formed in the through hole becomes large. Therefore, at the time of over-etching, the conductive layer in the through hole is completely removed, and the lower wiring layer is not further cut off. Therefore, the electrical connection between the upper wiring layer and the lower wiring layer can be made well.

According to a second aspect of the present invention, a lower wiring layer, which is a part of a cell plate, is provided in a region between a memory cell forming region and a first interlayer insulating layer, the upper surface of the first interlayer insulating layer. It is formed at a lower position. Then, the second interlayer insulation formed on the main surface of the semiconductor substrate is selectively removed by etching, and a through hole reaching the lower wiring layer between the memory cell formation region and the first interlayer insulation layer is formed. Has formed. For this reason, the depth of the through hole is larger than in the case where the through hole is formed on the first interlayer insulating layer.

[0041]

FIG. 1 is a sectional view of a first embodiment of the present invention. The portion indicated by A indicates a memory cell formation region. A portion indicated by B indicates a peripheral circuit formation region located at a position distant from the memory cell formation region. The description starts with the memory cell formation region.

On the silicon substrate 81, source / drain regions 83a, 83b, 83c are formed with a space therebetween. 89a and 89b are gate electrodes (word lines).
The gate electrodes 89a and 89b are covered with an insulating film 88. A bit line 87 is electrically connected to the source / drain region 83b. The bit line 87 is covered with an insulating film 92.

The base portion 85a of the storage node 85 is electrically connected to the source / drain region 83c. The standing wall portion 85b is electrically connected to the base portion 85a. On the surface of storage node 85, a dielectric film 90 is formed. A cell plate 91 is formed on the surface of the dielectric film 90. 89c is a word line.

Part of the cell plate 91 is formed up to the field oxide film 107a, and further extends to the upper surface portion 123a of the silicon oxide film 123 as the first interlayer insulating layer. In the cell plate 91, the field oxide film 10
The film formed on 7a and the silicon oxide film 123 is referred to as a lower wiring film 109. The lower wiring film 109 is made concave by the standing wall portion 85b and the silicon oxide film 123.

Cell plate 91 and lower wiring film 109
A silicon oxide film 93 serving as a second interlayer insulating layer is formed thereon. The silicon oxide film 93 has a lower wiring film 10
9, a through hole 95 a is formed to reach a portion closest to the main surface 111 of the silicon substrate 81.
That is, the through hole 95a reaches the concave bottom. The depth of the through hole 95a is 5000 ° or more.
The through hole 95a is partially formed with the tungsten film 101a.
And the rest is buried with an upper wiring film 103a made of aluminum. Reference numeral 103 denotes an upper wiring film made of aluminum.

An impurity region 97 is formed in silicon substrate 81 between field oxide film 107a and field oxide film 107b. Silicon oxide films 93 and 123
Is formed with a through hole 95b reaching impurity region 97. The through hole 95b is partially filled with the tungsten film 101b, and the rest is filled with the upper wiring film 103b made of aluminum. The upper wiring films 103, 103a, 103b are covered with a protective film 105.

Next, the peripheral circuit formation region indicated by B will be described. 83d is one source / drain region of the MOS transistor. 89d is a gate electrode, and 88 is an insulating film covering the gate electrode 89d. Source / drain regions 83 are formed in silicon oxide films 93 and 123.
A through hole 95c reaching d is formed. The through hole 95c is buried with the tungsten film 101c. The upper wiring film 103c made of aluminum is electrically connected to the tungsten film 101c. The upper wiring film 103c is covered with a protective film 105.

Next, the manufacturing method of the first embodiment of the present invention shown in FIG. 1 will be described below. As shown in FIG. 2, first, gate electrodes (word lines) 89a, 89a, 8a
9b, word lines 89c, and gate electrodes 89d were formed.
The gate electrode and the word line were covered with an insulating film 88 made of a silicon oxide film. Next, using the insulating film 88 as a mask,
Ions are implanted into the silicon substrate 81 to form source / drain regions 83a, 83b, 83c, 83d and impurity regions 9
7 was formed. Thereafter, a bit line 87 electrically connected to the source / drain region 83b is formed, and the bit line 87 is formed.
Was covered with an insulating film 92 made of a silicon oxide film.

As shown in FIG. 3, a silicon nitride film 113 was formed on the entire main surface of the silicon substrate 81 by using the CVD method. Instead of the silicon nitride film, a structure in which a silicon nitride film is laminated on a silicon oxide film may be used.

As shown in FIG. 4, a resist 115 was applied to the entire main surface of the silicon substrate 81. Resist 11
5 is selectively exposed, so that the source / drain regions 83a, 83
The resist 115 on 3c was selectively removed.

As shown in FIG. 5, using the resist 115 as a mask, the silicon nitride film 113 was selectively removed by reactive ion etching. Due to the anisotropic etching, the silicon nitride film 113 remains on the side wall of the insulating film 88.

As shown in FIG. 6, a polycrystalline silicon film 119 is formed on the entire main surface of silicon substrate 81 by CVD.
Was formed. A silicon oxide film 117 was formed on the polycrystalline silicon film 119 by using a CVD method. Using a normal photolithography technique and an etching technique, the silicon oxide film 117 in the other area was removed while leaving only the silicon oxide film 117 on the memory cell formation area.

As shown in FIG. 6, a silicon oxide film 117 is formed.
Is used as a mask to remove the polycrystalline silicon film 119 by etching, and the silicon oxide film 117 is removed. In this case, a resist may be provided instead of the silicon oxide film 117, and the polycrystalline silicon film 119 may be removed by etching using the resist as a mask. FIG. 7 shows this state. When the polycrystalline silicon film 119 is etched by the silicon nitride film 113, the impurity region 97, the source / drain region 83
d is prevented from being etched.

As shown in FIG. 8, a silicon oxide film 123 was formed on the entire main surface of the silicon substrate 81 by using the CVD method. A resist 121 was applied on the silicon oxide film 123, and the resist 121 was subjected to predetermined patterning.

As shown in FIG. 9, the resist 121 is used as a mask to cover the bit line 87 and the field oxide film 10.
The silicon oxide film 123 on 7a was selectively removed by etching. The polycrystalline silicon film 119 on the field oxide film 107a prevents the field oxide film 107a from being etched. That is, since the difference in etching rate between the silicon nitride film 113 and the silicon oxide film 123 is small, the silicon nitride film 113 is unlikely to serve as an etching stopper. Therefore, the polycrystalline silicon film 119 is used as an etching stopper. Since the polycrystalline silicon film 119 is used as an etching stopper, the silicon oxide film 123 is
9 is mounted on the end 119a.

Then, as shown in FIG.
Was removed. As shown in FIG.
3 was used as a mask to selectively remove the polycrystalline silicon film 119 by etching. Source / drain regions 83a, 83
The polycrystalline silicon film 119 electrically connected to c is hereinafter referred to as a base portion 85a. The silicon oxide film 123 is formed to reduce the level difference between the memory cell formation region and other regions, but is also used as a mask for etching and removing the polycrystalline silicon film 119.

As shown in FIG. 12, a polycrystalline silicon film 12 is formed on the entire main surface of a silicon substrate 81 by CVD.
5 was formed.

As shown in FIG. 13, a resist 127 was applied to the entire main surface of the silicon substrate 81. Then, the resist 127 on the memory cell formation region was removed.

As shown in FIG. 14, the polycrystalline silicon film 125 was selectively etched away using reactive ion etching with the resist 127 as a mask. Thereby, the silicon oxide film 1 is formed on the field oxide film 107a.
Polycrystalline silicon film 1 on bit 23 and bit line 87
25 were removed. Since anisotropic etching is used, the polycrystalline silicon film 125 formed on the side wall of the silicon oxide film 123 is not removed. The polycrystalline silicon film 125 remaining on the side wall of the silicon oxide film 123 is hereinafter referred to as a standing wall portion 85b.

As shown in FIG. 15, the silicon oxide film 123 was removed by etching in a self-aligned manner. Resist 127
Was removed.

As shown in FIG. 16, a resist 129 was applied on the entire main surface of the silicon substrate 81. The resist 129 in the other area was removed while leaving the resist 129 on the memory cell formation area.

As shown in FIG. 17, the polysilicon film 125 was removed by etching using the resist 129 as a mask. As shown in FIG. 16, this etching uses pseudo anisotropic etching to remove the polycrystalline silicon 125a formed on the side wall of the silicon oxide film 123. Therefore, a part of the polycrystalline silicon film 119a is etched as shown in FIG. Note that since the polycrystalline silicon film 119a is useless, the isotropic element may be strengthened and all may be removed by etching.

As shown in FIG. 18, the resist 129 was removed. As shown in FIG. 19, a dielectric film 90 is formed on a main surface of a silicon substrate 81 by using a normal method. Further, a polycrystalline silicon film 92a is formed on the dielectric film 90 by using the CVD method, and predetermined patterning is performed by using a resist 94. Thus, a cell plate 91 and a lower wiring film 109 are formed as shown in FIG. Part of the lower wiring film 109 is formed on the upper surface 1 of the silicon oxide film 123.
23a.

The lower wiring film 109 is replaced with a silicon oxide film 123
Since the through hole is formed in the region indicated by E, the lower wiring film 109 is formed on the silicon oxide film 12.
3 to ensure that the lower wiring film 109 exists in the region indicated by E. However, the effect of the present invention can be achieved without forming the lower wiring film 109 up to the silicon oxide film 123. The length of the region indicated by E, that is, the length of the bottom of the concave portion is 1.0 μm or more and 3.0
μm or less is preferred.

As shown in FIG. 21, a silicon oxide film 93 was formed on the entire main surface of the silicon substrate 81 by using the CVD method.

As shown in FIG. 22, a silicon oxide film 93, 1
23 is selectively removed by etching to form a through hole 95.
a, 95b and 95c were formed. Through hole 95a
Has reached the portion of the lower wiring film 109 closest to the main surface of the silicon substrate 81, that is, the concave bottom.

As shown in FIG. 23, a tungsten film 101 was formed on the entire main surface of a silicon substrate 81 by using a CVD method.

As shown in FIG. 24, a silicon oxide film 93 is formed.
The tungsten film 101 on the entire surface was removed by etching. The etching rate and the tungsten film thickness vary depending on the positions of the semiconductor devices arranged on the wafer. In this embodiment, in the peripheral circuit formation region B, the tungsten film 101 on the silicon oxide film 93 has not been completely removed yet. The tungsten film buried in the through hole 95a is called a tungsten film 101a.
Similarly, the tungsten film buried in the through hole 95b is called a tungsten film 101b.

As shown in FIG. 25, a silicon oxide film 93 is formed.
Etching was further continued to remove the tungsten film 101 remaining on the upper surface. Conventionally, a through hole reaching the lower wiring film 109 has been formed on the silicon oxide film 123. Therefore, the depth of the through hole is shallow, and the tungsten film in the through hole may be removed by this over-etching, and a part of the lower wiring film 109 may be removed. In the first embodiment, such a phenomenon did not occur because the depth of the through hole 95a was large.

As shown in FIG. 26, a silicon oxide film 93 is formed.
An aluminum film was formed thereon using a sputtering method. Then, predetermined patterning is performed on the aluminum film to form upper wiring films 103, 103a, 103b, and 103c.
Was formed. Then, as shown in FIG.
A protective film 105 was formed so as to cover 3, 103a, 103b, and 103c. Thus, the manufacturing method according to the first embodiment of the present invention has been completed.

(Second Embodiment) FIG. 2 described in the first embodiment
Through the steps shown in FIGS. Then, a dielectric film 90 is formed on the main surface of the silicon substrate 81 as shown in FIG. A polycrystalline silicon film 92a is formed on dielectric film 90 using a CVD method. A resist 94 is formed on the polycrystalline silicon film 92a. Resist 94 after exposure and development
Exposure and development of the resist 94 is performed so that the side surface portion 94a of the resist 94 is located in the region indicated by E.

The polycrystalline silicon film 92a and the dielectric film 90 are sequentially etched and removed using anisotropic etching with the resist 94 as a mask, and a cell plate 91 is formed as shown in FIG. Since the anisotropic etching is used, the polycrystalline silicon film 92a and the dielectric film 90 remain on the side surface 123b of the silicon oxide film 123. After the steps shown in FIGS. 20 to 25 described in the first embodiment, the second embodiment of the present invention is completed as shown in FIG.

In the first embodiment, the end of the lower wiring film 109 extends over the upper surface portion 123a of the silicon oxide film 123, but in the second embodiment, the end of the lower wiring film 109 is formed on the side surface of the silicon oxide film 123. It is before the part 123b.

(Third Embodiment) FIG. 2 described in the first embodiment
Through the steps shown in FIGS. Then, a dielectric film 90 is formed on the main surface of the silicon substrate 81 as shown in FIG. A polycrystalline silicon film 92a is formed on dielectric film 90 using a CVD method. A resist 94 is formed on the polycrystalline silicon film 92a. Exposure and development of the resist 94 are performed so that the side surface portion 94a of the resist 94 after exposure and development is located in a region indicated by E.

Using the resist 94 as a mask, the polycrystalline silicon film 92a and the dielectric film 90 are etched and removed in order using isotropic etching to form a cell plate 91 as shown in FIG. Since the isotropic etching is used, the dielectric film 9 is formed on the side surface 123b of the silicon oxide film 123.
0, the polycrystalline silicon film 92a does not remain. Then, after the steps shown in FIGS. 20 to 25 described in the first embodiment, the third embodiment of the present invention is completed as shown in FIG.

In the second embodiment shown in FIG.
b, the dielectric film 90 and the polycrystalline silicon film 92a remain. Since the dielectric film 90 and the polycrystalline silicon film 92a on the side surface portion 123b may peel off and become dust, the dielectric film 90 and the polycrystalline silicon film 92 on the side surface portion 123b may be formed.
It is preferable that a does not remain. In the third embodiment, isotropic etching is used as shown in FIG.
Dielectric film 90 and polycrystalline silicon film 92a do not remain on 23b.

As shown in FIG. 32, through holes 95a
In order to ensure that the lower wiring film 109 is located on the lower wiring film 109, the lower wiring film 109 must be longer than a predetermined length. Since the isotropic etching is used in the third embodiment, the side etching proceeds as shown in FIG. 31, and the end of the lower wiring film 109 is located inside the side surface portion 94a of the resist 94. Considering such side etching, as shown in FIG. 30, the design value L of the length of the lower wiring film 109 is obtained.
Therefore, it is necessary to perform exposure and development of the resist 94 so that the length of the resist 94 after exposure and development is increased. Since the length of the resist 94 after the exposure and development is increased, the distance indicated by E must be increased as compared with the second embodiment. Therefore, in terms of miniaturization, the second embodiment in which the distance indicated by E can be reduced is more advantageous.

(Fourth Embodiment) FIG. 33 is a sectional view of a fourth embodiment of the present invention. The same components as those in the first embodiment shown in FIG. The first embodiment differs from the first embodiment shown in FIG. 1 in that a field oxide film 107a is located below a through hole 95a. As shown in FIG. 33, in the fourth embodiment, no field oxide film exists under the through hole 95a.

[0079]

According to a first aspect of the present invention, a through hole used for electrically connecting a lower wiring layer and an upper wiring layer is formed between a memory cell forming region and a first interlayer insulating layer. ing. For this reason, the depth of the through hole can be increased as compared with the case where the through hole is formed on the first interlayer insulating layer. Therefore, the conductive layer in the through hole is entirely removed at the time of over-etching, and the lower conductive layer is not further removed. Therefore, the electrical connection between the upper wiring layer and the lower wiring layer can be made well.

According to a second aspect of the present invention, a lower wiring layer, which is a part of a cell plate, is provided in a region between a memory cell forming region and a first interlayer insulating layer, and a top surface portion of the first interlayer insulating layer is provided. It is formed at a lower position. Then, the second interlayer insulating layer formed on the main surface of the semiconductor substrate is selectively etched away, and a through hole reaching the lower wiring layer between the memory cell forming region and the first interlayer insulating layer. Is formed. For this reason, the depth of the through hole is larger than in the case where the through hole is formed on the first interlayer insulating layer.
Therefore, at the time of over-etching, the conductive layer in the through hole is completely removed, and the lower wiring layer is not further cut off. Therefore, the electrical connection between the upper wiring layer and the lower wiring layer can be made well.

[Brief description of the drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention.

FIG. 2 is a sectional view of the silicon substrate showing a first step of the manufacturing method according to the first embodiment of the present invention.

FIG. 3 is a sectional view of the silicon substrate showing a second step of the manufacturing method according to the first embodiment of the present invention.

FIG. 4 is a sectional view of the silicon substrate showing a third step of the manufacturing method according to the first embodiment of the present invention.

FIG. 5 is a sectional view of the silicon substrate showing a fourth step of the manufacturing method according to the first embodiment of the present invention.

FIG. 6 is a sectional view of the silicon substrate showing a fifth step of the manufacturing method according to the first embodiment of the present invention.

FIG. 7 is a sectional view of the silicon substrate showing a sixth step of the manufacturing method according to the first embodiment of the present invention.

FIG. 8 is a sectional view of the silicon substrate showing a seventh step of the manufacturing method according to the first embodiment of the present invention.

FIG. 9 is a sectional view of the silicon substrate showing an eighth step of the manufacturing method according to the first embodiment of the present invention.

FIG. 10 is a sectional view of the silicon substrate showing a ninth step of the manufacturing method according to the first embodiment of the present invention.

FIG. 11 is a sectional view of the silicon substrate showing a tenth step of the manufacturing method according to the first embodiment of the present invention.

FIG. 12 is a sectional view of the silicon substrate showing an eleventh step of the manufacturing method according to the first embodiment of the present invention.

FIG. 13 is a sectional view of the silicon substrate showing a twelfth step of the manufacturing method according to the first embodiment of the present invention.

FIG. 14 is a sectional view of the silicon substrate showing a thirteenth step of the manufacturing method according to the first embodiment of the present invention.

FIG. 15 is a sectional view of the silicon substrate showing a fourteenth step of the manufacturing method according to the first embodiment of the present invention;

FIG. 16 is a sectional view of the silicon substrate showing a fifteenth step of the manufacturing method according to the first embodiment of the present invention;

FIG. 17 is a sectional view of the silicon substrate showing a sixteenth step of the manufacturing method according to the first embodiment of the present invention.

FIG. 18 is a sectional view of the silicon substrate showing a seventeenth step of the manufacturing method according to the first embodiment of the present invention.

FIG. 19 is a sectional view of the silicon substrate showing an eighteenth step of the manufacturing method according to the first embodiment of the present invention.

FIG. 20 is a sectional view of the silicon substrate showing a nineteenth step of the manufacturing method according to the first embodiment of the present invention;

FIG. 21 is a sectional view of the silicon substrate showing a twentieth step of the manufacturing method according to the first embodiment of the present invention.

FIG. 22 is a sectional view of the silicon substrate showing a twenty-first step of the manufacturing method according to the first embodiment of the present invention.

FIG. 23 is a sectional view of the silicon substrate showing the 22nd step of the manufacturing method according to the first embodiment of the present invention;

FIG. 24 is a sectional view of the silicon substrate showing a 23rd step of the manufacturing method according to the first embodiment of the present invention;

FIG. 25 is a sectional view of the silicon substrate showing a 24th step of the manufacturing method according to the first embodiment of the present invention;

FIG. 26 is a sectional view of the silicon substrate showing a 25th step of the manufacturing method according to the first embodiment of the present invention;

FIG. 27 is a cross-sectional view of a silicon substrate showing a first step in a manufacturing method according to the second embodiment of the present invention.

FIG. 28 is a sectional view of the silicon substrate showing a second step in the manufacturing method according to the second embodiment of the present invention;

FIG. 29 is a sectional view of the silicon substrate showing a third step of the manufacturing method according to the second embodiment of the present invention.

FIG. 30 is a sectional view of a silicon substrate showing a first step in a manufacturing method according to a third embodiment of the present invention.

FIG. 31 is a cross sectional view of a silicon substrate showing a second step of the manufacturing method according to the third embodiment of the present invention.

FIG. 32 is a sectional view of the silicon substrate showing a third step in the manufacturing method according to the third embodiment of the present invention.

FIG. 33 is a sectional view of a fourth embodiment of the present invention.

FIG. 34 is a block diagram of a conventional DRAM.

FIG. 35 is an equivalent circuit diagram of a conventional memory cell.

FIG. 36 is a sectional structural view of a memory cell including a conventional stacked capacitor.

FIG. 37 is a sectional structural view of a memory cell provided with another conventional type of stacked capacitor.

FIG. 38 is a sectional view of the silicon substrate showing the first step of the method for manufacturing the capacitor shown in FIG. 37.

39 is a sectional view of the silicon substrate showing a second step of the method for manufacturing the capacitor shown in FIG. 37.

40 is a sectional view of the silicon substrate showing a third step of the method for manufacturing the capacitor shown in FIG. 37.

FIG. 41 is a sectional view of the silicon substrate showing a fourth step of the method for manufacturing the capacitor shown in FIG. 37.

42 is a sectional view of the silicon substrate showing a fifth step of the method for manufacturing the capacitor shown in FIG. 37.

FIG. 43 is a sectional view of the silicon substrate showing the sixth step of the method for manufacturing the capacitor shown in FIG. 37.

FIG. 44 is a sectional view of the silicon substrate showing the seventh step of the method for manufacturing the capacitor shown in FIG. 37.

FIG. 45 is a sectional view of the silicon substrate showing the eighth step of the method for manufacturing the capacitor shown in FIG. 37.

46 is a cross-sectional view of the silicon substrate showing a ninth step of the method for manufacturing the capacitor shown in FIG. 37.

FIG. 47 is a tenth method of manufacturing the capacitor shown in FIG. 37;
It is sectional drawing of the silicon substrate which shows a process.

FIG. 48 is an eleventh method of manufacturing the capacitor shown in FIG. 37;
It is sectional drawing of the silicon substrate which shows a process.

FIG. 49 is a twelfth method of manufacturing the capacitor shown in FIG. 37;
It is sectional drawing of the silicon substrate which shows a process.

50 is a thirteenth method of manufacturing the capacitor shown in FIG.
It is sectional drawing of the silicon substrate which shows a process.

FIG. 51 is a fourteenth method of manufacturing the capacitor shown in FIG. 37;
It is sectional drawing of the silicon substrate which shows a process.

FIG. 52 is a cross-sectional view of the silicon substrate showing a first step for making electrical connection between the lower wiring layer and the upper wiring layer.

FIG. 53 is a cross sectional view of the silicon substrate showing a second step for making electrical connection between the lower wiring layer and the upper wiring layer.

FIG. 54 is a cross-sectional view of the silicon substrate showing a third step for making electrical connection between the lower wiring layer and the upper wiring layer.

FIG. 55 is a cross sectional view of the silicon substrate showing a fourth step for making electrical connection between the lower wiring layer and the upper wiring layer.

FIG. 56 is a cross sectional view of the silicon substrate showing a fifth step for making electrical connection between the lower wiring layer and the upper wiring layer.

FIG. 57 is a cross sectional view of the silicon substrate showing a sixth step for making electrical connection between the lower wiring layer and the upper wiring layer.

[Explanation of symbols]

 Reference Signs List 81 silicon substrate 83c source / drain region 85 storage node 91 cell plate 93 silicon oxide film 95a through hole 101a tungsten film 103a upper wiring film 107a field oxide film 109 lower wiring film 111 main surface

Continuation of the front page (56) References JP-A-4-30465 (JP, A) JP-A-5-299599 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27 / 10 H01L 21/768

Claims (2)

(57) [Claims] A semiconductor substrate having a main surface; an impurity region formed on the main surface; and a portion formed to be electrically connected to the impurity region and extending upward with respect to the main surface. A memory cell forming area including a storage node having a memory cell, a dielectric layer formed on the surface of the storage node, and a cell plate formed on the surface of the dielectric layer; A first interlayer insulating layer formed above and apart from the memory cell forming region; and a first interlayer insulating layer between the memory cell forming region and the first interlayer insulating layer, A lower wiring layer formed below the upper surface of the layer and being a part of the cell plate; and a through-hole formed between the memory cell forming region and the first interlayer insulating layer to expose the lower wiring layer. hole A semiconductor memory device comprising: a second interlayer insulating layer having: and an upper wiring layer formed on the second interlayer insulating layer and electrically connected to the lower wiring layer via the through hole. 2. forming a first interlayer insulating layer on the main surface of the semiconductor substrate having a memory cell formation region on the main surface and at a position separated from the memory cell formation region; Forming, on a region, a storage node having a portion extending upward with respect to the main surface; forming a dielectric layer on the surface of the storage node; and forming a cell plate on the surface of the dielectric layer. Forming a lower wiring, which is a part of the cell plate in a region between the memory cell forming region and the first interlayer insulating layer and below a top surface of the first interlayer insulating layer Forming a layer, forming a second interlayer insulating layer on the main surface, selectively removing the second interlayer insulating layer by etching, and forming the memory cell forming region and the first interlayer insulating layer Between Forming a through hole reaching the lower wiring layer; forming a conductive layer on the second interlayer insulating layer so as to fill the through hole; and leaving the conductive layer in the through hole. Etching the conductive layer, and forming an upper wiring layer electrically connected to the conductive layer in the through hole on the second interlayer insulating layer. Device manufacturing method.