JP2790110B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a capacitor electrode of a semiconductor device.

[0002]

2. Description of the Related Art Among semiconductor memory devices, there is a DRAM that can arbitrarily input and output stored information. Here, the memory cell of the DRAM, which includes one transfer transistor and one capacitor, is widely used as being simple in structure and most suitable for high integration of semiconductors. .

As such a memory cell capacitor, one having a three-dimensional structure has been developed and used with further higher integration of semiconductor devices. The three-dimensional structure of the capacitor is based on the following reasons. 2. Description of the Related Art Along with miniaturization and higher density of semiconductor elements, it is necessary to reduce the area occupied by capacitors. However, in order to ensure stable operation and reliability of the DRAM, a capacitance value equal to or more than a certain value is required. Therefore, it is necessary to increase the surface area of the capacitor electrode within the reduced occupied area by changing the electrode of the capacitor from a planar structure to a three-dimensional structure.

The three-dimensional capacitor of the DRAM memory cell includes a stacked structure and a trench structure. Each of these structures has advantages and disadvantages, but the stacked structure has a high resistance to the incidence of alpha rays or noise from circuits and the like, and operates stably even when the capacitance is relatively small. For this reason, 1 gigabit D, which is a design standard of a semiconductor element of about 0.15 μm.
It is considered that a capacitor having a stacked structure is also effective in a RAM. However, for a capacitor having a simple stack structure, about 0.8 for a 256 Mbit DRAM
It is predicted that an electrode height exceeding 1.2 μm is required for a μm and 1 gigabit DRAM, which is not realistic. This is because a large step easily causes disconnection of the wiring, and there is a limit to the depth of field in the lithography technology, and there is a strong demand for suppression of the electrode height.

Therefore, a structure called a cylinder type has attracted attention as a kind of the capacitor having the stacked structure (hereinafter, referred to as a stacked capacitor). For example, JP-A-5-136371 and JP-A-6-29
No. 463 proposes to increase the surface area by making the lower electrode of the capacitor a cylinder structure.

A method of forming a lower electrode of a conventional cylinder type capacitor will be described below with reference to the drawings.

[0007] As schematically shown in FIG.
A field oxide film 2 as an element isolation insulating film is formed on the surface of a silicon substrate 1 of a mold type. Then, a gate electrode 3 (also serving as a word line) of the transistor of the memory cell, a diffusion layer 4 for a capacity and a diffusion layer 5 for a bit line to be N ⁺ -type source / drain regions are formed. Next, an interlayer insulating film 6-1 covering the gate electrode (word line) 3 is formed of a silicon oxide film or the like, and a bit line contact plug 9 is formed in the bit line diffusion layer region 5. Then, a bit line 8 electrically connected to the bit line contact plug 9 is provided, and an interlayer insulating film 6-2 is formed so as to cover the bit line.
Is deposited.

Next, a stopper film 7 laminated on the interlayer insulating film 6-2 is formed. Here, the stopper film 7 is formed of a silicon nitride film.

Next, a contact hole 10 is opened on the above-mentioned capacitance diffusion layer 4 and a first silicon film 11 which becomes a part of an information storage electrode (lower electrode) of the capacitor is formed by a known CVD method.
Then, the spacer film 12 is formed. Here, as the spacer film 12, a silicon oxide film formed by a known CVD method is used. This is so that a selective ratio between the stopper film 7 and the etching can be obtained in a later step of removing the spacer film 12.

Next, using a known lithography technique, a photoresist is applied, exposed, developed, and patterned into a desired shape to form a photoresist film 13.

Next, as shown in FIG.
Anisotropic dry etching is performed using an already patterned photoresist film 13 as a mask by using an IE (reactive ion etching) technique or the like, and the spacer film 12 and the first silicon film 11 are patterned together. . This includes a spacer film 12 made of silicon oxide.
Is etched using a mixed gas mainly composed of CF ₄ and CHF ₃ , and then the first silicon film 11 is etched by switching the gas system to a mixed gas mainly composed of Cl ₂ and HBr. When the spacer film 12 is etched, an attachment 14 made of a fluorocarbon polymer is simultaneously deposited on the opening side wall of the spacer film 12 with the progress of the etching, and the progress of the etching from the side wall is prevented. It becomes possible. The thickness of the attachment 14 is 1
In order to etch the first silicon film 11 to a size including the attachment 14, the spacer film 12a
And the first silicon film 11a have a dimensional difference.

Next, as shown in FIG. 7A, the photoresist film is removed. However, in the step of removing these photoresist films, not only the photoresist film but also the first silicon film 11a is etched by 1 to 2 nm and the spacer film 12a is etched by 10 to 30 nm, respectively. The dimensional difference of the silicon film 11b is further enlarged.

Next, as shown in FIG. 7B, a second silicon film 15 is formed by a CVD method.

Next, as shown in FIG. 8A, anisotropic dry etching is performed using a known RIE (reactive ion etching) technique or the like, and the patterned spacers 12b and the first spacers 12b are formed. The second silicon film 15a is left in a sidewall shape around the silicon film 11b. For the etching, a mixed gas containing Cl ₂ and HBr as main components is used.

Next, as shown in FIG. 8B, the spacers 12b are selectively removed with a hydrogen fluoride solution.

Next, impurities such as arsenic and phosphorus are introduced into the first silicon film 11b and the second silicon film 15b to improve the conductivity, thereby improving the information storage electrode of the capacitor (with the pedestal (11b)). The formation of the lower electrode composed of the side wall (15b) is completed. Next, a dielectric film (not shown) is formed, a counter electrode is formed, and a capacitor is formed.

[0017]

However, in the prior art, the first silicon film 11 is patterned after the spacer film 12a is patterned and before the photoresist film 13 and the attachment 14 are removed. As shown in (b), the spacer film 12a and the first silicon film 11a
The spacer film 12b and the first silicon film 11 are further removed in a subsequent step of removing the photoresist film 13 or the like.
The dimensional difference of b becomes large.

If this dimensional difference b (FIG. 8B) is large,
There is a problem in that the mechanical strength of the portion A surrounded by the two-dot chain line circle becomes insufficient, and the portion A is broken in the cleaning process, thereby causing a reduction in yield.

In order to avoid this, if the thickness c of the second silicon film 15 is increased, the distance d between the adjacent information storage electrodes is reduced, which in turn causes a short circuit at the portion B.
Again, yield is reduced.

Therefore, it is conceivable to increase the thickness d of the second silicon film 15 and increase the distance d between the adjacent information storage electrodes. However, the pitch a + e of the information storage electrodes is kept constant in design. E must be reduced because of the relationship a = 2c + d. Then, the information storage electrode becomes smaller as a whole, and the surface area cannot be effectively increased.

Further, in order to suppress the dimensional difference b between the spacer 12b and the first silicon film 11b (the pedestal portion of the lower electrode), a stopper film having a small etching amount in the photoresist film removing step and the cleaning step is used. In addition, it must be used as a spacer film, which limits the choice of materials.

For example, as shown in FIG. 9, it is known that a good flow shape can be obtained in a step portion of a BPSG film by heat treatment at 800 ° C. or more. This has the advantage that silicon residue, which is likely to occur in the above, can be prevented. If a good flow shape cannot be obtained at the stepped portion other than the memory cell region, for example, at the peripheral circuit portion, as shown in FIG. At the same time, the silicon minute pieces 15c are simultaneously peeled off, causing particles to be generated. Since this directly leads to deterioration of the yield, the use of the BPSG film for the spacer film is effective for improving the yield.

However, the BPSG film has a large etching amount in the photoresist film removing step and the cleaning step, and further increases the dimensional difference b between the spacer film and the first silicon film.
The prior art has been difficult to use.

A first object of the present invention is to suppress the dimensional difference between the spacer film and the pedestal portion of the lower electrode so as to prevent shortage of mechanical strength and to increase the capacitance value effectively and at a high yield. An object of the present invention is to provide a method for manufacturing a semiconductor device having a cylindrical capacitor that can be manufactured.

Further, a second object of the present invention is to make it possible to use a material which has been difficult to use in the prior art due to a large etching amount in a photoresist removing step and a cleaning step, and a spacer film and a stopper film. It is an object of the present invention to provide a method of manufacturing a semiconductor device having a cylinder-type capacitor, which allows a higher degree of freedom in material selection and enables a process design with a higher yield.

[0026]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: depositing a silicon nitride film on a semiconductor substrate having a MOS transistor formed thereon;
A step of forming a contact hole penetrating the silicon nitride film and reaching the semiconductor substrate; and forming a first conductive film covering the silicon nitride film by filling the contact hole and then comprising a BPSG film or a PSG film. Insulation
Depositing a film, after forming the insulating film, heat treatment
And insulating the contact hole above the contact hole.
The resist selectively forming a resist film, the resist film with the progress of etching to selectively remove the first conductive film by reactive ion etching said insulating film as a mask covering the film A step of using a means for performing a first anisotropic etching while attaching a reaction product to the film and the side wall of the insulating film for the etched portion, and removing the resist film and the attached matter, Etching the first conductive film by using a spacer formed of an insulating film as a mask to expose the silicon nitride film, and performing a second anisotropic etching after depositing a second conductive film on the entire surface; forming a second electrode in contact with the first electrode side face formed by the first conductive film is left spacer and its lower, heated phosphoric acid aqueous solution or hydrofluoric
Forming a capacitor lower electrode comprising a first electrode and a second electrode by removing the spacer with an acid aqueous solution .

Preferably, each of the first conductive film and the second conductive film is a polysilicon film or an amorphous silicon film .

Second Embodiment of Semiconductor Device Manufacturing Method of the Present Invention
Is not possible on the semiconductor substrate on which the MOS transistor is formed.
Depositing a pure NSG film;
A contact hole that penetrates the SG film and reaches the semiconductor substrate.
Forming a contact hole and filling the contact hole.
After forming the first conductive film covering the NSG film, B
Step of depositing PSG film or insulating film made of PSG film
Performing a heat treatment after forming the insulating film.
And covering the insulating film above the contact hole.
Selectively forming a resist film, and the resist film
Is used as a mask for the reactive ion etching of the insulating film.
Etching to selectively remove the first conductive film
As the etching progresses, the resist film and the etched portion
First anisotropy while attaching a reaction product to the side wall of the insulating film
Using means for performing etching;
After removing the film and attached materials, the remaining insulating film
Etching the first conductive film using the spacer as a mask
Exposing the NSG film to form a second conductive film
Is deposited on the entire surface and then a second anisotropic etching is performed.
The spacer and the first conductive film left under the spacer
Forming a second electrode in contact with the side surface of the first electrode
And heating the aqueous solution with a phosphoric acid aqueous solution or a hydrofluoric acid aqueous solution.
By removing the electrode, the first electrode and the second electrode
Forming a capacitor lower electrode,
is there.

Preferably, the first conductive film and the second conductive film
All conductive films are polysilicon film or amorphous
It is a silicon film.

[0030]

[0031]

[0032]

[0033]

[0034]

[0035]

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described.
Prior to this, the related art of the present invention will be described.

As schematically shown in FIG. 1A, a field oxide film 2 as an element isolation insulating film is formed on the surface of a P-type silicon substrate 1 to partition a MOS transistor formation region of a memory cell. A gate oxide film, a gate electrode 3 of the MOS transistor (also serving as a word line), an N ⁺ type source
A diffusion layer 4 for a capacity and a diffusion layer 5 for a bit line to be a drain region are formed. Next, an interlayer insulating film 6-1 covering the gate electrode and the word line 3 is formed of a silicon oxide film or the like, and a bit line contact plug 9 is formed on the bit line diffusion layer region 5. Then, a bit line 8 electrically connected to the bit line contact plug 9 is provided, and an interlayer insulating film 6-2 is deposited so as to cover the bit line.

Next, a stopper film 7 to be laminated on the interlayer insulating film 6-2 is formed. Here, the stopper film 7 is formed of a silicon nitride film.

Next, a contact hole 10 for a capacitor is opened on the above-mentioned capacitance diffusion layer 4, and a first silicon film 11 (thickness not doped with impurities) which becomes a part of an information storage electrode (lower electrode) of the capacitor is formed. A polysilicon film having a thickness of about 100 to 300 nm) is formed by a known CVD method, and a spacer film 12 is further formed. Here, this spacer film 1
2 has a thickness of 400 to 400 formed by a known CVD method.
A silicon oxide film of about 500 nm is used. After the spacer film 12 is formed, it is heated at 800 to 900 ° C. for 10 to 3 times.
A heat treatment for 0 minutes is performed. This is to make it difficult to be etched in a later step of removing the photoresist film.

Next, using a known lithography technique, a photoresist is applied, exposed, developed and patterned into a desired shape to form a photoresist film 13.

Next, as shown in FIG.
Anisotropic dry etching is performed by using an already patterned photoresist film 13 as a mask by using an IE (reactive ion etching) technique or the like, and the spacer film 12 is patterned. This includes CF ₄ and CH
Etching is performed using a mixed gas mainly containing F ₃ or the like. At this time, as the etching progresses, the spacer film 1 is formed.
Attachment 14A made of a fluorocarbon-based polymer is simultaneously deposited on the side wall generated in 2 and the side wall of photoresist film 13.

Next, the photoresist film 13 is removed.
This includes ashing in oxygen plasma and 120-1
Hot concentrated sulfuric acid treatment at 50 ° C. is generally used. At this time, the attachment 14A is also removed at the same time, and the spacer film 12a is removed.
Is thinned by 10 to 30 nm, and the spacer 12 shown in FIG.
b is obtained. However, the dimensions of the photoresist film pattern need only be determined in consideration of the thinning, and there is no particular inconvenience.

Next, as shown in FIG. 2B, the first silicon film 11 is etched using a mixed gas containing Cl ₂ and HBr as main components and using the already patterned spacer 12b as a mask. . At this time, the reaction product SiBr _x adheres to the spacer 12b and the side wall formed below the spacer 12b (not shown) as the etching progresses, thereby enabling anisotropic etching, as in the conventional example. Attachment 14 when forming
A and spacer 12 caused by photoresist film removal process
There is almost no dimensional difference between b and the first electrode 11aA (the pedestal portion of the lower electrode).

Next, as shown in FIG. 3A, a second silicon film 15A (undoped polysilicon film) is formed to a thickness of, for example, 150 nm by a CVD method. Next, FIG.
As shown in FIG.
Anisotropic dry etching (etch-back) is performed using a technique or the like, and a second layer is formed around the patterned spacer 12b and the first silicon film (11aA).
The second electrode 15Aa (side wall of the lower electrode) is formed by leaving the silicon film in a sidewall shape. For the etching, for example, a mixed gas containing Cl ₂ and HBr as main components is used.

Next, as shown in FIG.
Is selectively removed with a hydrogen fluoride solution. Then, impurities such as arsenic and phosphorus are introduced into the first silicon film and the second silicon film to improve conductivity and complete the formation of the lower electrode. . Next, a dielectric film (not shown) is formed, and a counter electrode is formed to form a capacitor.

In this related technique , the impurity is introduced last when the information storage electrode is formed. However, the impurity may be introduced simultaneously with the formation of the first silicon film and the second silicon film. Good.

Thus, the dimension e1 of the pedestal portion (11aA)
And the inner dimension f1 of the spacer or the side wall (15Aa) can be made almost equal. Therefore, the side wall portion is not thinned near the edge of the pedestal portion and the mechanical strength is not reduced, and it is not necessary to particularly increase the thickness c1 of the side wall portion. It is possible to prevent the yield from being lowered due to the collapse of the side wall while avoiding the danger. Therefore, it is possible to realize a cylinder type in which the capacitance value of the stack type capacitor is increased with a high yield.

Next, a first embodiment of the present invention will be described.

In the related art , the silicon nitride film is used as the stopper film and the silicon oxide film is used as the spacer film. However, a BPSG (silicate glass containing boron glass and phosphorus glass) film may be used as the spacer film. Where BP
The SG film is formed by a known CVD method or the like, and the concentration of boron (B) is set to about 8 to 14 mol% and the concentration of phosphorus (P) is set to about 2 to 8 mol%. After forming the spacer film, heat treatment is performed at 800 to 900 ° C. for 10 to 30 minutes. This is to make it difficult to be etched in a later step of removing the photoresist film 13 and to obtain a flow shape described below.

It is known that a heat treatment at 800 to 900 ° C. can provide a good flow shape at a step portion of a BPSG film, and prevents silicon residue which is likely to be generated at the step portion at the time of etching back the second silicon film. It has the advantage of being able to. However, in the conventional technique, if BPSG is used for the spacer film in order to remove the photoresist film after patterning the spacer film and the first silicon film, the spacer film is etched by 20 to 50 nm in the photoresist removing step, and the spacer film and the first silicon film are removed. This is not practical because a very large dimensional difference is formed between the silicon films.

In the present invention, as described above, after removing the photoresist film, the first film is removed using the spacer film as a mask.
Since the silicon film is patterned, the dimensional difference between the spacer film and the first silicon film can be minimized even if BPSG is used for the spacer film. Also, thin B
In order to use PSG as a mask, the first silicon film is also finely patterned. However, if the size of the photoresist mask is determined in advance in consideration of the thinning of BPSG, no particular problem occurs.

[0052] Next will be described a second embodiment of the present invention. Since BPSG or PSG has a lower chemical resistance and a higher etching rate than NSG (silicate glass containing no impurities), the spacer film can be selectively formed using NSG as a stopper film with heated phosphoric acid, an aqueous solution of hydrogen fluoride, or the like. Can be removed. NSG film is 800
Since the etching rate is reduced by performing the heat treatment at a temperature of about 900 ° C. to about 900 ° C., if the heat treatment is performed after the stopper film is
The selectivity of etching for removing the spacer film can be improved.

The advantages of using the NSG film as a stopper film as described above are as follows.

The silicon nitride film is a film having a high stress, and often causes cracks (cracks) in the silicon nitride film to cause a defect. Further, since the insulating film has a high electric trap density, charge-up is caused, which may adversely affect the operation of the semiconductor device. Therefore, by changing the material of the stopper film from the silicon nitride film to NSG, the occurrence of these defects can be prevented.

It has been confirmed that a PSG (silicate glass containing phosphor glass) film can be used as the spacer film.

At this time, the concentration of phosphorus P in the PSG was 8 mol%.
It is set to not less than 15 mol%. The higher the concentration of phosphorus P, the easier it is to obtain a flow shape and the faster the etching rate with an aqueous solution of hydrogen fluoride or the like, so that the selectivity with a stopper film such as NSG can be easily obtained. However, 15m
%, the surface quality of PSG is deteriorated and the surface is liable to be clouded due to deposition.
Set to 1%.

In addition, ASG (silicate glass containing arsenic glass), GSG (silicate glass containing germanium glass), BSG (silicate glass containing boron glass), group V elements and group III elements,
Alternatively, silicate glass containing both of them can be used similarly.

The case where the first and second silicon films are polysilicon films has been described above, but these may be amorphous silicon films. Alternatively, a barrier film such as TiN _X can be used. The amorphous silicon film becomes a polysilicon film by heat treatment at 600 to 800 ° C. This conversion may be performed after the deposition of the second silicon film and before or after performing the anisotropic etching.

After forming the cylindrical information storage electrode (lower electrode), hemispherical silicon crystal grains (HSG) 16 are formed by a known method as shown in FIG. By doing so, the surface area can be further increased. In particular, in the method of forming microcrystalline nuclei on the surface of amorphous silicon and forming hemispherical silicon crystal grains (HSG) using the surface migration phenomenon of silicon, silicon is consumed from the underlying amorphous silicon and the crystal grains are consumed. Since the swelling occurs, the base material becomes thin, and mechanical strength of the cylinder is required. Therefore, the present invention
It is also effective for the above applications.

[0060]

As described above, according to the present invention, the first insulating film is formed on the first conductive film by using the resist film as a mask.
The anisotropic etching is performed to form a spacer, the resist film is removed, and then the first conductive film is patterned using the spacer as a mask to form a pedestal portion (first electrode) of the capacitor lower electrode. And the pedestal portion can be substantially free of a dimensional difference. Therefore, the side wall portion (second electrode) of the base electrode becomes thin near the edge of the pedestal portion and the mechanical strength is reduced, and it is possible to prevent collapse during the process, and to compensate for the mechanical shortage. The risk of a short circuit between adjacent lower electrodes due to the thickened portion is eliminated.

Further, a reflowable material such as a BPSG film or a PSG film, which has been difficult to use as a spacer in the prior art because of a large etching amount in a resist film removing step and a cleaning step, can be used as a spacer film. By eliminating the remaining second conductive film at the stepped portion, it is possible to provide an effect that dust generated at the time of removing the spacer film can be suppressed.

Further, in this case, since the second insulating film for the spacer having a high etching rate can be used, the use of the NSG film as the stopper film causes the conventional silicon nitride film to be used as the stopper film. It is possible to prevent adverse effects on device operation due to cracks and charge-up that have occurred. Therefore, there is an effect that the reliability and the yield of devices such as a semiconductor storage device having a cylinder type capacitor are improved.

[Brief description of the drawings]

FIGS. 1A and 1B are cross-sectional views in the order of steps for explaining a related technique of the present invention.

FIG. 2 is a cross-sectional view in the order of steps, which is separated from (a) and (b) following FIG. 1;

FIG. 3 is a cross-sectional view in the order of steps, which is separated from (a) and (b) following FIG. 2;

FIG. 4 is a sectional view in order of the process shown after FIG. 3;

FIG. 5 is a cross-sectional view for describing a modification of the related art .

FIG. 6A and FIG. 6B for explaining a conventional example.
FIG.

FIG. 7 is a cross-sectional view in the order of steps, which is shown separately in FIGS.

FIG. 8 is a cross-sectional view in the order of steps, which is separated from (a) and (b) following FIG. 7;

FIG. 9 is a cross-sectional view for describing a problem of the conventional example.

FIG. 10 is a cross-sectional view for describing a problem of the conventional example.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 field oxide film 3 gate electrode 4 capacitance diffusion layer 5 bit line diffusion layer 6-1 interlayer insulation film 6-2 interlayer insulation film 7 stopper film 8 bit line 9 bit line contact plug 10 contact hole 11 first Silicon film 11a, 11aA Lower electrode pedestal portion 12, 12a Spacer film 12b Spacer 13 Photoresist film 14, 14A Attachment 15, 15A Second silicon film 15a, 15Aa Lower electrode sidewall 16 Hemispherical silicon crystal grains

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-260442 (JP, A) JP-A-5-315543 (JP, A) JP-A-6-151535 (JP, A) JP-A-7- 153916 (JP, A) "VLSI Technology" (Second Edition) McGraw-Hill Book Company, 1988; M. Sze (P.200-P.204: Sidewall Mechanism) (58) Fields investigated (Int.Cl. ⁶ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (4)

(57) [Claims] 1. A step of depositing a silicon nitride film on a semiconductor substrate on which a MOS transistor is formed, a step of forming a contact hole penetrating the silicon nitride film and reaching the semiconductor substrate, and filling the contact hole. After forming a first conductive film covering the silicon nitride film , a BPSG film or
Depositing an insulating film made of a PSG film , performing a heat treatment after forming the insulating film, selectively forming a resist film covering the insulating film above the contact hole; attaching a reaction product on a sidewall of the first conductive film and the resist film and already etched portion of the insulating film with the progress of etching to selectively removed by reactive ion etching said insulating film a film as a mask Using a means for performing the first anisotropic etching while removing the resist film and the attached matter,
Etching the first conductive film by using a spacer formed of an insulating film as a mask to expose the silicon nitride film; and performing a second anisotropic etching after depositing a second conductive film on the entire surface. Forming a second electrode in contact with the side surface of the first electrode formed of the spacer and the first conductive film left under the spacer, and removing the spacer with a heated phosphoric acid aqueous solution or a hydrofluoric acid aqueous solution to form a second electrode. Forming a capacitor lower electrode comprising the first electrode and the second electrode. 2. The method according to claim 1, wherein both the first conductive film and the second conductive film are silicon films. 3. A semiconductor substrate on which a MOS transistor is formed.
Silicate glass film (NS
Depositing a G film), and a contour penetrating the NSG film and reaching the semiconductor substrate.
Forming a contact hole and filling the contact hole with the NSG film.
After forming the first conductive film, a BPSG film or a PSG film is formed.
Depositing an insulating film made of a film, performing a heat treatment after forming the insulating film, and a resist covering the insulating film above the contact hole.
Forming a resist film selectively, and reacting the insulating film with a reactive ion using the resist film as a mask.
Selectively removing the first conductive film by etching.
However, as the etching progresses, the resist film and the
The reaction product adheres to the side wall of the insulating film corresponding to the etching.
Using means for performing a first anisotropic etching
And, after removing the resist film and the attached matter, the remaining
The first conductive film using a spacer formed of an insulating film as a mask;
Etching the NSG film to expose the NSG film; and depositing a second conductive film on the entire surface and then forming a second anisotropic etchant.
The spacer and the lower part of the spacer.
A second electrode contacting the first electrode side surface made of the first conductive film
Forming a pole and removing the spacer with a heated phosphoric acid solution or a hydrofluoric acid solution
The first electrode and the second electrode
And forming a lower electrode.
Semiconductor device manufacturing method. 4. The method according to claim 1, wherein the first conductive film and the second conductive film
4. The method of manufacturing a semiconductor device according to claim 3, wherein the semiconductor device is also a silicon film.
Law.