KR100431712B1 - Method of manufacturing semiconductor device with improved topology - Google Patents

Method of manufacturing semiconductor device with improved topology Download PDF

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KR100431712B1
KR100431712B1 KR1019970027884A KR19970027884A KR100431712B1 KR 100431712 B1 KR100431712 B1 KR 100431712B1 KR 1019970027884 A KR1019970027884 A KR 1019970027884A KR 19970027884 A KR19970027884 A KR 19970027884A KR 100431712 B1 KR100431712 B1 KR 100431712B1
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South Korea
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film
peripheral circuit
cell region
insulating film
region
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KR1019970027884A
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Korean (ko)
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KR19990003921A (en
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윤민식
이태국
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method of manufacturing a semiconductor device is provided to improve the topology between a cell region and a peripheral region by leaving a polysilicon layer within the peripheral region. CONSTITUTION: A first insulating layer(24) is formed on a semiconductor substrate(20) with a predetermined lower layer. A conductive layer(25) made of polysilicon and a photoresist pattern are sequentially formed on the first insulating layer. A plate node electrode of the cell region and a plurality of holes within the peripheral region are simultaneously formed by etching selectively the conductive layer and the first insulating layer using the photoresist pattern as an etching mask. A second insulating layer(27) is formed on the resultant structure. A stepped portion between the cell region and the peripheral region is lessened by performing an etch-back process on the second insulating layer.

Description

반도체 장치 제조 방법Semiconductor device manufacturing method

본 발명은 반도체 장치 제조 방법에 관한 것으로 특히, 셀영역과 주변회로 간에 발생하는 단차를 제거할 수 있는 반도체 장치 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of eliminating a step generated between a cell region and a peripheral circuit.

반도체 장치 제조 공정에 있어서, 캐패시터의 플레이트(PLATE)전극이 형성된 후 셀(CELL) 지역과 주변회로 지역 간에 단차가 발생되어 후속 공정을 매우 어렵게 만든다.In the semiconductor device manufacturing process, a step is generated between the CELL region and the peripheral circuit region after the plate electrode of the capacitor is formed, which makes the subsequent process very difficult.

이하, 첨부된 도면을 참조하여 종래 기술의 문제점을 형성한다.Hereinafter, with reference to the accompanying drawings to form a problem of the prior art.

먼저, 도1a에 도시한 바와 같이 전하 저장 전극(11) 등을 포함한 소정의 하부층이 형성된 반도체 기판(10)의 셀영역(a)에 플레이트 전극을 형성하기 위한 사진 식각 공정을 하기 위하여 ONO(oxide-nitride-oxide)막(14)을 형성하여 단차를 제거한다. 이어서, 상기 ONO막(14)상에 플레이트 전극을 형성하기 위하여 도핑된 폴리실리콘막(15)을 증착한다.First, as illustrated in FIG. 1A, ONO (oxide) is used to perform a photolithography process for forming a plate electrode in the cell region a of the semiconductor substrate 10 on which a predetermined lower layer including the charge storage electrode 11 and the like is formed. -nitride-oxide film 14 is formed to eliminate the step. Subsequently, a doped polysilicon film 15 is deposited on the ONO film 14 to form a plate electrode.

다음으로, 도1b에 도시한 바와 같이 상기 폴리실리콘막(15) 상에 플레이트 전극을 형성하기 위한 감광막 패턴(16)을 형성한다.Next, as illustrated in FIG. 1B, a photosensitive film pattern 16 for forming a plate electrode is formed on the polysilicon film 15.

다음으로, 도1c에 도시한 바와 같이 상기 감광막 패턴(16)을 식각 방지막으로 주변회로 영역(b)의 ONO막(14)과 폴리실리콘막(15)을 플라즈마 식각으로 제거하고 상기 감광막 패턴(16)을 제거한다. 미설명 도면 부호 '12' 및 '13'은 각각 활성영역 및 하부 폴리실리콘막과 이후의 형성될 금속막의 콘택 위치를 도시한 것이다.Next, as shown in FIG. 1C, the ONO film 14 and the polysilicon film 15 in the peripheral circuit region b are removed by plasma etching using the photoresist pattern 16 as an etch stop layer. ). Unexplained reference numerals '12' and '13' show contact positions of the active region and the lower polysilicon film and the metal film to be formed later.

상기와 같이 이루어지는 종래 기술은 셀 영역(a)과 주변회로(b) 영역이 ONO막 및 폴리실리콘막의 두께만큼 단차를 갖게 된다. 따라서 후속 금속 배선 공정에서 단차에 의해 감광막의 벌크 효과(BULK EFFECT)가 발생하여 임계치수(CRITICAL DEMENSION) 변화 및 정확성(FIDELITY) 불량을 가져와서 공정의 불안정을 초래한다. 또한, 금속막의 얇아짐이나 무너짐이 나타나 결과적으로 디바이스(DEVICE)의 특성저하 및 수율 감소 현상이 발생하게 된다.According to the prior art made as described above, the cell region a and the peripheral circuit b region have a step difference by the thickness of the ONO film and the polysilicon film. Accordingly, the bulk effect of the photoresist film occurs due to the step difference in the subsequent metal wiring process, resulting in a change in critical dimension and a defect in accuracy, resulting in instability of the process. In addition, the thinning or collapsing of the metal film may occur, resulting in deterioration of the characteristics and yield reduction of the device DEVICE.

상기와 같은 문제점을 해결하기 위한 본 발명은 셀영역과 주변회로의 단차를 줄이기 위한 반도체 장치 제조 방법을 제공하는 것을 그 목적으로 한다.An object of the present invention is to provide a method for manufacturing a semiconductor device for reducing the step between the cell region and the peripheral circuit.

도1a 내지 도1c는 종래 기술에 따른 반도체 장치 형성 공정 단면도1A to 1C are cross-sectional views of a semiconductor device forming process according to the prior art.

도2a 내지 도2e는 본 발명의 일실시예에 따른 반도체 장치 형성 공정 단면도2A through 2E are cross-sectional views of a semiconductor device forming process in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 설명* Description of the main parts of the drawing

10, 20: 반도체 기판 11, 21: 전하 저장 전극10, 20: semiconductor substrate 11, 21: charge storage electrode

12, 13, 23, 33: 금속막 콘택 위치 14, 24: ONO막12, 13, 23, 33: metal film contact positions 14, 24: ONO film

15, 25: 폴리실리콘막 16, 26: 감광막 패턴15, 25: polysilicon film 16, 26: photosensitive film pattern

27: 콘택홀 28: 절연막27 contact hole 28 insulating film

상기 목적을 달성하기 위한 본 발명은 셀영역과 주변회로 영역의 단차를 제거하기 위한 반도체 장치 제조 방법에 있어서, 소정의 하부층이 형성된 반도체 기판 상에 제1 절연막을 형성하는 단계; 상기 절연막 상에 플레이트 전극을 형성하기 위한 전도막을 형성하는 단계; 상기 전도막 상에 플레이트 전극을 정의하고 및 셀영역과 주변회로 영역의 경계를 노출하는 감광막 패턴을 형성하는 단계; 상기 감광막 패턴을 식각 방지막으로 상기 전도막 및 절연막을 식각하여 셀영역에 플레이트 전극을 형성하고 셀영역과 주변회로 영역 경계에 홀을 형성하는 단계; 전체 구조 상에 제2 절연막을 형성하는 단계; 및 상기 제2 절연막을 전면식각하여 셀영역과 주변 회로 영역의 경계에 형성된 홀에 절연막이 남도록 하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device for removing a step between a cell region and a peripheral circuit region, the method including: forming a first insulating layer on a semiconductor substrate on which a predetermined lower layer is formed; Forming a conductive film for forming a plate electrode on the insulating film; Defining a plate electrode on the conductive film and forming a photoresist pattern that exposes a boundary between a cell region and a peripheral circuit region; Etching the conductive layer and the insulating layer using the photoresist pattern as an etch stop layer to form a plate electrode in a cell region and to form a hole in a boundary between the cell region and a peripheral circuit region; Forming a second insulating film on the entire structure; And etching the entire surface of the second insulating film so that the insulating film remains in a hole formed at the boundary between the cell region and the peripheral circuit region.

본 발명은 셀영역과 주변회로의 단차를 줄이기 위해 플레이트 전극 패턴 형성시 주변 회로 영역의 폴리실리콘막 및 절연막을 식각하지않고 셀 영역 지역과 주변 회로 영역을 절연시키기 위하여 셀영역과 주변회로 영역의 경계에 절연막을 형성한다.In order to reduce the step between the cell region and the peripheral circuit, the boundary between the cell region and the peripheral circuit region to insulate the cell region and the peripheral circuit region without etching the polysilicon film and the insulating film of the peripheral circuit region when forming the plate electrode pattern. An insulating film is formed in the film.

이하 첨부된 도면을 참조하여 본 발명을 설명한다.Hereinafter, the present invention will be described with reference to the accompanying drawings.

도2a 내지 도2e는 본 발명의 일실시예에 따른 반도체 장치 제조 방법을 나타내는 단면도이다.2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

먼저, 도2a에 도시한 바와 같이 전하 저장 전극(21) 등을 포함한 소정의 하부층이 형성된 반도체 기판(20) 상에 ONO막(24) 및 폴리실리콘막(25)을 형성한다.First, as shown in FIG. 2A, the ONO film 24 and the polysilicon film 25 are formed on the semiconductor substrate 20 on which the predetermined lower layer including the charge storage electrode 21 and the like is formed.

다음으로, 도2b에 도시한 바와 같이 상기 폴리실리콘막(25) 상에 감광막 패턴(26)을 형성한다. 상기 감광막 패턴은 셀영역(a)에 플레이트 전극 패턴을 형성하고 셀영역(a)과 주변회로 영역(b)의 경계를 노출하며 주변회로 영역(b)의 콘택홀을 형성하기 위한 것이다. 여기서, 미설명 도면 부호 '22' 및 '23'은 각각 활성영역 및 하부 폴리실리콘막과 이후의 형성될 금속막의 콘택 위치를 도시한 것이다.Next, as shown in FIG. 2B, a photosensitive film pattern 26 is formed on the polysilicon film 25. The photoresist pattern is for forming a plate electrode pattern in the cell region a, exposing a boundary between the cell region a and the peripheral circuit region b, and forming a contact hole in the peripheral circuit region b. Here, reference numerals '22' and '23' denote contact positions of the active region and the lower polysilicon film and the metal film to be formed later.

다음으로, 도2c에 도시한 바와 같이 상기 감광막 패턴(26)을 식각 방지막으로 셀영역(a)과 주변회로 영역(b) 경계와 주변회로 영역의 ONO막(24) 및 폴리실리콘막(25)을 선택적으로 식각한다.Next, as shown in FIG. 2C, the photoresist pattern 26 is formed as an etch stop layer, and the ONO film 24 and the polysilicon film 25 in the boundary between the cell region a and the peripheral circuit region b and the peripheral circuit region are formed. Etch selectively.

다음으로, 도2d에 도시한 바와 같이 전체 구조 상에 절연막(28)을 형성한다. 상기 절연막으로 TEOS(tetraorthosilicate)계 산화막, MTO(medium temperature oxide), HTO(high temperature oxide), PSG(phospho-silicate glass), BPSG(boro-phospho-silicate glass), 또는 플라즈마 산화막을 이용한다.Next, as shown in Fig. 2D, an insulating film 28 is formed over the entire structure. A tetraorthosilicate (TEOS) -based oxide film, a medium temperature oxide (MTO), a high temperature oxide (HTO), a phospho-silicate glass (PSG), a boro-phospho-silicate glass (BPSG), or a plasma oxide film is used as the insulating film.

이어서, 도2e에 도시한 바와 같이 상기 절연막(28)을 전면 식각하여 상기 절연막이 주변 회로 영역의 콘택홀(27)내에만 남도록 한다.Subsequently, as shown in FIG. 2E, the insulating film 28 is etched entirely so that the insulating film remains only in the contact hole 27 in the peripheral circuit region.

상기와 같이 이루어지는 본 발명은 플레이트 전극 형성시 주변 회로 영역의 폴리실리콘막 및 ONO막을 제거하지 않으므로 셀영역과 주변 회로의 단차를 줄일 수 있다.According to the present invention, the polysilicon film and the ONO film of the peripheral circuit region are not removed when the plate electrode is formed, so that the step between the cell region and the peripheral circuit can be reduced.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

상기와 같이 이루어지는 본 발명은 셀 영역과 주변 회로 영역의 단차를 제거하여 이후의 금속 배선 공정시 감광막의 벌크 효과(BULK EFFECT)에 의한 임계치수 변동현상을 극소화할 수 있고 정확도 향상을 가져온다. 또한 금속막의 얇아짐 현상이나 무너짐 현상을 방지할 수 있어 디바이스 특성을 향상시킬 수 있다.According to the present invention as described above, the step difference between the cell region and the peripheral circuit region can be eliminated, thereby minimizing the variation of the critical dimension caused by the bulk effect of the photoresist film during the subsequent metal wiring process, and the accuracy is improved. In addition, thinning or collapsing of the metal film can be prevented, thereby improving device characteristics.

Claims (6)

소정의 하부층이 형성된 반도체 기판 상에 제1 절연막을 형성하는 단계;Forming a first insulating film on a semiconductor substrate on which a predetermined lower layer is formed; 상기 절연막 상에 플레이트 전극을 형성하기 위한 전도막을 형성하는 단계;Forming a conductive film for forming a plate electrode on the insulating film; 상기 전도막 상에 플레이트 전극을 정의하고 및 셀영역과 주변회로영역의 경계를 노출하는 감광막 패턴을 형성하는 단계;Defining a plate electrode on the conductive film and forming a photoresist pattern that exposes a boundary between a cell region and a peripheral circuit region; 상기 감광막 패턴을 식각 방지막으로 상기 전도막 및 절연막을 식각하여 셀영역에 플레이트 전극을 형성하고 셀영역과 주변회로 영역 경계에 홀을 형성하는 단계;Etching the conductive layer and the insulating layer using the photoresist pattern as an etch stop layer to form a plate electrode in a cell region and to form a hole in a boundary between the cell region and a peripheral circuit region; 전체 구조 상에 제2 절연막을 형성하는 단계; 및Forming a second insulating film on the entire structure; And 상기 제2 절연막을 전면식각하여 셀영역과 주변 회로 영역의 경계에 형성된 홀에 절연막이 남도록하여 셀영역과 주변 회로의 단차를 줄이는 단계를 포함하여 이루어지는 반도체 장치 제조 방법.And etching an entire surface of the second insulating film so that the insulating film remains in a hole formed at a boundary between the cell region and the peripheral circuit region, thereby reducing the step between the cell region and the peripheral circuit. 제 1 항에 있어서,The method of claim 1, 상기 제1 절연막은 적층된 산화막-질화막-산화막인 것을 특징으로 하는 반도체 장치 제조 방법.And the first insulating film is a stacked oxide film-nitride film-oxide film. 제 1 항에 있어서,The method of claim 1, 상기 전도막은 폴리실리콘막인 것을 특징으로 하는 반도체 장치 제조 방법.And the conductive film is a polysilicon film. 제 1 항에 있어서,The method of claim 1, 상기 감광막 패턴은 주변회로 영역에 콘택홀을 형성하기 위한 패턴을 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.The photoresist pattern includes a pattern for forming a contact hole in the peripheral circuit region. 제 1 항에 있어서,The method of claim 1, 상기 제2 절연막은 TEOS(tetraorthosilicate)계 산화막, MTO(medium temperature oxide), HTO(high temperature oxide), PSG(phospho-silicate glass), BPSG(boro-phospho-silicate glass), 플라즈마 산화막 중의 어느 하나인 것을 특징으로 하는 반도체 장치 제조 방법.The second insulating layer may be any one of a tetraorthosilicate oxide (TEOS), a medium temperature oxide (MTO), a high temperature oxide (HTO), a phospho-silicate glass (PSG), a boro-phospho-silicate glass (BPSG), and a plasma oxide layer. A semiconductor device manufacturing method characterized by the above-mentioned. 제 4 항에 있어서,The method of claim 4, wherein 상기 제2 절연막을 전면 식각하는 과정에서 상기 제2 절연막이 셀영역과 주변회로 영역의 경계에 형성된 홀 및 주변 회로 영역의 콘택홀에 남도록 하는 것을 특징으로 하는 반도체 장치 제조 방법.And etching the second insulating film so that the second insulating film remains in a hole formed at a boundary between the cell region and the peripheral circuit region and a contact hole in the peripheral circuit region.
KR1019970027884A 1997-06-26 1997-06-26 Method of manufacturing semiconductor device with improved topology KR100431712B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0645553A (en) * 1992-05-25 1994-02-18 Mitsubishi Electric Corp Semiconductor storage device and its manufacture
KR950024343A (en) * 1994-01-14 1995-08-21 문정환 Semiconductor memory cell manufacturing method
JPH0870105A (en) * 1994-08-30 1996-03-12 Mitsubishi Electric Corp Semiconductor device and its fabrication

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0645553A (en) * 1992-05-25 1994-02-18 Mitsubishi Electric Corp Semiconductor storage device and its manufacture
KR950024343A (en) * 1994-01-14 1995-08-21 문정환 Semiconductor memory cell manufacturing method
JPH0870105A (en) * 1994-08-30 1996-03-12 Mitsubishi Electric Corp Semiconductor device and its fabrication

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