GB2330002B - Fabrication of integrated circuits having both DRAM and logic circuit - Google Patents
Fabrication of integrated circuits having both DRAM and logic circuitInfo
- Publication number
- GB2330002B GB2330002B GB9721154A GB9721154A GB2330002B GB 2330002 B GB2330002 B GB 2330002B GB 9721154 A GB9721154 A GB 9721154A GB 9721154 A GB9721154 A GB 9721154A GB 2330002 B GB2330002 B GB 2330002B
- Authority
- GB
- United Kingdom
- Prior art keywords
- dram
- fabrication
- logic circuit
- integrated circuits
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9721154A GB2330002B (en) | 1997-10-06 | 1997-10-06 | Fabrication of integrated circuits having both DRAM and logic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9721154A GB2330002B (en) | 1997-10-06 | 1997-10-06 | Fabrication of integrated circuits having both DRAM and logic circuit |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9721154D0 GB9721154D0 (en) | 1997-12-03 |
GB2330002A GB2330002A (en) | 1999-04-07 |
GB2330002B true GB2330002B (en) | 1999-09-08 |
Family
ID=10820108
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9721154A Expired - Lifetime GB2330002B (en) | 1997-10-06 | 1997-10-06 | Fabrication of integrated circuits having both DRAM and logic circuit |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2330002B (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5296399A (en) * | 1991-04-24 | 1994-03-22 | Samsung Electronics Co., Ltd. | Method for manufacturing a narrowed sidewall spacer in a peripheral circuit of a ULSI semiconductor memory device |
US5580813A (en) * | 1992-05-25 | 1996-12-03 | Mitsubishi Denki Kabushiki Kaisha | Method of forming a semiconductor memory device having a contact region between memory cell and an interlayer insolating layer |
-
1997
- 1997-10-06 GB GB9721154A patent/GB2330002B/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5296399A (en) * | 1991-04-24 | 1994-03-22 | Samsung Electronics Co., Ltd. | Method for manufacturing a narrowed sidewall spacer in a peripheral circuit of a ULSI semiconductor memory device |
US5580813A (en) * | 1992-05-25 | 1996-12-03 | Mitsubishi Denki Kabushiki Kaisha | Method of forming a semiconductor memory device having a contact region between memory cell and an interlayer insolating layer |
Also Published As
Publication number | Publication date |
---|---|
GB9721154D0 (en) | 1997-12-03 |
GB2330002A (en) | 1999-04-07 |
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