GB2330002B - Fabrication of integrated circuits having both DRAM and logic circuit - Google Patents

Fabrication of integrated circuits having both DRAM and logic circuit

Info

Publication number
GB2330002B
GB2330002B GB9721154A GB9721154A GB2330002B GB 2330002 B GB2330002 B GB 2330002B GB 9721154 A GB9721154 A GB 9721154A GB 9721154 A GB9721154 A GB 9721154A GB 2330002 B GB2330002 B GB 2330002B
Authority
GB
United Kingdom
Prior art keywords
dram
fabrication
logic circuit
integrated circuits
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB9721154A
Other versions
GB9721154D0 (en
GB2330002A (en
Inventor
Shih-Wei Sun
Tri-Rung Yew
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to GB9721154A priority Critical patent/GB2330002B/en
Publication of GB9721154D0 publication Critical patent/GB9721154D0/en
Publication of GB2330002A publication Critical patent/GB2330002A/en
Application granted granted Critical
Publication of GB2330002B publication Critical patent/GB2330002B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/033Making the capacitor or connections thereto the capacitor extending over the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
GB9721154A 1997-10-06 1997-10-06 Fabrication of integrated circuits having both DRAM and logic circuit Expired - Lifetime GB2330002B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9721154A GB2330002B (en) 1997-10-06 1997-10-06 Fabrication of integrated circuits having both DRAM and logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9721154A GB2330002B (en) 1997-10-06 1997-10-06 Fabrication of integrated circuits having both DRAM and logic circuit

Publications (3)

Publication Number Publication Date
GB9721154D0 GB9721154D0 (en) 1997-12-03
GB2330002A GB2330002A (en) 1999-04-07
GB2330002B true GB2330002B (en) 1999-09-08

Family

ID=10820108

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9721154A Expired - Lifetime GB2330002B (en) 1997-10-06 1997-10-06 Fabrication of integrated circuits having both DRAM and logic circuit

Country Status (1)

Country Link
GB (1) GB2330002B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5296399A (en) * 1991-04-24 1994-03-22 Samsung Electronics Co., Ltd. Method for manufacturing a narrowed sidewall spacer in a peripheral circuit of a ULSI semiconductor memory device
US5580813A (en) * 1992-05-25 1996-12-03 Mitsubishi Denki Kabushiki Kaisha Method of forming a semiconductor memory device having a contact region between memory cell and an interlayer insolating layer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5296399A (en) * 1991-04-24 1994-03-22 Samsung Electronics Co., Ltd. Method for manufacturing a narrowed sidewall spacer in a peripheral circuit of a ULSI semiconductor memory device
US5580813A (en) * 1992-05-25 1996-12-03 Mitsubishi Denki Kabushiki Kaisha Method of forming a semiconductor memory device having a contact region between memory cell and an interlayer insolating layer

Also Published As

Publication number Publication date
GB9721154D0 (en) 1997-12-03
GB2330002A (en) 1999-04-07

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