JPH09116109A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device wherein the effective area of a capacitor can be increased without increasing the occupation planar area of its memory cell. SOLUTION: In a semiconductor storage device, a semiconductor substrate 1, a gate electrode 4 formed on the semiconductor substrate 1 via a gate oxide film 3, a gate coating oxide film 5 formed to coat the gate electrode 4 therewith, and an insulation layer 6 formed thereon are provided respectively. Also, a recessed portion 12 having respectively as its bottom wall and sidewall the upper portion of the gate coating oxide film 5 and a hole passed through the insulation layer 6 is formed. Further, a lower layer capacitor electrode 9 is formed along the bottom wall and sidewall of the recessed portion 12. Moreover, an upper layer capacitor electrode 11 is formed on the lower layer capacitor electrode 9 via a dielectric film 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a dynamic random access memory (DRAM) and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, the demand for semiconductor memory devices has been rapidly expanding due to the remarkable spread of information equipment such as computers. Functionally, a memory having a large storage capacity and capable of high-speed operation is required. In response to this, technological developments related to high integration, high-speed response, and high reliability of semiconductor memory devices are being promoted.

Among semiconductor memory devices, DRAMs (Dynamic Rands) are used as those capable of random input / output of information storage.
om Access Memory) is known. Generally, DRAM
Is composed of a memory cell array, which is a storage area for accumulating a large amount of storage information, and peripheral circuits necessary for external input / output.

FIG. 8 is a block diagram showing the structure of a general DRAM. Referring to FIG. 8, the DRAM 150 is
A memory cell array 151 for accumulating a data signal for information storage, a row-and-column address buffer 152 for externally receiving an address signal for selecting a memory cell forming a unit memory circuit, and decoding the address signal Row decoder 153 and column decoder 154 for designating a memory cell array
A sense refresh amplifier 155 for amplifying and reading a signal stored in a designated memory cell, a data-in buffer 156 and a data-out buffer 157 for data input / output, and a clock signal for generating a clock signal. And a clock generator 158.

A memory cell array 151 occupying a large area on a semiconductor chip is formed by arranging a plurality of memory cells for storing unit storage information in a matrix. FIG. 9 is an equivalent circuit diagram of memory cells constituting the memory cell array 151 for 4 bits. One memory cell 200 includes one MOS (Metal Oxide Semico).
nductor) transistor 220 and 1 connected to it
It is composed of individual capacitors 221. Such a memory cell 200 is called a one-transistor / one-capacitor memory cell. This type of memory cell
Since the structure is simple, it is easy to improve the degree of integration of the memory cell array, and it is widely used for large capacity DRAM.

The memory cells of a DRAM can be classified into several types according to the structure of a capacitor. Among them, in the stacked type capacitor, by extending the main part of the capacitor to the upper part of the gate electrode or the field oxide film, the facing area between the electrodes of the capacitor can be increased and the capacitor capacitance can be increased. Since the stacked type capacitor has such features, even when the element is miniaturized with the integration of the semiconductor device, the capacitance of the capacitor can be secured. As a result, with the integration of semiconductor devices, stacked type capacitors have come to be widely used.
In addition, integration of semiconductor devices has been further advanced, and in response to this, development of stacked capacitors has also been advanced.

FIG. 10 is a sectional view of a stacked type capacitor proposed in Japanese Patent Laid-Open No. 4-82261. Referring to FIG. 10, this one memory cell 200
Includes a MOS transistor 220 and a capacitor 221.

MOS transistor 220 has impurity regions 213 and 214, a gate oxide film 203, and a gate electrode 204b. The impurity regions 213 and 214 are formed in the semiconductor substrate 201. Gate oxide film 20
3 is formed on the semiconductor substrate 201 between the impurity regions 213 and 214. The gate electrode 204b is formed on the semiconductor substrate 201 with the gate oxide film 203 interposed. The insulating film 206 is formed so as to cover the gate electrode 204b.

The capacitor 221 includes a lower layer capacitor electrode 209, a dielectric film 210, and an upper layer capacitor electrode 211.
And The lower layer capacitor electrode 209 is formed on the impurity region 214 and the insulating film 206, and
14 is electrically connected. The dielectric film 210 is formed on the lower layer capacitor electrode 209. Upper layer capacitor electrode 211 is formed on lower layer capacitor electrode 209 with dielectric film 210 interposed.

The bit line 217 is an interlayer insulating film 21 formed on the insulating film 206 and the upper layer capacitor electrode 211.
5 is formed on top of. Bit line 217 is electrically connected to impurity region 213.

Further, on the semiconductor substrate 201, the element isolation film 20 is formed in a region other than the region where the memory cell 200 is formed.
2 are formed. Word lines 204c and 204d are formed on the element isolation film 202. Word line 204
An insulating film 218 is formed so as to cover c and 204d. A step 212 is formed on the upper surface of the insulating film 218. A lower layer capacitor electrode 209 is formed along the step 212.

Next, the manufacturing process of the DRAM shown in FIG. 10 is shown in FIGS. Referring to FIG. 11, a predetermined region of semiconductor substrate 201 has a thickness of 0.2 to
An element isolation film 202 of about 0.6 μm is formed.

Referring to FIG. 12, the surface of semiconductor substrate 201 is thermally oxidized to form gate oxide film 203 having a thickness of about 6 nm to 20 nm on the surface of semiconductor substrate 201 surrounded by element isolation film 202. . Next, a conductive film 204 made of phosphorus-doped polycrystalline silicon having a film thickness of about 100 nm to 300 nm is formed by a low pressure CVD method.
An insulating film 205 made of an oxide film with a thickness of 150 nm to 400 nm is formed by the VD method.

Referring to FIG. 13, the photoconductive method and the dry etching method are used to remove the other portions of the conductive film 204 and the insulating film 205 except for the predetermined portions. As a result, the insulating films 205a and
Gate electrodes or word lines 204a, 204b, 2 of a MOS transistor having 05b, 205c, 205d
04c and 204d are formed.

Referring to FIG. 14, gate electrode 204a,
Impurity regions 213 and 21 are formed on the surface of the semiconductor substrate 201 by implanting phosphorus (P) by an ion implantation method using 204b, 204c and 204d and the insulating films 205a, 205b, 205c and 205d above them as masks.
4 is formed.

Referring to FIG. 15, an insulating film 222 made of an oxide film is deposited on the entire surface of semiconductor substrate 201 by a low pressure CVD method to a film thickness of 50 nm to 400 nm. A resist 219 is formed at a predetermined position on the insulating film 222, and the resist 219 is formed.
16 is used as a mask to selectively remove the other portion by using anisotropic etching, thereby forming an insulating film 206 covering the gate electrodes 204a and 204b as shown in FIG. 16 on the word lines 204c and 204d. An insulating film 218, which is thicker than the insulating film 206 and has a step 212, is formed on the upper surface thereof.

Referring to FIG. 17, a conductive film made of polycrystalline silicon is deposited to a thickness of 50 nm to 400 nm by a low pressure CVD method, and a lower layer capacitor electrode 209 is formed by a usual photolithography method and dry etching method. To do.

Referring to FIG. 18, by the low pressure CVD method,
A nitride film is formed on the entire surface of the semiconductor substrate 201, for example, 4 nm to 1
Deposit to a thickness of 0 nm. By performing heat treatment in an oxygen atmosphere, a part of this nitride film is oxidized to form the dielectric film 210 of the capacitor. Then, a conductive film made of polycrystalline silicon is formed by low pressure CVD to a thickness of about 50 nm to 300 nm.
A film having a thickness of nm is deposited on the entire surface, and the conductive film other than a predetermined region is removed to form an upper layer capacitor electrode 211.

Finally, referring to FIG. 10, an insulating film 215 made of an oxide film is formed to a thickness of 100 nm by the CVD method.
It is deposited on the entire surface with a thickness of up to 700 nm. A contact 216 is formed in a portion where a bit line described later is connected to the source / drain region of the gate electrode. Next, a conductive film made of polycrystalline silicon is formed to a thickness of, for example, 50 nm by the CVD method.
It is deposited on the entire surface with a film thickness of 200 nm. After that, a tungsten silicide film is formed by, for example, 50 n by a sputtering method.
A bit line 217 is formed by depositing a film having a thickness of m to 400 nm on the entire surface and using a normal photolithography method and a dry etching method.

In the DRAM thus formed, the lower layer capacitor electrode 209 is formed along the step 212 of the insulating film 218 to increase the effective area of the capacitor without increasing the occupied area of the memory cell. Can be made.

[0021]

Problems to be Solved by the Invention DRA shown in FIG.
In M, some degree of integration (1 to 4 megabits)
If so, the capacity of the capacitor can be secured, but it cannot cope with the recent remarkable integration of memory cells (64 to 256 Mbits).

Therefore, an object of the present invention is to provide a semiconductor memory device in which the capacitance of a capacitor can be secured without increasing the number of new processes and increasing the area occupied by a memory cell.

[0023]

A semiconductor memory device of the present invention comprises a semiconductor substrate, a gate electrode, an insulating layer, a lower layer capacitor electrode, and an upper layer capacitor electrode. The gate electrode is formed on the semiconductor substrate with a gate insulating film interposed. The insulating layer covers the gate electrode, and a recess having a bottom wall and a side wall is formed on the gate electrode. The lower layer capacitor electrode is formed along the bottom wall and the side wall of the recess of the insulating layer. The upper layer capacitor electrode is formed on the lower layer capacitor electrode with a dielectric film interposed.

Further, the recess may be formed on the gate electrode. In the semiconductor memory device configured as above, since the lower layer capacitor electrode is formed along the bottom wall and the side wall of the recess, it is possible to increase the effective area of the capacitor without increasing the plane area occupied by the memory cell. You can

Further, the method of manufacturing a semiconductor memory device of the present invention comprises a step of forming a gate electrode on a semiconductor substrate with a gate insulating film interposed, and a step of forming an insulating layer so as to cover the gate electrode. A step of forming a recess having a bottom wall and a side wall on the top of the insulating layer, a step of forming a lower layer capacitor electrode along the bottom wall and the side wall of the recess of the insulating layer, and a dielectric film on the lower layer capacitor electrode. And a step of forming an upper layer capacitor electrode with the interposition of.

The step of forming the insulating layer includes the step of covering the gate electrode with the first insulating layer and forming the second insulating layer so as to cover the first insulating layer. May be.

The step of forming the recess may include forming a through hole in the second insulating layer.

Further, the step of forming the recess may include forming the recess on the gate electrode.

In the method of manufacturing the semiconductor memory device having the above structure, the lower layer capacitor electrode formed along the bottom wall and the side wall of the recess of the insulating layer, and the dielectric film interposed on the lower layer capacitor electrode. It is possible to manufacture a semiconductor memory device having an upper layer capacitor electrode formed as described above. Therefore, the effective area of the capacitor can be increased without increasing the area occupied by the memory cell without adding a special process.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a stacked type memory cell of a DRAM according to an embodiment of the present invention. Referring to FIG. 1, a memory cell is formed in active region 19 on the semiconductor substrate. Further, the active region 19 is provided with a capacitor contact hole 8, a bit line contact hole 16, and a recess 12. A lower layer capacitor electrode 9 is provided above the capacitor contact hole 8 and the recess 12. Gate electrode wiring 4 is provided so as to intersect with active region 19.

FIG. 2 is a sectional view taken along line II-II in FIG. Referring to FIG. 2, one memory cell 2
0 has a transistor 22 and a capacitor 21.

The transistor 22 has a gate oxide film 3 and
The gate electrode wiring 4 and the impurity regions 13 and 14 are included. The impurity regions 13 and 14 are respectively composed of high-concentration portions 13a and 14a having a relatively high impurity concentration and low-concentration portions 13b and 14b having a relatively low impurity concentration. The impurity regions 13 and 14 are formed on the semiconductor substrate 1.
Is formed. Gate oxide film 3 is formed on semiconductor substrate 1 between impurity regions 13 and 14. Gate electrode wiring 4 is formed on semiconductor substrate 1 with gate oxide film 3 interposed. The gate coating oxide film 5 is formed so as to cover the gate electrode wiring 4. Insulation film 6
Are formed so as to cover the gate coating oxide film 5. On the upper part of the insulating film 6, there is formed a recess 12 which penetrates the insulating film 6 and whose bottom wall reaches the gate coating oxide film 5.

The capacitor 21 is the lower layer capacitor electrode 9
And a dielectric film 10 and an upper layer capacitor electrode 11. Lower layer capacitor electrode 9 is formed on impurity region 14 and insulating film 6 and along recess 12. Also,
Lower layer capacitor electrode 9 is electrically connected to impurity region 14. The dielectric film 10 is formed on the lower layer capacitor electrode 9. The upper layer capacitor electrode 11 is the dielectric film 1
It is formed on lower layer capacitor electrode 9 with 0 interposed.

Bit line 17 is formed on interlayer insulating film 15 formed on insulating film 6 and upper layer capacitor electrode 11. Bit line 17 is electrically connected to impurity region 13.

Further, the element isolation film 2 is formed on the semiconductor substrate 1 in a region other than the region where the memory cell is formed. Gate electrode wiring 4 is formed on element isolation film 2 with gate oxide film 3 interposed. A gate coating oxide film 5 is formed so as to cover the gate electrode wiring 4.
An insulating film 6 is formed so as to cover the gate coating oxide film 5. In the upper part of the insulating film 6, a recess 12 is formed which penetrates the insulating film 6 and whose bottom wall reaches the upper part of the gate coating oxide film 5. Lower layer capacitor electrode 9 is formed along recess 12. In addition, the lower layer capacitor electrode 9
Upper layer capacitor electrode 11 with dielectric film 10 interposed therebetween.
Are formed.

In the semiconductor memory device of the present invention having the above structure, lower layer capacitor electrode 9 is formed along recess 12. Therefore, the effective area of the lower layer capacitor electrode can be increased as compared with the case where the conventional lower layer capacitor electrode is formed along the step. As a result, the capacitance of the capacitor can be ensured without increasing the area occupied by the memory cell.

Next, manufacturing steps of the DRAM of the present invention shown in FIG. 2 are shown in FIGS. Referring to FIG. 3, semiconductor substrate 1
After the field oxide film 2 is formed at a desired place by using the selective oxidation method (LOCOS method) on the substrate, and the element isolation is performed,
The gate oxide film 3 is deposited to a thickness of 10 nm to 20 nm by the thermal oxidation method. Next, a polycrystalline silicon film or a polycrystalline silicon film doped with phosphorus (P) or the like is deposited by the low pressure CVD method to a film thickness of about 100 nm to 300 nm. Then, the gate electrode wiring 4 is patterned at a desired portion by photolithography and dry etching. Then, the oxide film is formed to a thickness of 300 nm to 40 by the low pressure CVD method.
The gate coating oxide film 5 is added to the gate electrode wiring 4 by depositing it with a film thickness of 0 nm and performing an etch back process. Next, by implanting impurity ions, the low concentration portion 1
3b and 14b are formed, and impurity ions are further implanted to form high-concentration portions 13a and 14a. Next, the interlayer oxide film 18 is formed to a thickness of 200 nm to 30 by a low pressure CVD method.
A film having a thickness of about 0 nm is deposited to form a film that insulates the gate electrode wiring 4 from the lower layer capacitor electrode provided on the gate electrode wiring 4.

Referring to FIG. 4, at the stage of forming capacitor contact hole 8, resist 7 having a pattern for forming a recess is formed and anisotropic etching is performed to form capacitor contact hole 8 and recess 12. Form. The sizes of the recesses 12 and the capacitor contact holes 8 may be the same or different, and the number of the recesses 12 is not limited. Further, since the bottom wall of the recess 12 is formed from the gate coating oxide film 5, insulation between the gate electrode wiring 4 and the lower layer capacitor electrode 9 is secured.

Referring to FIG. 5, a polycrystal silicon film or a polycrystal silicon film doped with phosphorus (P) or the like is deposited to a thickness of 100 nm to 300 nm by a low pressure CVD method, followed by photolithography and dry etching. According to the method, a polycrystalline silicon film or phosphorus (P) is formed only on a desired portion.
The lower layer capacitor electrode 9 is formed while leaving the polycrystalline silicon film doped with the like.

Referring to FIG. 6, a silicon nitride film having a film thickness of about 10 nm to 30 nm is deposited by a low pressure CVD method, and then an oxide film having a film thickness of about 5 nm to 20 nm is deposited by a thermal oxidation method. The film 10 is formed. After that, low pressure CVD
By the method, a polycrystalline silicon film or a polycrystalline silicon film doped with phosphorus (P) or the like is deposited to a film thickness of about 100 nm to 300 nm to form upper layer capacitor electrode 11.

Referring to FIG. 7, an insulating film is formed on the entire surface of semiconductor substrate 1, a resist having a pattern for forming a contact hole is formed, and contact hole 16 is formed by anisotropic etching.

Finally, referring to FIG. 2, the interlayer insulating film 15 is formed.
A bit line 17 made of a conductor is formed on the top of the bit line 17 so as to be connected to the impurity region 13.

In the method of manufacturing a DRAM having such a structure, since the recess 12 is formed at the same time when the capacitor contact hole 8 is formed, the effective area of the capacitor can be increased without adding a special process. Even if the memory cell is reduced in size due to miniaturization, the capacitance of the capacitor can be ensured.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor memory device according to an embodiment of the present invention.

2 is a cross-sectional view taken along line II-II of FIG.
1 is a cross-sectional view of a semiconductor memory device according to one embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a first step of the method for manufacturing the semiconductor memory device of the present invention.

FIG. 4 is a cross-sectional view showing a second step of the method for manufacturing the semiconductor memory device of the present invention.

FIG. 5 is a cross-sectional view showing a third step of the method for manufacturing the semiconductor memory device of the present invention.

FIG. 6 is a cross-sectional view showing a fourth step of the method for manufacturing the semiconductor memory device of the present invention.

FIG. 7 is a sectional view showing a fifth step of the method for manufacturing the semiconductor memory device of the present invention.

FIG. 8 is a block diagram of a conventional general DRAM.

FIG. 9 is an equivalent circuit diagram of a memory cell of a conventional DRAM.

FIG. 10 is a cross-sectional view of a DRAM having a conventional stacked type capacitor.

11 is a cross-sectional view showing a first step of the method for manufacturing the conventional DRAM shown in FIG.

12 is a sectional view showing a second step of the method for manufacturing the conventional DRAM shown in FIG.

13 is a sectional view showing a third step of the method for manufacturing the conventional DRAM shown in FIG.

14 is a sectional view showing a fourth step of the method for manufacturing the conventional DRAM shown in FIG.

FIG. 15 is a cross-sectional view showing a fifth step of the method for manufacturing the conventional DRAM shown in FIG. 10.

16 is a sectional view showing a sixth step of the method for manufacturing the conventional DRAM shown in FIG. 10. FIG.

FIG. 17 is a sectional view showing a seventh step of the method for manufacturing the conventional DRAM shown in FIG. 10.

FIG. 18 is a cross-sectional view showing an eighth step of the method for manufacturing the conventional DRAM shown in FIG. 10.

[Explanation of symbols]

1 semiconductor substrate, 3 gate oxide film, 4 gate electrode,
5 gate coating oxide film, 6 insulating film, 9 lower layer capacitor electrode, 10 dielectric film, 11 upper layer capacitor electrode, 1
2 recess.

Claims (6)

[Claims] 1. A semiconductor substrate, a gate electrode formed on the semiconductor substrate with a gate insulating film interposed, and a recess having a bottom wall and a sidewall formed on the gate electrode to cover the gate electrode. An insulating layer, a lower layer capacitor electrode formed along the bottom wall and side wall of the recess of the insulating layer, and an upper layer capacitor electrode formed with a dielectric film interposed on the lower layer capacitor electrode. A semiconductor memory device provided. 2. The semiconductor memory device according to claim 1, wherein the recess of the insulating layer is formed on the gate electrode. 3. A step of forming a gate electrode on a semiconductor substrate with a gate insulating film interposed, a step of forming an insulating layer so as to cover the gate electrode, and a bottom wall on the insulating layer. Forming a recess having a side wall, forming a lower layer capacitor electrode along a bottom wall and a side wall of the recess of the insulating layer, and an upper layer capacitor with a dielectric film interposed on the lower layer capacitor electrode. And a step of forming an electrode. 4. The step of forming the insulating layer includes the step of covering the gate electrode with the first insulating layer and forming the second insulating layer so as to cover the first insulating layer. Item 3
A method for manufacturing a semiconductor memory device according to claim 1. 5. The method of manufacturing a semiconductor memory device according to claim 4, wherein the step of forming the recess includes forming a through hole in the second insulating layer. 6. The method of manufacturing a semiconductor memory device according to claim 3, wherein the step of forming the recess includes forming a recess on the gate electrode.