JPH06169068A - Semiconductor memory cell and its manufacture - Google Patents

Abstract

PURPOSE:To avoid crackings in a layer insulating film under a capacitor and decrease of the film thickness by a method wherein a cylindrical node electrode is formed on a MOS transistor with the layer insulating film therebetween and the node electrode side uppermost layer of the layer insulating film is composed of an etching-proof film. CONSTITUTION:A node electrode 16 is composed of a first N-type polycrystalline silicon film 13a connected to an N-type node diffused layer 5, a cylindrical second N-type polycrystalline silicon film 13b and a cylindrical third N-type polycrystalline silicon film 13c. A cell-plate 18 and a bit line 8 are separated from each other with a layer insulating film 10 and a boron silicate glass film 11 which is an etching-proof film. With this constitution, very little stress is produced in the interlayer film and crackings are not developed. Further, hydrogen for a hydrogen treatment for the reduction of an interfacial level can be supplied sufficiently. Moreover, a constriction in the contact which is produced in a pre-treatment for forming a conductor film in the contact hole of the node electrode can be avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory cell and a manufacturing method thereof, and more particularly to a dynamic random access memory (DRAM) having a cylindrical node electrode as a stacked capacitor and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, as a memory cell of a highly integrated dynamic random access memory (DRAM),
Multi-cylindrical stacked capacitor cells have been proposed which increase the capacitor surface area with miniaturized cell area.

Next, the manufacturing method thereof will be described. FIG. 3 is a cross-sectional view showing the manufacturing process sequence of a cylindrical stacked capacitor cell of Conventional Example 1 (Japanese Patent Application No. 4-29283).

First, as shown in FIG. 3A, an element isolation insulating film 2 is formed on the surface of a P-type silicon substrate 1, and a gate electrode 3, a gate insulating film 4, an N-type node diffusion layer 5 and N are formed. A transistor including the type bit diffusion layer 6 is formed.

A bit line 8 is connected to the N-type bit diffusion layer 6 through a bit contact hole 7, and the bit line 8 is connected to the gate electrode 3 and the N-type node diffusion layer 5 by an interlayer insulating film 9. Is isolated by. Next, after depositing an interlayer insulating film 10 on the entire surface, a silicon nitride film 12 which is an anti-corrosion film is sequentially deposited.

Next, a contact hole reaching the node diffusion layer 5 is opened, and the first N-type polycrystalline silicon film 13a and the first N-type polycrystalline silicon film 13a are formed.
The silicon oxide film 15a is sequentially deposited. Subsequently, by anisotropic etching such as reactive ion etching using a photoresist film (not shown) as a mask, the first silicon oxide film 15a and the first N-type polycrystalline silicon film 13a are formed.
Are sequentially etched. After removing the photoresist film, the second N-type polycrystalline silicon film 13b and the second silicon oxide film 15b are sequentially deposited, and then the second silicon oxide film is formed by anisotropic etching such as reactive ion etching. The film 15b is etched so that the second silicon oxide film 15b is left on the sidewall of the second N-type polycrystalline silicon film 13b.

Next, as shown in FIG. 3B, after depositing a third N-type polycrystalline silicon film 13c, anisotropic etching such as reactive ion etching is performed to form a second N-type polycrystalline silicon film. Film 13b and third N-type polycrystalline silicon film 1
Etch 3c.

Next, as shown in FIG. 3C, the first and second silicon oxide films 15a and 15b are removed by hydrofluoric acid-based wet etching to remove the first to third polycrystalline silicon films. The node electrode 16 is formed.

Next, as shown in FIG. 3D, after the capacitive insulating film 17 and the N-type polycrystalline silicon 18 are deposited on the entire surface,
This is etched to form a cell plate electrode,
Complete the DRAM.

FIG. 4 is a cross-sectional view showing the manufacturing process sequence of the cylindrical stacked capacitor cell of Conventional Example 2. 4A to 4D, the difference from the conventional example 1 is that the silicon nitride film 12 on the interlayer insulating film 10 is clear as shown in FIGS.
Is abolished, and the first and second silicon oxide films 15 are removed.
The only difference is that a and 15b are replaced with phosphorus silicate glass films (silicon oxide films containing phosphorus) 14a and 14b.

[0011]

However, in the method of Conventional Example 1, the presence of the silicon nitride film causes (1) the semiconductor substrate to warp due to the stress of the silicon nitride film. A crack occurs. (2) At the end of the manufacturing process, hydrogen in the hydrotreatment for reducing the interface state is not sufficiently supplied. (3) After the contact hole that connects the upper and lower portions of the silicon nitride film is opened, the etching rate ratio between the interlayer insulating film and the silicon nitride film is about 100: 1 in the pretreatment for forming the conductor film. Since it is high, there is a problem that the contact hole is narrowed, the conductor film is hard to be formed on the side wall of the contact hole, and disconnection occurs.

Further, according to the method of Conventional Example 2 which solves these problems, (1) the etching rate ratio between the phosphoric acid silicate glass film and the interlayer insulating film is 7: 7 when removed with a solution containing hydrofluoric acid. In the case of a phosphorus silicate glass film having a phosphorus concentration of about 1, the etching amount in the photoresist film removing step and the pretreatment steps for forming the second and third polycrystalline silicon films is large, and is 0.18 μm.
The film thickness is reduced, which hinders the increase in the diameter of the cylinder for increasing the surface area of the node electrode. (2) In the phosphorous silicate glass film having a phosphorus concentration that suppresses the film loss in (1) to less than half, the fluoric acid between the phosphorous silicate glass film and the interlayer insulating film composed of the phosphorus-boron silicate glass film is removed. The etching rate ratio with respect to the containing solution is as small as about 5: 1, the etching amount of the interlayer insulating film is increased as much as about 0.12 μm, and the manufacturing margin is reduced.

An object of the present invention is to provide a semiconductor memory cell in which cracks in an interlayer film under a capacitor are prevented from being generated and a semiconductor memory cell is manufactured, and a manufacturing method thereof.

[0014]

To achieve the above object, a semiconductor memory cell according to the present invention is a semiconductor memory cell comprising a combination of a MOS transistor and a tubular node electrode, the tubular node electrode Is formed on the MOS transistor via an interlayer insulating film, and the uppermost layer of the interlayer insulating film on the side of the cylindrical node electrode is a corrosion resistant film.

A method of manufacturing a semiconductor memory cell according to the present invention is a method of manufacturing a semiconductor memory cell, which includes a corrosion-resistant film forming step, a contact opening step, and a node electrode forming step. In the process, a corrosion-resistant film is formed on the uppermost layer of the interlayer insulating film covering the transistor on the semiconductor substrate, and in the contact opening process, the transistor is penetrated through the uppermost corrosion-resistant film and the lower interlayer insulating film. Contact electrode formation step, the node electrode forming step includes a bottom film forming step, a peripheral wall film forming step, and a finishing step, and the bottom film forming step includes forming a cylindrical node on the corrosion-resistant film. A bottom film that forms the bottom of the electrode is formed. The bottom film reaches the transistor through a contact hole and has an insulator deposited on the upper surface. The step is to form the peripheral wall film forming the peripheral wall of the cylindrical node electrode along the side wall of the insulator so as to rise upward from the outer edge of the bottom film, and in the finishing step, the insulator is removed to form the bottom film. And a cylindrical node electrode composed of the peripheral wall film.

The peripheral wall film is connected to the bottom film and is formed in multiple layers inside and outside.

[0017]

[Function] A phosphorous silicate glass film is used as an insulator formed inside the inner cylinder, and boron silicate glass covers the surface of the interlayer insulating film below the node electrode as an etching-resistant film when the phosphorous silicate glass film is removed. It is structured.

Therefore, stress is not generated in the interlayer film and cracks do not occur. It is possible to sufficiently supply hydrogen for hydrotreatment for reducing the interface state. There is no occurrence of constriction in the contact that occurs in the pretreatment when the conductor film is formed in the contact hole of the node electrode. And so on.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A is a schematic plan view showing an embodiment of the present invention, and FIG. 1B is a sectional view taken along the line AA ′ of FIG.

In FIG. 1, a semiconductor memory cell according to the present invention has a MOS transistor and a capacitor section.

The MOS transistor is composed of an N-type node diffusion layer 5 and an N-type bit diffusion layer 6 formed on a P-type silicon substrate 1, and a gate electrode 3 stacked with a gate insulating film 4 interposed therebetween. The MOS transistors are electrically isolated from each other by the element isolation insulating film 2.
The gate electrode 4 is embedded in the interlayer insulating film 9, and the bit line 8 and the N-type bit diffusion layer 6 are connected through the bit contact hole 7 formed in the interlayer insulating film 9.

The capacitance portion is coupled to the first N-type polycrystalline silicon film 13a connected to the N-type node diffusion layer 5 and the outer edge of the first N-type polycrystalline silicon film 13a and rises upward. The cylindrical second N-type polycrystalline silicon film 13b and the second
Cylindrical N-type polycrystalline silicon film 13c which is joined to the outer edge of the N-type polycrystalline silicon film 13b and rises upward.
And a cell plate electrode 18 as a counter electrode, and a capacitive insulating film 17 as a dielectric film for isolating the cell plate electrode 18 from the node electrode. The node electrode 16 has a structure in which cylindrical polycrystalline silicon films 13b and 13c are arranged in inner and outer double layers, and inner and outer double polycrystalline silicon films 13b and 13c are mutually coupled to the polycrystalline silicon film 13a. Has become.

Further, the cell plate electrode 18 and the bit line 8
Are separated from each other by the interlayer insulating film 10 and the boron silicate glass film 11 as a corrosion resistant film.

2A to 2D are schematic sectional views showing a method of manufacturing the semiconductor memory cell according to the embodiment of the present invention shown in FIG. 1 in the order of manufacturing steps.

First, as shown in FIG. 2A, an element isolation insulating film 2 is formed on the surface of a P-type silicon substrate 1, and a gate electrode 3, a gate insulating film 4, an N-type node diffusion layer 5, and the like. N
A transistor including the bit diffusion layer 6 of the mold is formed.

A bit line 8 is connected to the N-type bit diffusion layer 6 through a bit contact hole 7, and the bit line 8 is interlayer-insulated with respect to the gate electrode 3 and the N-type node diffusion layer 5. It is isolated via the membrane 9.

Next, the interlayer insulating film 1 is formed on the entire surface including the bit line 8.
After depositing 0, a boron silicate glass film 1 which is an anti-corrosion film
1 is sequentially deposited by, for example, a film having a concentration of boron of about 10 mol%.

Next, a contact hole reaching the node diffusion layer 5 is opened, and the first N-type polycrystalline silicon film 13a and the first N-type polycrystalline silicon film 13a are formed.
The phosphorous silicate glass film 14a is sequentially deposited with, for example, a film of phosphorus having a concentration of about 4 mol%. Then, by anisotropic etching such as reactive ion etching using a photoresist film (not shown) as a mask, the first phosphosilicate glass film 1 is formed.
4a and the first N-type polycrystalline silicon film 13a are sequentially etched. After removing the photoresist film, the second N
Type polycrystalline silicon film 13b and second phosphosilicate glass film 14b are sequentially deposited with the same phosphorus concentration as the first phosphosilicate glass film 14a, and then anisotropic etching such as reactive ion etching is performed. , The second phosphosilicate glass film 14
b is etched to obtain the second N-type polycrystalline silicon film 13
It is formed so that the second phosphosilicate glass film 14b is left on the outer periphery of b.

Next, as shown in FIG. 2 (b), after depositing a third N-type polycrystalline silicon film 13c on the outer periphery of the second phosphosilicate glass film 14b, anisotropic etching such as reactive ion etching is performed. The second and third N-type polycrystalline silicon films 13b and 13c are etched by reactive etching.

Next, as shown in FIG. 2C, for example, wet etching of buffered hydrofluoric acid of about 8% hydrofluoric acid and about 25% ammonium fluoride is performed for about 2 minutes, whereby the first etching is performed.
And removing the second phosphosilicate glass films 14a and 14b,
First to third polycrystalline silicon films 13a, 13b, 13c
To form the node electrode 16.

Next, as shown in FIG. 2D, after the capacitance insulating film 17 and the N-type polycrystalline silicon 18 are deposited on the entire surface,
This is etched to form the cell plate electrode 18 to complete the DRAM.

Although the double cylinder type stack capacitor has been described in the present embodiment, in the case of the single cylinder type stack capacitor, the second polycrystalline silicon film 13 is used.
After depositing b, the second polycrystalline silicon film 13b is formed on the side wall of the first phosphosilicate glass film 14a by anisotropic etching.
Are formed so as to leave the first and second polycrystal silicon films 13a and 13a by removing the first phosphosilicate glass film 14a by hydrofluoric acid-based wet etching.
A single-cylindrical node electrode 16 made of b is formed, a capacitor insulating film and N-type polycrystalline silicon are then deposited on the entire surface, and this is etched to form a cell plate electrode, thereby completing a DRAM. .

In the case of a triple or more cylindrical stack capacitor, after depositing the third polycrystalline silicon film 13c,
The n-th phosphosilicate glass film is deposited to a thickness within the range in which the first phosphosilicate glass film step and the first phosphosilicate glass film are present, and this is anisotropically etched to The step of forming the n-th polycrystalline silicon film so as to leave the n-th phosphosilicate glass film on the side wall and then depositing the (n + 1) -th polycrystalline silicon is repeated (where n is a natural number).

Next, anisotropic etching is applied to the second to (n + 1) th.
Of the first to (n + 1) th polycrystalline silicon film is removed by wet etching of hydrofluoric acid to remove the first to (n + 1) th polycrystalline silicon. By forming a node electrode, then depositing a capacitive insulating film and N-type polycrystalline silicon on the entire surface, and etching this to form a cell plate electrode, D
Complete the RAM.

[0035]

As described above, the present invention provides a DR having a cylindrical node electrode as a stacked capacitor.
In AM, a phosphosilicate glass film is used as an insulator formed inside a cylinder, and a boron silicate glass film covers the surface of the interlayer insulating film under the node electrode as an etching-resistant film when removing the phosphosilicate glass film. With the structure, since the silicon nitride film is not used as the corrosion-resistant film, stress is not generated in the interlayer film and cracks do not occur. It is possible to sufficiently supply hydrogen for hydrotreatment for reducing the interface state. There is no occurrence of constriction in the contact that occurs in the pretreatment when the conductor film is formed in the contact hole of the node electrode. And so on.

Further, the phosphorus concentration in the phosphorous silicate glass film can be suppressed to a low level as compared with the case where the interlayer insulating film itself made of a phosphorus-boron silicate glass film is used as the corrosion resistant film, and the post-treatment of the phosphorus silicate glass film deposition The film loss of the phosphosilicate glass film due to can be reduced to about 0.06 μm. The reduction in thickness of the interlayer insulating film under the node electrode is suppressed to about 0.06 μm, which is less than half, and the manufacturing margin is increased. And so on.

[Brief description of drawings]

FIG. 1A is a plan view showing an embodiment of the present invention, and FIG.
FIG. 7A is a sectional view taken along line AA ′ in (a).

FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor memory cell according to an embodiment of the present invention in the order of steps.

3A to 3C are cross-sectional views showing a manufacturing method according to Conventional Example 1 in the order of steps.

4A to 4C are cross-sectional views showing a manufacturing method according to Conventional Example 2 in the order of steps.

[Explanation of symbols]

 1 P-type silicon substrate 2 Element isolation insulating film 3 Gate electrode (word line) 4 Gate insulating film 5 N-type node diffusion layer 6 N-type bit diffusion layer 7 Bit contact hole 8 Bit line 9, 10 Interlayer insulation film 11 Boron silicate Glass film 12 Silicon nitride film 13a, 13b, 13c N-type polycrystalline silicon film 14a, 14b Phosphorus silicate glass film 15a, 15b Silicon oxide film 16 Node electrode 17 Capacitive insulating film 18 Cell plate electrode (polycrystalline silicon)

Claims (3)

[Claims] 1. A semiconductor memory cell comprising a combination of a MOS transistor and a tubular node electrode, wherein the tubular node electrode is formed on the MOS transistor via an interlayer insulating film, A semiconductor memory cell, wherein an uppermost layer of the interlayer insulating film on the side of the cylindrical node electrode is a corrosion-resistant film. 2. A method of manufacturing a semiconductor memory cell, comprising: a corrosion-resistant film forming step, a contact opening step, and a node electrode forming step, wherein the corrosion-resistant film forming step is an interlayer insulation covering a transistor on a semiconductor substrate. The corrosion-resistant film is formed on the uppermost layer of the film, and the contact opening step forms a contact hole that reaches the transistor by penetrating the uppermost corrosion-resistant film and the lower interlayer insulating film. The electrode forming process includes a bottom film forming process, a peripheral wall film forming process, and a finishing process.The bottom film forming process forms a bottom film forming the bottom of the cylindrical node electrode on the corrosion-resistant film. And the bottom membrane is
It reaches the transistor through the contact hole, and the insulator is deposited on the upper surface. In the peripheral wall film forming process, the peripheral wall film forming the peripheral wall of the tubular node electrode is attached to the side wall of the insulator and the outer edge of the bottom film is formed. The method of manufacturing a semiconductor memory cell is characterized in that it is formed by rising upwards, and the finishing step is a step of removing an insulator and forming a cylindrical node electrode composed of a bottom film and a peripheral wall film. . 3. The method of manufacturing a semiconductor memory cell according to claim 2, wherein the peripheral wall film is connected to the bottom film and is formed in multiple layers inside and outside.