JPH048431U - - Google Patents
Info
- Publication number
- JPH048431U JPH048431U JP1990046889U JP4688990U JPH048431U JP H048431 U JPH048431 U JP H048431U JP 1990046889 U JP1990046889 U JP 1990046889U JP 4688990 U JP4688990 U JP 4688990U JP H048431 U JPH048431 U JP H048431U
- Authority
- JP
- Japan
- Prior art keywords
- wire bonding
- bare chip
- mounting board
- chip mounting
- bonding pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
第１図は本考案によるベアチツプ取付基板の一
実施例を示す概略平面図である。第２図は本考案
によるベアチツプ取付基板の他の実施例を示す概
略平面図である。第３図は従来のベアチツプ取付
基板の一例を示す概略平面図である。
１０……ベアチツプ取付基板；１１……ベアチ
ツプ；１１ｂ……電極端子；１２……ワイヤボン
デイングパツド；１３……ボンデイングワイヤ。
FIG. 1 is a schematic plan view showing an embodiment of a bare chip mounting board according to the present invention. FIG. 2 is a schematic plan view showing another embodiment of the bare chip mounting board according to the present invention. FIG. 3 is a schematic plan view showing an example of a conventional bare chip mounting board. 10... Bear chip mounting board; 11... Bare chip; 11b... Electrode terminal; 12... Wire bonding pad; 13... Bonding wire.
Claims (1)
に沿つて整列するように導電パターンにより構成
された複数のワイヤボンデイングパツドを備えた
ベアチツプ取付基板において、 上記ワイヤボンデイングパツドのうち、各ベア
チツプに関連する少なくとも一方の端部に位置す
るワイヤボンデイングパツドが、他のワイヤボン
デイングパツドと異なる形状に形成されているこ
とを特徴とする、ベアチツプ取付基板。[Claims for Utility Model Registration] A bare chip mounting board comprising a plurality of wire bonding pads formed of a conductive pattern so as to be aligned along the side edges of a plurality of bare chips to be attached, A bare chip mounting board characterized in that a wire bonding pad located at at least one end associated with each bare chip is formed in a shape different from other wire bonding pads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990046889U JPH048431U (en) | 1990-05-07 | 1990-05-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990046889U JPH048431U (en) | 1990-05-07 | 1990-05-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH048431U true JPH048431U (en) | 1992-01-27 |
Family
ID=31562352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990046889U Pending JPH048431U (en) | 1990-05-07 | 1990-05-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH048431U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6242241B2 (en) * | 1985-01-18 | 1987-09-07 | Yoshio Morita |
-
1990
- 1990-05-07 JP JP1990046889U patent/JPH048431U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6242241B2 (en) * | 1985-01-18 | 1987-09-07 | Yoshio Morita |