JPS6373968U - - Google Patents

Info

Publication number
JPS6373968U
JPS6373968U JP1986167744U JP16774486U JPS6373968U JP S6373968 U JPS6373968 U JP S6373968U JP 1986167744 U JP1986167744 U JP 1986167744U JP 16774486 U JP16774486 U JP 16774486U JP S6373968 U JPS6373968 U JP S6373968U
Authority
JP
Japan
Prior art keywords
solder surface
jumper wire
utility
wiring board
scope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986167744U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986167744U priority Critical patent/JPS6373968U/ja
Publication of JPS6373968U publication Critical patent/JPS6373968U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Multi-Conductor Connections (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の実施例によるデイツプIC
の下のパターン接続図、第2図及び第3図はジヤ
ンパ線による接続変更の説明図、第4図は従来の
デイツプICの下のパターン接続図である。 図において、Wはジヤンパ線、Mは半田面であ
る。なお、図中、同一符号は同一、又は相当部分
を示す。
Figure 1 shows a dip IC according to an embodiment of this invention.
2 and 3 are explanatory diagrams of connection changes using jumper wires, and FIG. 4 is a pattern connection diagram below the conventional dip IC. In the figure, W is a jumper wire and M is a solder surface. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] デユアルインラインパツケージICの下に実装
するジヤンパ線を半田面で接続したことを特徴と
するプリント配線基板。
A printed wiring board characterized in that a jumper wire mounted under a dual inline package IC is connected with a solder surface.
JP1986167744U 1986-10-31 1986-10-31 Pending JPS6373968U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986167744U JPS6373968U (en) 1986-10-31 1986-10-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986167744U JPS6373968U (en) 1986-10-31 1986-10-31

Publications (1)

Publication Number Publication Date
JPS6373968U true JPS6373968U (en) 1988-05-17

Family

ID=31099963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986167744U Pending JPS6373968U (en) 1986-10-31 1986-10-31

Country Status (1)

Country Link
JP (1) JPS6373968U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02174185A (en) * 1988-12-26 1990-07-05 Hitachi Ltd memory module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02174185A (en) * 1988-12-26 1990-07-05 Hitachi Ltd memory module

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