JPH0469424B2 - - Google Patents

Info

Publication number
JPH0469424B2
JPH0469424B2 JP58173541A JP17354183A JPH0469424B2 JP H0469424 B2 JPH0469424 B2 JP H0469424B2 JP 58173541 A JP58173541 A JP 58173541A JP 17354183 A JP17354183 A JP 17354183A JP H0469424 B2 JPH0469424 B2 JP H0469424B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
view
bonding
semiconductor
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58173541A
Other languages
English (en)
Other versions
JPS6064442A (ja
Inventor
Toshuki Yoda
Junichi Kasai
Katsushi Yoshitoshi
Akihiro Kubota
Koichi Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58173541A priority Critical patent/JPS6064442A/ja
Publication of JPS6064442A publication Critical patent/JPS6064442A/ja
Publication of JPH0469424B2 publication Critical patent/JPH0469424B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は半導体装置にかかり、特にワイヤ短絡
防止構造に関する。
(b) 従来技術と問題点 半導体装置の目覚ましい進歩によつてIC、
LSI、VLSIと極めて高集積化されているが、そ
れに伴つて半導体チツプから導出するボンデイン
グワイヤの数も多くなり、且つ半導体チツプも大
きくなつてきた。
そうすると、多数のボンデイングワイヤの中に
は、長い距離を接続しなければならないボンデイ
ングワイヤも現れ、その場合にワイヤの垂れ下り
が起こり易くなる。ワイヤの垂れはボンデイング
機の調整不良にも原因があるが、ボンデイング機
を長時間使用していると次第に調整が崩れてくる
問題もある。そのためワイヤ垂れを起こし、次の
プラスチツク樹脂封止工程や試験工程において多
数の接触不良品を検出し、歩留が低下して手痛い
損害を被ることがある。
第１図はボンデイングワイヤを配線した工程後
の全体断面図、第２図ａ、ｂは上記のような問題
点の一例を図示した部分図で、同図ａは断面図、
同図ｂは平面図である。１は半導体チツプ、２は
ボンデイングワイヤ、３はステージ、４はワイヤ
接続端子で、ボンデイングワイヤ２が垂れて半導
体チツプ１の表面周縁（矢印部分）で接触してお
り、このような状態になると半導体装置は正常な
電気特性が得られない。
(c) 発明の目的 本発明はこのような問題点を除去した半導体装
置を提供するものである。
(d) 発明の構成 その目的は、半導体チツプとボンデイングワイ
ヤとの短絡防止用絶縁フイルムが該半導体チツプ
表面に、その周辺からはみ出すように貼付されて
いる半導体装置、もしくは該絶縁フイルムが該半
導体チツプのボンデイングパツド部を除く全表面
を覆い、且つその周辺部からはみ出すように貼付
されている半導体装置によつて達成される。
(e) 発明の実施例 以下、図面を参照して実施例によつて詳細に説
明する。第３図ａ，ｂは本発明にかかる一実施例
図で、同図ａは一部断面図、同図ｂは全体の平面
図である。図において、１０は耐熱性テープに接
着剤を付けた絶縁フイルムを示しており、ボンデ
イングパツド領域を除く半導体チツプ１の全面を
周縁からはみ出すように絶縁フイルム１０で覆つ
ている。耐熱性テープは例えば商品名KAPTON
フイルム、接着剤はポリイミドなどを使用し、厚
みは接着剤を含めて100μｍ前後のものである。
このようにすれば、第３図ａに図示されているよ
うにボンデイングワイヤ２が垂れ下つても、絶縁
フイルム１０のために半導体チツプ１と接触する
ことはなくなり、樹脂封入までその形状を維持
し、また封止後に絶縁フイルム１０を残存してい
ても耐熱性絶縁体のため悪影響はない。
第３図ｂに全体の平面図を示しているが、本例
はLSIメモリ、例えば64KビツトDRAMのチツプ
部分の平面図である。著しく高集積化されると、
半導体チツプ１は大きくなるものの、パツケージ
の型式に規正されて、チツプ形状は一方向に細長
くならざるを得ない。且つ、ボンデイングパツド
領域は長手方向の両端に設けられる。従つて、図
示のようにボンデイングワイヤ２が極めて長くな
つて、本発明による構造が必要になるわけであ
る。
また、第４図ａ，ｂは本発明にかかる更に他の
実施例を示した図で、同図ａは部分断面図、同図
ｂは全体平面図である。本例では絶縁フイルム１
２を半導体チツプ１の表面周囲に貼付しており、
同様に接触防止の効果がある。
これらの絶縁フイルムの取りつけはいづれも半
導体チツプ１をステージ３に取りつけた後、ワイ
ヤをボンデイングする前に行う。かくすることに
よつて、ボンデイングワイヤが垂れ下つても、半
導体チツプとは絶縁が維持される。
(f) 発明の効果 以上の説明から判るように、本発明によればボ
ンデイングワイヤの接触が防止されて、半導体装
置の歩留並びに信頼性が向上するものである。
なお、本発明はプラステイツク樹脂封止型半導
体装置だけでなく、セラミツク容器などパツケー
ジ封止型半導体装置にも適用できることは云うま
でもない。
【図面の簡単な説明】
第１図はワイヤ配線の全体断面図、第２図ａ，
ｂは従来の問題点を示す部分断面図と部分平面
図、第３図ａ，ｂは本発明にかかる一実施例の一
部断面図と全体平面図、第４図ａ，ｂは本発明に
かかる他の実施例の部分断面図と全体平面図。 図中、１は半導体チツプ、２はボンデイングワ
イヤ、３はステージ、４はワイヤ接続端子、１
０，１１，１２は絶縁フイルムを示している。

Claims (1)

  1. 【特許請求の範囲】 １ 半導体チツプとボンデイングワイヤとの短絡
    防止用絶縁フイルムが該半導体チツプ表面に、そ
    の周辺部からはみ出すように貼付されていること
    を特徴とする半導体装置。 ２ 半導体チツプとボンデイングワイヤとの短絡
    防止用絶縁フイルムが該半導体チツプのボンデイ
    ングパツド部を除く全表面を覆い、且つその周辺
    部からはみ出すように貼付されていることを特徴
    とする半導体装置。
JP58173541A 1983-09-19 1983-09-19 半導体装置 Granted JPS6064442A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58173541A JPS6064442A (ja) 1983-09-19 1983-09-19 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58173541A JPS6064442A (ja) 1983-09-19 1983-09-19 半導体装置

Publications (2)

Publication Number Publication Date
JPS6064442A JPS6064442A (ja) 1985-04-13
JPH0469424B2 true JPH0469424B2 (ja) 1992-11-06

Family

ID=15962441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58173541A Granted JPS6064442A (ja) 1983-09-19 1983-09-19 半導体装置

Country Status (1)

Country Link
JP (1) JPS6064442A (ja)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2509422B2 (ja) * 1991-10-30 1996-06-19 三菱電機株式会社 半導体装置及びその製造方法
JP2586835B2 (ja) * 1994-10-28 1997-03-05 日本電気株式会社 半導体集積回路
US5585667A (en) * 1994-12-23 1996-12-17 National Semiconductor Corporation Lead frame for handling crossing bonding wires
JP5234703B2 (ja) * 2006-06-21 2013-07-10 株式会社日立超エル・エス・アイ・システムズ 半導体装置の製造方法
JP2016192513A (ja) * 2015-03-31 2016-11-10 株式会社沖データ 半導体装置、半導体素子アレイ装置、及び画像形成装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5375763A (en) * 1976-12-16 1978-07-05 Nec Corp Manufacture for semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5265868U (ja) * 1975-11-11 1977-05-16
JPS5784752U (ja) * 1980-11-12 1982-05-25

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5375763A (en) * 1976-12-16 1978-07-05 Nec Corp Manufacture for semiconductor device

Also Published As

Publication number Publication date
JPS6064442A (ja) 1985-04-13

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