JPH0463175U - - Google Patents
Info
- Publication number
- JPH0463175U JPH0463175U JP10551390U JP10551390U JPH0463175U JP H0463175 U JPH0463175 U JP H0463175U JP 10551390 U JP10551390 U JP 10551390U JP 10551390 U JP10551390 U JP 10551390U JP H0463175 U JPH0463175 U JP H0463175U
- Authority
- JP
- Japan
- Prior art keywords
- split
- board
- boards
- printed wiring
- multilayer printed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010354 integration Effects 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 1
Landscapes
- Structure Of Printed Boards (AREA)
Description
第１図は本考案に係る多層プリント配線基板の
一実施例を模式的に示した断面図、第２図は本考
案に係る多層プリント配線基板の別の実施例を模
式的に示した断面図である。
１０，２０……割り基板、１４，１４ａ〜１４
ｈ，４４，４４ａ〜４４ｈ……回路パターン、３
０……割り部分、３１……内層パターン、４０…
…第１の割り基板、５０……第２の割り基板、５
６……ランド部。
FIG. 1 is a cross-sectional view schematically showing one embodiment of the multilayer printed wiring board according to the present invention, and FIG. 2 is a cross-sectional view schematically showing another embodiment of the multilayer printed wiring board according to the present invention. It is. 10, 20...Split board, 14, 14a-14
h, 44, 44a to 44h...Circuit pattern, 3
0...Split part, 31...Inner layer pattern, 40...
...First split board, 50...Second split board, 5
6... Land department.
Claims (1)
ント配線基板において、前記割り基板の分割前に
はこれら各割り基板に形成されている回路パター
ンを接続し、前記割り基板の分割時には前記回路
パターンとの接続が切断される内層パターンが、
前記割り基板間の割り部分に形成されていること
を特徴とする多層プリント配線基板。 (2) 機器組み込みに使用される第１の割り基板
と、機器組み込みに使用されない第２の割り基板
とから構成された多層プリント配線基板であつて
、前記第２の割り基板に治具を接続するためのラ
ンド部が形成される一方、前記第１及び第２の割
り基板の分割前には、前記第１の割り基板に形成
されている回路パターンと第２の割り基板に形成
されている前記ランド部とを接続し、前記割り基
板の分割時にはその接続が切断される内層パター
ンが、前記第１及び第２の割り基板間の割り部分
に形成されていることを特徴とする多層プリント
配線基板。[Claims for Utility Model Registration] (1) In a multilayer printed wiring board composed of a plurality of split boards, before dividing the split boards, the circuit patterns formed on each of the split boards are connected, and the circuit patterns formed on the split boards are connected. The inner layer pattern, which is disconnected from the circuit pattern when the board is divided, is
A multilayer printed wiring board, characterized in that it is formed in a split portion between the split boards. (2) A multilayer printed wiring board consisting of a first split board used for device integration and a second split board not used for device integration, wherein a jig is connected to the second split board. On the other hand, before the first and second split boards are divided, a circuit pattern formed on the first split board and a circuit pattern formed on the second split board are formed. The multilayer printed wiring is characterized in that an inner layer pattern that connects the land portion and is disconnected when the split board is divided is formed in the split portion between the first and second split boards. substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10551390U JPH0463175U (en) | 1990-10-05 | 1990-10-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10551390U JPH0463175U (en) | 1990-10-05 | 1990-10-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0463175U true JPH0463175U (en) | 1992-05-29 |
Family
ID=31851221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10551390U Pending JPH0463175U (en) | 1990-10-05 | 1990-10-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0463175U (en) |
-
1990
- 1990-10-05 JP JP10551390U patent/JPH0463175U/ja active Pending
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