JPH0457027B2 - - Google Patents

Info

Publication number
JPH0457027B2
JPH0457027B2 JP59130443A JP13044384A JPH0457027B2 JP H0457027 B2 JPH0457027 B2 JP H0457027B2 JP 59130443 A JP59130443 A JP 59130443A JP 13044384 A JP13044384 A JP 13044384A JP H0457027 B2 JPH0457027 B2 JP H0457027B2
Authority
JP
Japan
Prior art keywords
events
communication
control function
control
message
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP59130443A
Other languages
English (en)
Japanese (ja)
Other versions
JPS619742A (ja
Inventor
Myuki Takasaki
Toshio Hayashi
Shosaku Furubayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PFU Ltd
Original Assignee
PFU Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PFU Ltd filed Critical PFU Ltd
Priority to JP59130443A priority Critical patent/JPS619742A/ja
Publication of JPS619742A publication Critical patent/JPS619742A/ja
Publication of JPH0457027B2 publication Critical patent/JPH0457027B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)
JP59130443A 1984-06-25 1984-06-25 事象管理方式 Granted JPS619742A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59130443A JPS619742A (ja) 1984-06-25 1984-06-25 事象管理方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59130443A JPS619742A (ja) 1984-06-25 1984-06-25 事象管理方式

Publications (2)

Publication Number Publication Date
JPS619742A JPS619742A (ja) 1986-01-17
JPH0457027B2 true JPH0457027B2 (enExample) 1992-09-10

Family

ID=15034363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59130443A Granted JPS619742A (ja) 1984-06-25 1984-06-25 事象管理方式

Country Status (1)

Country Link
JP (1) JPS619742A (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62243057A (ja) * 1986-04-16 1987-10-23 Hitachi Ltd フアイル転送管理方式
JPH01180050A (ja) * 1988-01-11 1989-07-18 Pfu Ltd プロセス間通信制御方式

Also Published As

Publication number Publication date
JPS619742A (ja) 1986-01-17

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