JPH0452560B2 - - Google Patents

Info

Publication number
JPH0452560B2
JPH0452560B2 JP57181148A JP18114882A JPH0452560B2 JP H0452560 B2 JPH0452560 B2 JP H0452560B2 JP 57181148 A JP57181148 A JP 57181148A JP 18114882 A JP18114882 A JP 18114882A JP H0452560 B2 JPH0452560 B2 JP H0452560B2
Authority
JP
Japan
Prior art keywords
pipeline
history information
state
information recording
invalid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57181148A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5969853A (ja
Inventor
Masayuki Ooya
Terutaka Tateishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57181148A priority Critical patent/JPS5969853A/ja
Publication of JPS5969853A publication Critical patent/JPS5969853A/ja
Publication of JPH0452560B2 publication Critical patent/JPH0452560B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Debugging And Monitoring (AREA)
JP57181148A 1982-10-15 1982-10-15 履歴情報記録圧縮方式 Granted JPS5969853A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57181148A JPS5969853A (ja) 1982-10-15 1982-10-15 履歴情報記録圧縮方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57181148A JPS5969853A (ja) 1982-10-15 1982-10-15 履歴情報記録圧縮方式

Publications (2)

Publication Number Publication Date
JPS5969853A JPS5969853A (ja) 1984-04-20
JPH0452560B2 true JPH0452560B2 (US07935154-20110503-C00006.png) 1992-08-24

Family

ID=16095719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57181148A Granted JPS5969853A (ja) 1982-10-15 1982-10-15 履歴情報記録圧縮方式

Country Status (1)

Country Link
JP (1) JPS5969853A (US07935154-20110503-C00006.png)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5875256A (ja) * 1981-10-28 1983-05-06 Fuji Electric Co Ltd 実行命令遂行状態のモニタ方式

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5875256A (ja) * 1981-10-28 1983-05-06 Fuji Electric Co Ltd 実行命令遂行状態のモニタ方式

Also Published As

Publication number Publication date
JPS5969853A (ja) 1984-04-20

Similar Documents

Publication Publication Date Title
JPH0452560B2 (US07935154-20110503-C00006.png)
US4833466A (en) Pulse code modulation decommutator interfacing system
SU1101832A1 (ru) Устройство дл обработки и сжати информации
SU1488815A1 (ru) Устройство для сопряжения источника и приемника информации
SU1168958A1 (ru) Устройство дл ввода информации
SU1686451A1 (ru) Устройство дл сопр жени источника информации с процессором
SU1689957A1 (ru) Устройство пр мого доступа в пам ть ЭВМ
SU1376074A1 (ru) Устройство дл программируемой задержки информации
SU1571601A1 (ru) Устройство дл сопр жени источника информации с процессором
SU1689960A2 (ru) Устройство дл сопр жени источника информации с процессором
RU2217791C1 (ru) Устройство ввода информации
SU1656545A1 (ru) Устройство дл сопр жени источника и приемника информации
SU1180908A1 (ru) Устройство дл обмена данными между оперативной пам тью и внешним устройством
SU1238091A1 (ru) Устройство дл вывода информации
SU1179349A1 (ru) Устройство дл контрол микропрограмм
SU1256034A1 (ru) Устройство дл сопр жени двух ЭВМ с общей пам тью
JPS6184746A (ja) トレ−サ・メモリ・デ−タ記録回路
SU1376091A1 (ru) Устройство дл сопр жени абонентов с ЭВМ
SU1261010A1 (ru) Буферное запоминающее устройство
SU1179351A1 (ru) Устройство дл сопр жени электронно-вычислительной машины с периферийными устройствами
SU1730630A2 (ru) Устройство дл сопр жени источника и приемника информации
SU1605244A1 (ru) Устройство дл сопр жени источника и приемника информации
SU1287237A1 (ru) Буферное запоминающее устройство
RU1833857C (ru) Устройство дл вывода информации
SU972588A1 (ru) Устройство дл управлени записью информации в блок пам ти