JPH0451056B2 - - Google Patents

Info

Publication number
JPH0451056B2
JPH0451056B2 JP61010977A JP1097786A JPH0451056B2 JP H0451056 B2 JPH0451056 B2 JP H0451056B2 JP 61010977 A JP61010977 A JP 61010977A JP 1097786 A JP1097786 A JP 1097786A JP H0451056 B2 JPH0451056 B2 JP H0451056B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
lead
film
substrate
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61010977A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62171132A (ja
Inventor
Masaru Kimura
Takashi Okada
Yoshiro Takahashi
Hiromi Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP61010977A priority Critical patent/JPS62171132A/ja
Publication of JPS62171132A publication Critical patent/JPS62171132A/ja
Publication of JPH0451056B2 publication Critical patent/JPH0451056B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP61010977A 1986-01-23 1986-01-23 半導体チップの実装方法 Granted JPS62171132A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61010977A JPS62171132A (ja) 1986-01-23 1986-01-23 半導体チップの実装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61010977A JPS62171132A (ja) 1986-01-23 1986-01-23 半導体チップの実装方法

Publications (2)

Publication Number Publication Date
JPS62171132A JPS62171132A (ja) 1987-07-28
JPH0451056B2 true JPH0451056B2 (ko) 1992-08-18

Family

ID=11765220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61010977A Granted JPS62171132A (ja) 1986-01-23 1986-01-23 半導体チップの実装方法

Country Status (1)

Country Link
JP (1) JPS62171132A (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02102553A (ja) * 1988-10-12 1990-04-16 Nec Corp 集積回路装置
JPH02101538U (ko) * 1989-01-30 1990-08-13
JPH02252250A (ja) * 1989-03-27 1990-10-11 Nippon Telegr & Teleph Corp <Ntt> 半導体チップ端子接続用フィルムおよび半導体チップ端子接続方法
JPH0498843A (ja) * 1990-08-16 1992-03-31 Nec Corp Ｌｓｉの実装方法

Also Published As

Publication number Publication date
JPS62171132A (ja) 1987-07-28

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