JPH0450629B2 - - Google Patents

Info

Publication number
JPH0450629B2
JPH0450629B2 JP57143708A JP14370882A JPH0450629B2 JP H0450629 B2 JPH0450629 B2 JP H0450629B2 JP 57143708 A JP57143708 A JP 57143708A JP 14370882 A JP14370882 A JP 14370882A JP H0450629 B2 JPH0450629 B2 JP H0450629B2
Authority
JP
Japan
Prior art keywords
signal
circuit
register
hold
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57143708A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5933549A (ja
Inventor
Seiji Eguchi
Minejiro Nojima
Naoyasu Tasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP57143708A priority Critical patent/JPS5933549A/ja
Priority to EP83108170A priority patent/EP0103755A2/en
Publication of JPS5933549A publication Critical patent/JPS5933549A/ja
Publication of JPH0450629B2 publication Critical patent/JPH0450629B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)
  • Microcomputers (AREA)
  • Executing Machine-Instructions (AREA)
JP57143708A 1982-08-19 1982-08-19 Ｃｍｏｓ形１チツプマイクロプロセツサ Granted JPS5933549A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP57143708A JPS5933549A (ja) 1982-08-19 1982-08-19 Ｃｍｏｓ形１チツプマイクロプロセツサ
EP83108170A EP0103755A2 (en) 1982-08-19 1983-08-18 CMOS single chip microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57143708A JPS5933549A (ja) 1982-08-19 1982-08-19 Ｃｍｏｓ形１チツプマイクロプロセツサ

Publications (2)

Publication Number Publication Date
JPS5933549A JPS5933549A (ja) 1984-02-23
JPH0450629B2 true JPH0450629B2 (en, 2012) 1992-08-14

Family

ID=15345122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57143708A Granted JPS5933549A (ja) 1982-08-19 1982-08-19 Ｃｍｏｓ形１チツプマイクロプロセツサ

Country Status (2)

Country Link
EP (1) EP0103755A2 (en, 2012)
JP (1) JPS5933549A (en, 2012)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2150721A (en) * 1983-12-02 1985-07-03 Itt Remote data collection and transport apparatus
JPS61262827A (ja) * 1985-05-15 1986-11-20 Mitsubishi Electric Corp 半導体集積回路装置
JPH0789346B2 (ja) * 1985-07-05 1995-09-27 日本電気株式会社 Ｄｍａコントローラ
DE3701919C1 (de) * 1987-01-23 1988-07-14 Neumann Elektronik Gmbh Verfahren zur Reduzierung der Energieaufnahme einer Fernsprecheinrichtung,deren Versorgung mit elektrischer Energie ueber die Fernsprechleitung erfolgt,sowie Einrichtung zur Druchfuehrung des Verfahrens
JPH0642691B2 (ja) * 1988-05-21 1994-06-01 富士通株式会社 移動電話端末
US5842029A (en) * 1991-10-17 1998-11-24 Intel Corporation Method and apparatus for powering down an integrated circuit transparently and its phase locked loop
GB2260631B (en) * 1991-10-17 1995-06-28 Intel Corp Microprocessor 2X core design
US5935253A (en) * 1991-10-17 1999-08-10 Intel Corporation Method and apparatus for powering down an integrated circuit having a core that operates at a speed greater than the bus frequency
GB2264794B (en) * 1992-03-06 1995-09-20 Intel Corp Method and apparatus for automatic power management in a high integration floppy disk controller
US5473767A (en) * 1992-11-03 1995-12-05 Intel Corporation Method and apparatus for asynchronously stopping the clock in a processor
US5392437A (en) * 1992-11-06 1995-02-21 Intel Corporation Method and apparatus for independently stopping and restarting functional units
US5586332A (en) * 1993-03-24 1996-12-17 Intel Corporation Power management for low power processors through the use of auto clock-throttling
SG48805A1 (en) * 1994-02-04 1998-05-18 Intel Corp Method and apparatus for control of power consumption in a computer system
US5821784A (en) * 1995-12-29 1998-10-13 Intel Corporation Method and apparatus for generating 2/N mode bus clock signals
US5834956A (en) 1995-12-29 1998-11-10 Intel Corporation Core clock correction in a 2/N mode clocking scheme
US5802132A (en) 1995-12-29 1998-09-01 Intel Corporation Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
US5826067A (en) * 1996-09-06 1998-10-20 Intel Corporation Method and apparatus for preventing logic glitches in a 2/n clocking scheme
US5862373A (en) * 1996-09-06 1999-01-19 Intel Corporation Pad cells for a 2/N mode clocking scheme

Also Published As

Publication number Publication date
EP0103755A2 (en) 1984-03-28
JPS5933549A (ja) 1984-02-23

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