JPH0450625B2 - - Google Patents
Info
- Publication number
- JPH0450625B2 JPH0450625B2 JP61169919A JP16991986A JPH0450625B2 JP H0450625 B2 JPH0450625 B2 JP H0450625B2 JP 61169919 A JP61169919 A JP 61169919A JP 16991986 A JP16991986 A JP 16991986A JP H0450625 B2 JPH0450625 B2 JP H0450625B2
- Authority
- JP
- Japan
- Prior art keywords
- address
- memory
- bus
- signal
- refresh
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 11
- 230000008859 change Effects 0.000 claims description 2
- 239000000872 buffer Substances 0.000 description 27
- 238000010586 diagram Methods 0.000 description 5
- 230000004044 response Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61169919A JPS6326753A (ja) | 1986-07-21 | 1986-07-21 | メモリ−バス制御方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61169919A JPS6326753A (ja) | 1986-07-21 | 1986-07-21 | メモリ−バス制御方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6326753A JPS6326753A (ja) | 1988-02-04 |
| JPH0450625B2 true JPH0450625B2 (ko) | 1992-08-14 |
Family
ID=15895383
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61169919A Granted JPS6326753A (ja) | 1986-07-21 | 1986-07-21 | メモリ−バス制御方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6326753A (ko) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6413658A (en) * | 1987-07-07 | 1989-01-18 | Yokogawa Electric Corp | Dram access control device |
| US5440749A (en) * | 1989-08-03 | 1995-08-08 | Nanotronics Corporation | High performance, low cost microprocessor architecture |
| JP4306718B2 (ja) | 2006-11-10 | 2009-08-05 | トヨタ自動車株式会社 | シリンダヘッド |
| CN105355032B (zh) * | 2014-08-22 | 2019-06-04 | 无锡华润矽科微电子有限公司 | 内置可多次编程存储器的学习型遥控电路结构及学习方法 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57196334A (en) * | 1981-05-26 | 1982-12-02 | Toshiba Corp | Memory interface |
-
1986
- 1986-07-21 JP JP61169919A patent/JPS6326753A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57196334A (en) * | 1981-05-26 | 1982-12-02 | Toshiba Corp | Memory interface |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6326753A (ja) | 1988-02-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4128234B2 (ja) | メモリ素子、処理システム、メモリ素子を制御する方法およびダイナミックランダムアクセスメモリを操作する方法 | |
| KR100494201B1 (ko) | 메모리시스템,i/o서브시스템장치,및메모리장치를동작시키는방법 | |
| US4412313A (en) | Random access memory system having high-speed serial data paths | |
| US5394541A (en) | Programmable memory timing method and apparatus for programmably generating generic and then type specific memory timing signals | |
| KR930004426B1 (ko) | 듀얼 포트 판독/기입 레지스터 파일 메모리 및 그 구성방법 | |
| US4792929A (en) | Data processing system with extended memory access | |
| JPH01125795A (ja) | 仮想型スタティック半導体記憶装置及びこの記憶装置を用いたシステム | |
| JP3039557B2 (ja) | 記憶装置 | |
| WO2003007303A2 (en) | Memory device having different burst order addressing for read and write operations | |
| US5943681A (en) | Semiconductor memory device having cache function | |
| EP0509994B1 (en) | Centralized reference and change table for a multiprocessor virtual memory system | |
| US5829016A (en) | Memory system with multiplexed input-output port and systems and methods using the same | |
| JPS59129989A (ja) | デユアル・ポ−ト型ダイナミツク・ランダム・アクセス・メモリ・セル及びその動作方法 | |
| KR100332188B1 (ko) | 커맨드 적재 고대역폭 메모리와 그 메모리 내에서 커맨드를 적재하고 보류중인 동작을 자체 실행하는 방법 | |
| JPH0450625B2 (ko) | ||
| US6092167A (en) | Robust interface for high speed memory access | |
| US5325515A (en) | Single-component memory controller utilizing asynchronous state machines | |
| KR940002595Y1 (ko) | Cpu보드상의 이중 포트 기억장치 회로 | |
| JPH09311812A (ja) | マイクロコンピュータ | |
| US6035372A (en) | Dynamic RAM in a microprocessor system | |
| KR0180780B1 (ko) | 로오 어드레스 카운터 | |
| JPH02187989A (ja) | デュアルポートメモリ | |
| EP0552426A1 (en) | Multilevel memory system | |
| JPS63142589A (ja) | 半導体メモリ | |
| JPH025291A (ja) | 半導体メモリ |