JPS6326753A - メモリ−バス制御方法 - Google Patents

メモリ−バス制御方法

Info

Publication number
JPS6326753A
JPS6326753A JP61169919A JP16991986A JPS6326753A JP S6326753 A JPS6326753 A JP S6326753A JP 61169919 A JP61169919 A JP 61169919A JP 16991986 A JP16991986 A JP 16991986A JP S6326753 A JPS6326753 A JP S6326753A
Authority
JP
Japan
Prior art keywords
address
memory
signal
bus
refresh
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61169919A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0450625B2 (ko
Inventor
Masashi Suenaga
雅士 末永
Koji Ozawa
小沢　幸次
Atsuhiko Nishikawa
敦彦 西川
Manabu Araoka
荒岡　学
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61169919A priority Critical patent/JPS6326753A/ja
Publication of JPS6326753A publication Critical patent/JPS6326753A/ja
Publication of JPH0450625B2 publication Critical patent/JPH0450625B2/ja
Granted legal-status Critical Current

Links

JP61169919A 1986-07-21 1986-07-21 メモリ−バス制御方法 Granted JPS6326753A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61169919A JPS6326753A (ja) 1986-07-21 1986-07-21 メモリ−バス制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61169919A JPS6326753A (ja) 1986-07-21 1986-07-21 メモリ−バス制御方法

Publications (2)

Publication Number Publication Date
JPS6326753A true JPS6326753A (ja) 1988-02-04
JPH0450625B2 JPH0450625B2 (ko) 1992-08-14

Family

ID=15895383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61169919A Granted JPS6326753A (ja) 1986-07-21 1986-07-21 メモリ−バス制御方法

Country Status (1)

Country Link
JP (1) JPS6326753A (ko)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413658A (en) * 1987-07-07 1989-01-18 Yokogawa Electric Corp Dram access control device
EP0786730A1 (en) * 1989-08-03 1997-07-30 MOORE, Charles, H. High performance, low cost microprocessor
US7757654B2 (en) 2006-11-10 2010-07-20 Toyota Jidosha Kabushiki Kaisha Cylinder head
CN105355032A (zh) * 2014-08-22 2016-02-24 无锡华润矽科微电子有限公司 内置可多次编程存储器的学习型遥控电路结构及学习方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57196334A (en) * 1981-05-26 1982-12-02 Toshiba Corp Memory interface

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57196334A (en) * 1981-05-26 1982-12-02 Toshiba Corp Memory interface

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413658A (en) * 1987-07-07 1989-01-18 Yokogawa Electric Corp Dram access control device
EP0786730A1 (en) * 1989-08-03 1997-07-30 MOORE, Charles, H. High performance, low cost microprocessor
US7757654B2 (en) 2006-11-10 2010-07-20 Toyota Jidosha Kabushiki Kaisha Cylinder head
CN105355032A (zh) * 2014-08-22 2016-02-24 无锡华润矽科微电子有限公司 内置可多次编程存储器的学习型遥控电路结构及学习方法

Also Published As

Publication number Publication date
JPH0450625B2 (ko) 1992-08-14

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