JPH0441502B2 - - Google Patents

Info

Publication number
JPH0441502B2
JPH0441502B2 JP58146325A JP14632583A JPH0441502B2 JP H0441502 B2 JPH0441502 B2 JP H0441502B2 JP 58146325 A JP58146325 A JP 58146325A JP 14632583 A JP14632583 A JP 14632583A JP H0441502 B2 JPH0441502 B2 JP H0441502B2
Authority
JP
Japan
Prior art keywords
region
forming
emitter
layer
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58146325A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6038856A (ja
Inventor
Masanori Odaka
Katsumi Ogiue
Takahide Ikeda
Shuichi Myaoka
Nobuo Tanba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58146325A priority Critical patent/JPS6038856A/ja
Publication of JPS6038856A publication Critical patent/JPS6038856A/ja
Publication of JPH0441502B2 publication Critical patent/JPH0441502B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401Combinations of FETs or IGBTs with BJTs

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP58146325A 1983-08-12 1983-08-12 半導体装置及びその製造方法 Granted JPS6038856A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58146325A JPS6038856A (ja) 1983-08-12 1983-08-12 半導体装置及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58146325A JPS6038856A (ja) 1983-08-12 1983-08-12 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JPS6038856A JPS6038856A (ja) 1985-02-28
JPH0441502B2 true JPH0441502B2 (enrdf_load_stackoverflow) 1992-07-08

Family

ID=15405117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58146325A Granted JPS6038856A (ja) 1983-08-12 1983-08-12 半導体装置及びその製造方法

Country Status (1)

Country Link
JP (1) JPS6038856A (enrdf_load_stackoverflow)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0734453B2 (ja) * 1986-09-12 1995-04-12 三菱電機株式会社 半導体集積回路装置の製造方法
JPS6337642A (ja) * 1986-07-31 1988-02-18 Mitsubishi Electric Corp 半導体集積回路装置
JPS63131563A (ja) * 1986-11-20 1988-06-03 Mitsubishi Electric Corp 半導体集積回路装置
JPS63164458A (ja) * 1986-12-26 1988-07-07 Fujitsu Ltd Bi−CMOS素子の製造方法
JPS63205966A (ja) * 1987-02-23 1988-08-25 Matsushita Electronics Corp 半導体集積回路の製造方法
US6875648B1 (en) * 2004-07-09 2005-04-05 Atmel Corporation Fabrication of an EEPROM cell with emitter-polysilicon source/drain regions

Also Published As

Publication number Publication date
JPS6038856A (ja) 1985-02-28

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