JPH0440567U - - Google Patents

Info

Publication number
JPH0440567U
JPH0440567U JP8153390U JP8153390U JPH0440567U JP H0440567 U JPH0440567 U JP H0440567U JP 8153390 U JP8153390 U JP 8153390U JP 8153390 U JP8153390 U JP 8153390U JP H0440567 U JPH0440567 U JP H0440567U
Authority
JP
Japan
Prior art keywords
holes
wiring board
insulating substrate
printed wiring
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8153390U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8153390U priority Critical patent/JPH0440567U/ja
Publication of JPH0440567U publication Critical patent/JPH0440567U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図aとbは、本考案の実施例を示すプリン
ト配線基板の両主面の要部平面図、第2図は、そ
の1つの貫通孔にリード線を半田付けした状態を
示す要部拡大断面図、第3図aとbは、従来例を
示すプリント配線基板の両主面の要部平面図、第
4図は、その1つの貫通孔にリード線を半田付け
した状態を示す要部拡大断面図である。 1……絶縁基板、2……貫通孔、3……貫通孔
の開口部周りの導体膜、4……配線用の導体膜、
6……リード線、7……半田。
Figures 1a and b are plan views of main parts of both main surfaces of a printed wiring board showing an embodiment of the present invention, and Figure 2 is a main part showing a state in which a lead wire is soldered to one of the through holes. The enlarged sectional view and FIGS. 3a and 3b are plan views of main parts of both main surfaces of a printed wiring board showing a conventional example, and FIG. 4 is a main part showing a state in which a lead wire is soldered to one of the through holes. FIG. 1... Insulating substrate, 2... Through hole, 3... Conductor film around the opening of the through hole, 4... Conductor film for wiring,
6... Lead wire, 7... Solder.

Claims (1)

【実用新案登録請求の範囲】 (1) 絶縁基板1の一方の主面から他方の主面に
わたつて貫通孔2,2…を介して導体膜による回
路パターンが形成され、該貫通孔2,2…に挿通
されたリード線6が導体膜に半田付けされるプリ
ント配線基板であつて、前記絶縁基板1の両主面
における貫通孔2,2…の開口部周りの導体膜3
,3…が、リード線6の半田付けに必要最小の広
さで各々分離して形成され、該導体膜3,3…が
、これより幅の狭い配線用の導体膜4,4…を介
して他の導体膜と接続されていることを特徴とす
るプリント配線基板。 (2) 前記絶縁基板1の両主面における貫通孔2
,2…の開口部周りの導体膜3,3…の広さが、
互いにほぼ等しく設定されている実用新案登録請
求の範囲第1孔記載のプリント配線基板。
[Claims for Utility Model Registration] (1) A circuit pattern is formed by a conductive film from one main surface to the other main surface of the insulating substrate 1 through the through holes 2, 2... A printed wiring board in which lead wires 6 inserted through 2 are soldered to a conductor film, and the conductor film 3 around the openings of the through holes 2, 2 on both main surfaces of the insulating substrate 1.
, 3... are formed separately with the minimum width necessary for soldering the lead wire 6, and the conductor films 3, 3... are formed through conductor films 4, 4... for wiring having a narrower width. A printed wiring board characterized in that it is connected to another conductive film. (2) Through holes 2 on both main surfaces of the insulating substrate 1
The width of the conductor films 3, 3... around the openings of , 2... is
The printed wiring board according to the first hole of the utility model registration claim, which is set substantially equal to each other.
JP8153390U 1990-07-31 1990-07-31 Pending JPH0440567U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8153390U JPH0440567U (en) 1990-07-31 1990-07-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8153390U JPH0440567U (en) 1990-07-31 1990-07-31

Publications (1)

Publication Number Publication Date
JPH0440567U true JPH0440567U (en) 1992-04-07

Family

ID=31627570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8153390U Pending JPH0440567U (en) 1990-07-31 1990-07-31

Country Status (1)

Country Link
JP (1) JPH0440567U (en)

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