JPH04274363A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To decrease mask processes at the time of production, and to increase resistance against radiation by combining a split-word line type static random access memory (SRAM) and a thin-film transistor load type SRAM. CONSTITUTION:Two word lines WL and WL are connected respectively in each transfer transistor. Each thin-film transistor load is composed of a drain region 65 and a source region 66 or a drain region 68 and a source region 69 arranged while holding the channel region 67 or 70 of a semiconductor film and gate electrodes, which are insulated from the channel regions and disposed oppositely. Drains are connected to one impurity region of the thin-film transistor load through a pair contact sections 63 and 64 having the same structure respectively in each driver-transistor at that time, and each driver-transistor is connected to the gate electrode of the driver-transistor of the opposite party.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to TFT (thin
film transistor) load type SRAM (
static random access m
This invention relates to improvements in semiconductor memory devices called ``emory''.

[0002] Until recently, SRAMs of the type that use high resistance as a load have been widely used. However,
As the degree of integration improves and the number of memory cells increases, current consumption increases and various problems occur, so it is necessary to avoid this and with advances in semiconductor technology, TF
An SRAM with a load of T has been realized. However, another new problem arises due to the use of the TFT as a load, and it is necessary to solve this problem.

0003

[Prior Art] Figures 30 to 39 show high resistance load type SRA.
40 to 45 are cross-sectional side views of main parts at important points in the process to explain a conventional example of a method for manufacturing a high-resistance load type SRAM. Each shows a plan view of the main parts at key points in the process.
The explanation will be given below with reference to these figures. Incidentally, the cutaway side views of the main parts in FIGS. 30 to 39 are taken along the line YY shown in FIG. 45, which is a plan view of the main parts.

Refer to FIG. 30 30-(1) For example, a silicon dioxide (SiO2) film is used as a pad film, and silicon nitride (Si3 N4) is laminated thereon.
Selective thermal oxidation (e.g. lo
cal oxidation of silic
By applying the on:LOCOS method, a layer of SiO2 with a thickness of, for example, 400 mm is formed on the silicon semiconductor substrate 1.
A field insulating film 2 having a thickness of 0 [Å] is formed. 30-(2) Si3 N4 film and Si used for selective thermal oxidation
The O2 film is removed to expose the active region in the silicon semiconductor substrate 1.

Refer to FIG. 31 31-(1) A gate insulating film 3 made of SiO2 and having a thickness of, for example, 100 [Å] is formed by applying a thermal oxidation method. 31-(2) By applying a resist process in photolithography technology and a wet etching method using hydrofluoric acid as an etchant, the gate insulating film 3 is selectively etched to form a contact hole 3A. do.

Refer to FIGS. 32 and 40 32-(1) Chemical vapor deposition
By applying the CVD method, a first polycrystalline silicon film having a thickness of, for example, 1500 Å is formed. 32-(2) By applying the vapor phase diffusion method, e.g.
[cm-3] of phosphorus (P) is introduced to form an n + -impurity region 5'. In addition, in FIG. 40, for the sake of simplicity,
The first polycrystalline silicon film is omitted.

Refer to FIG. 33 33-(1) Resist process in photolithography technology and reactive ion etching using CCl4/O2 as etching gas.
By applying the etching: RIE) method,
Gate electrode 4 is formed by patterning the first polycrystalline silicon film. Note that this gate electrode 4 is a gate electrode of a word line driver transistor. 33-(2) By applying the ion implantation method, the dose can be reduced to 3×1.
015 [cm-2] and acceleration energy of 40 [keV], As ions are implanted to form a source region 5 and a drain region 6.

Refer to FIGS. 34 and 41 34-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film 7 made of SiO2 with a thickness of 1.5 Å is formed. 34-(2) RI using CHF3/He as the resist process and etching gas in photolithography technology
A ground line contact hole 7A is formed by applying the E method. Note that the ground line contact hole 7A is not visible in FIG.

Refer to FIG. 35 35-(1) By applying the CVD method, a thickness of, for example, 1500 [
A second polycrystalline silicon film is formed. 35-(2) By applying the ion implantation method, the dose can be reduced to 4×1.
015 [cm-2] and acceleration energy of 30 [keV], P is implanted into the second polycrystalline silicon film, and then annealing is performed to lower the resistance. 35-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the second polycrystalline silicon film is patterned to form the ground line 8.

Refer to FIGS. 36 and 42 36-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film 9 made of SiO2 with a thickness of 1.5 Å is formed. 36-(2) Resist process in photolithography technology and RIE using CHF3/He as etching gas
By applying a method, the insulating film 9 is selectively etched to form a load resistance contact hole 9A.

Refer to FIG. 37 37-(1) By applying the CVD method, a thickness of, for example, 1500 [
A third polycrystalline silicon film is formed. 37-(2) By applying the resist process and ion implantation method in photolithography technology, the dose can be reduced to 1.
×1015 [cm-2], and the acceleration energy is 30 [cm-2].
keV], As ions are implanted into the portion that is to become the supply line for the positive power supply voltage VCC and the portion where the high resistance load contacts the gate electrode 4. 37-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the third polycrystalline silicon film is patterned to form a contact portion 10, a high resistance load 11, and a VCC supply line 12.

Refer to FIGS. 38 and 43 38-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film made of SiO2 with a thickness of, for example, 500 Å]
0 [Å] phospho-silicic acid glass
ate glass (PSG)) is formed. In the figure, the two layers of insulating films are shown as one, and this is referred to as an insulating film 13. 38-(2) Heat treatment is performed to reflow and planarize the insulating film 13. 38-(3) Resist process in photolithography technology and RIE using CHF3/He as etching gas
By applying a method, the insulating film 13 and the like are selectively etched to form a bit line contact hole 13A.

Refer to FIGS. 39 and 44. 39-(1) By applying the sputtering method, the thickness can be reduced to, for example, 1.
An Al film of [μm] is formed and patterned by applying ordinary photolithography technology to form the bit line 14. It should be noted that symbols shown in FIGS. 39 and 44 that are not explained, such as BL, will become clear when compared with FIG. 46, which will be described next.

FIG. 45 is a plan view of the main parts of a high resistance load type SRAM completed through the steps described above, and the same symbols as those used in FIGS. 30 to 44 represent the same parts or are the same. It shall have meaning. However, for the sake of simplicity, the bit line 14 made of Al seen in FIGS. 39 and 44 is removed from FIG. 45.

FIG. 46 shows an equivalent circuit diagram of the main part of the high resistance load type SRAM described with reference to FIGS. 30 to 45. In the figure, Q1 and Q2 are drive transistors, Q
3 and Q4 are transfer gate transistors, R
1 and R2 are high resistance loads, WL is a word line, BL and /
BL represents a bit line, S1 and S2 represent nodes, VCC represents a positive power supply voltage, and VSS represents a negative power supply voltage.

Operation of this high resistance load type SRAM,
In particular, memory retention is performed as follows. Now, the positive side power supply voltage VCC = 5 [V], the negative side power supply voltage VS
S = 0 [V], and node S1 = 5 [V].
], node S2=0 [V], transistor Q2 is on and transistor Q1 is off. At the node S1, the potential is maintained at 5 [V] if the transistor Q1 is in the off state and the resistance value in that case is sufficiently high compared to the high resistance load R1. At node S2, the potential is maintained at 0 [V] if transistor Q2 is in the on state and the resistance value in that case is sufficiently lower than that of high resistance load R2.

However, under the above conditions, the negative power supply voltage VCC is supplied from the positive power supply voltage VCC supply line through the node S2.
DC current flows on the SS supply line side, and its value is high resistance load R
It is inversely proportional to the value of 2.

As the degree of integration of such a high resistance load type SRAM increases, the number of memory cells per chip increases, so unless the current consumption per memory cell is reduced, the current consumption of the entire chip will increase. I end up. Therefore, it is necessary to reduce the above-mentioned DC current, which requires increasing the values of the high resistance loads R2 and R1. However, when this resistance value is increased, it becomes difficult to stably maintain the potential at the node on the side where the driving transistor is turned off, which is the node S1 in the above example.

Due to the background described above, a TFT load type SRAM that uses a TFT instead of a high resistance as a load has appeared.

The TFT load type SRAM will now be explained. Similar to the explanation of the high resistance load type SRAM, first, the manufacturing of the TFT load type SRAM will be explained.

FIGS. 47 to 50 show TFT-loaded SRAMs.
51 to 54 are cross-sectional side views of main parts at important points in the process to explain a conventional example of a method for manufacturing TFT.
In order to explain a conventional example of a method for manufacturing a load-type SRAM, principal part plan views at key points in the process are shown, and the following description will be made with reference to these figures. Incidentally, the cutaway side views of the main parts in FIGS. 47 to 50 are taken along the line YY shown in FIG. 54, which is a plan view of the main parts. Incidentally, the steps 30-(1) to 36-(2) in manufacturing the high-resistance load type SRAM described above, that is, the steps up to forming the load resistance contact hole 9A, are as follows:
The process for manufacturing this TFT-loaded SRAM is almost the same, except that the ground line 8 made of the second polycrystalline silicon film is different from the grounding line 8 in the TFT made of the third polycrystalline silicon film. The only difference is that a contact hole 8A (see FIG. 51) necessary for contacting the gate electrode with the active region and the gate electrode 4 made of the first polycrystalline silicon film is formed. Therefore, we will explain the subsequent steps. Of course, Figures 30 to 4
The same symbols as those used in Section 6 shall represent the same parts or have the same meaning.

Refer to FIGS. 47 and 51 47-(1) By applying the CVD method, a thickness of, for example, 1500 [
A third polycrystalline silicon film is formed. 47-(2) By applying the ion implantation method, the dose can be reduced to 4×1.
015 [cm-2], and the acceleration energy is 30 [k].
eV], and P ions are implanted. 47-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the third polycrystalline silicon film is patterned to form the gate electrode 15 of the TFT.

Refer to FIG. 48 48-(1) By applying the CVD method, the TFT gate insulating film 16 made of SiO2 and having a thickness of, for example, 300 [Å] is formed.
form. 48-(2) By applying a resist process in photolithography technology and a wet etching method using hydrofluoric acid as an etchant, the gate insulating film 16 is selectively etched to form a drain contact hole 16A.
form.

Refer to FIGS. 49 and 52 49-(1) By applying the CVD method, a thickness of, for example, 500 [Å]
] A fourth polycrystalline silicon film is formed. 49-(2) By applying the resist process and ion implantation method in photolithography technology, the dose can be reduced to 1
×1014 [cm-2], and the acceleration energy is 10 [cm-2].
keV], the source region and drain region of the TFT,
B ions are implanted into the portion that will become the VCC supply line. 49-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the fourth polycrystalline silicon film is patterned to form the source region 17, drain region 18, channel region 19, and VCC supply line 20 of the TFT.

Refer to FIGS. 50 and 53 50-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film made of SiO2 with a thickness of, for example, 50 Å]
An insulating film made of PSG with a thickness of 0.00 Å is formed. Note that, in this figure as well, like FIGS. 38 and 39, two layers of insulating films are shown as one, and this is referred to as the insulating film 21. 50-(2) Heat treatment is performed to reflow and planarize the insulating film 21. 50-(3) Resist process in photolithography technology and RIE using CHF3/He as etching gas
By applying the method, the insulating film 21 and the like are selectively etched to form a bit line contact hole. 50-(4) Thickness of e.g.
An Al film of [μm] is formed and patterned by applying ordinary photolithography technology to form the bit line 22. Note that symbols shown in FIGS. 50 and 53 that are not explained, such as BL, will become clear when compared with FIG. 55, which will be described next.

FIG. 54 is a plan view of the main parts of the TFT-loaded SRAM completed through the steps described above, and the same symbols as those used in FIGS. 47 to 53 represent the same parts or have the same meanings. shall have. However, for the sake of simplicity, the bit line 22 made of Al seen in FIGS. 50 and 53 is removed from FIG. 54.

FIG. 55 shows an equivalent circuit diagram of the main part of the TFT load type SRAM described with reference to FIGS. 47 to 53. Note that the same symbols as those used in FIGS. 47 to 53 and FIG. 46 represent the same parts or have the same meaning. In the figure, Q5 and Q6 respectively indicate transistors that are load TFTs.

Operation in this TFT load type SRAM,
In particular, memory retention is performed as follows.

Now, suppose that the positive power supply voltage VCC = 5 [V] and the negative power supply voltage VSS = 0 [V], and node S1 = 5 [V] and node S2 = 0 [V]. , transistor Q2 is on and transistor Q6 is on.
is off, transistor Q1 is off, and transistor Q5 is on. Node S
1, transistor Q1 is in an off state,
Further, if the resistance value in that case is sufficiently higher than that in the on state of the transistor Q5, the potential is maintained at 5 [V]. At node S2, transistor Q2 is in an on state, and the resistance value in that case is equal to transistor Q.
If it is sufficiently low compared to the off state of 6, the potential will be 0 [V
] will be maintained.

As described above, under the above conditions, the resistance value of the transistor Q5 or transistor Q6, which is the load, changes depending on the stored information, so that the high resistance load type SRA
The problem with M is resolved and stable information storage can be performed. Note that the transistors Q5 and Q6 used here
The channel of the load TFT, that is, the channel of the load TFT, is made of polycrystalline silicon, and the crystalline state is much worse than that of single crystal, so current leaks even in the off state. Since the leakage current directly becomes the consumption current of the chip, it is desirable to make it as small as possible.

By the way, as is clear from FIG. 50, in this TFT-loaded SRAM, Al
A bit line 22 made of a film is provided, and a load T is provided directly below the bit line 22 via an insulating film 21 made of PSG or the like.
FT channel exists.

Such a configuration can be regarded as a transistor in which the bit line 22 made of an Al film serves as a gate electrode, and the insulating film 21 therebelow serves as a gate insulating film, and the bit line 22, which is the gate electrode, serves as a gate electrode. The potential of the line 22 is 0 [V] (
VSS) to 5 [V] (VCC), and therefore,
The TFT, that is, the transistor Q6, which should be in an off state, becomes close to an on state, resulting in an increase in leakage current and a significant parasitic effect. Therefore, in an attempt to solve these problems, a double-gate structure TFT-loaded SRAM, which is an improved version of the TFT-loaded SRAM, was developed.

This double gate structure TFT loaded SRAM
Now, the third polycrystalline silicon film in the TFT-loaded SRAM explained with reference to FIGS. A polycrystalline silicon film of source region 17, drain region 18, channel region 19, V
The above problem is solved by interposing the bit line 22 made of Al and the fourth polycrystalline silicon film constituting the CC supply line 20 and the like.

FIGS. 56 to 58 show double gate structure TFTs.
In order to explain a conventional example of a method for manufacturing a load-type SRAM, cutaway side views of essential parts at key points in the process are shown, and the following description will be made with reference to these figures. The steps 47-(1) to 49-(3) for manufacturing the TFT-loaded SRAM described above, namely, the source region 17, drain region 18, and channel region 19 of the TFT
, the steps up to the formation of the VCC supply line 20 are almost the same in the steps of manufacturing this double gate structure TFT load type SRAM, so the subsequent steps will be explained. Of course, the same symbols as those used in FIGS. 30 to 55 represent the same parts or have the same meanings.

Refer to FIG. 56 56-(1) By applying the CVD method, an insulating film 23 made of SiO2 and having a thickness of, for example, 500 [Å] is formed. 56-(2) Resist process in photolithography technology and RIE using CHF3 +He as etching gas
By applying a method, the insulating film 23 is selectively etched to form a contact hole 23A for the drain electrode 18 of the TFT.

Refer to FIG. 57 57-(1) By applying the CVD method, a thickness of, for example, 1000 [
A fifth polycrystalline silicon film is formed. 57-(2) By applying an ion implantation method, for example, 4×10 15 [cm −2 ] of P is implanted into the fifth polycrystalline silicon film. 57-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the fifth polycrystalline silicon film is patterned to form the second gate electrode 24 of the TFT.

Refer to FIG. 58 58-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film made of SiO2 with a thickness of, for example, 50 Å]
An insulating film made of PSG with a thickness of 0.00 Å is formed. It should be noted that in this figure, as in FIG. 50, two layers of insulating films are shown as one, and this is referred to as an insulating film 25. 58-(2) Heat treatment is performed to reflow and planarize the insulating film 25. 58-(3) Resist process in photolithography technology and RIE using CHF3/He as etching gas
By applying the method, the insulating film 25 and the like are selectively etched to form a bit line contact hole. 58-(4) By applying a sputtering method, the thickness can be reduced to 1
An Al film with a thickness of [μm] is formed and patterned by applying ordinary photolithography technology to form the bit line 26.

[0038]

[Problem to be solved by the invention] As explained above,
SRAM started with high resistance load type, then TFT load type,
It has evolved into a double gate structure TFT loaded type. However, first, as it should become clear by comparing FIGS. 30 to 39 (particularly FIG. 39) and FIGS. 56 to 58 (particularly FIG.
When shifting to a load type SRAM, the number of polycrystalline silicon films increases by two layers, and the number of mask steps increases by four times.

Next, with reference to the drawings, we will explore other problems in the conventional double-gate structure TFT-loaded SRAM.

FIG. 59 shows a plan view of a main part at key points in the process for explaining a conventional example of a TFT load type SRAM.
The same symbols as those used in Section 1 shall represent the same parts or have the same meaning.

FIG. 59 mentioned here is similar to FIG. 51, but the symbols H1, H2, and H3 shown here represent one memory.
It indicates the three contact holes required for the cell, and thus the conventional TFT-loaded S
In a RAM, three contact holes must be formed three times for each memory cell, and two types of contact holes with different configurations are required.

That is, the film to be etched when forming the contact hole for contacting the fifth polycrystalline silicon film, which will become the second gate electrode 24 of the TFT, is the fourth polycrystalline silicon film in the contact holes H1 and H3. This is the TFT gate insulating film 16 between the polycrystalline silicon film and the fifth polycrystalline silicon film, and the contact hole H.
2, an insulating film existing between (third polycrystalline silicon film and fourth polycrystalline silicon film) + (fourth polycrystalline silicon film and fifth polycrystalline silicon film), and contact hole H1 It is much thicker than that of H3 and H3.

[0043] Also, contact holes H1 and H3
are n+ - impurity region 5', first polycrystalline silicon film, third polycrystalline silicon film, fourth polycrystalline silicon film,
The contact hole H2 is for interconnecting the fifth polycrystalline silicon film, and the contact hole H2 is in the n+ - impurity region 5'.
・First polycrystalline silicon film ・Third polycrystalline silicon film・
This is for interconnecting the fifth polycrystalline silicon film. As can be seen from FIG. 52, the reason for this is that the source electrode of the TFT, which is a fourth polycrystalline silicon film with a different potential, is placed very close to the contact hole H2. This is because the fourth polycrystalline silicon film cannot be placed in the contact hole H2.

In order to improve the manufacturing yield of double-gate structure TFT-loaded SRAM, which is an extremely fine and highly integrated device, it is necessary to reduce the number of contact holes per memory cell, and When forming a contact hole, if there are a plurality of thicknesses of the insulating film to be etched, the control thereof is complicated, and the process margin is reduced accordingly. That is,
Only one type of contact hole is formed at a time.
Moreover, unless the number is reduced as much as possible, it is difficult to improve the manufacturing yield of fine semiconductor elements. for example,
Assuming that the probability of a non-defective product for one contact hole is p and the total number of memory cells is N, the overall probability of a non-defective product P is, if there are 3 contact holes/memory cell, P3 = (
p3 )N = p3N, and in the case of two contact holes/memory cell, P2 = (p2)N = p2N. For example, when p = 0.999999 (99.9999 [%] non-defective product), N = 1024 (1k) P3 = 99.7 [%] P2 = 99.8 [%] N = 1024 × 1024 (1M) P3 = 4.3 [%] P2 = 12.3 [%], and the larger N is, that is, the higher the integration, the less the influence of the number of contact holes per memory cell on manufacturing yield. big.

In addition, double gate structure TFT loaded type SR
Although not directly related to AM, new problems that have arisen in miniaturizing semiconductor devices will be explained.

FIG. 60 shows a plan view of a main part of a semiconductor device at key points in the process to explain the case where a field insulating film surrounding an active region is formed by applying a selective thermal oxidation method. There is.

In the figure, 31 is an oxidation-resistant mask film made of Si3N4, 32 is a field insulating film made of SiO2, 32A is an edge of the field insulating film, and 33 is a field insulating film made of SiO2.
indicate the active region, and a and b represent the bird's
beak (bird's beak) overhang length,
x indicates the width of the oxidation-resistant mask film.

Generally, when the width of the active region 33 is 1 [μm] or less, the width largely depends on the bird's beak pattern. In particular, as illustrated,
When the oxidation-resistant mask film 31 has a so-called dead-end pattern portion, the length b of the bird's beak extending there becomes significantly large. The width of the active region 33 should originally be equal to the width x of the oxidation-resistant mask film 31, but it becomes narrower due to the occurrence of bird's beak.

FIG. 61 shows the overhang length a of the bird's beak.
A diagram for explaining the relationship between and b is shown. As is clear from the figure, when the width of the oxidation-resistant mask film 31, that is, the original width of the active region, becomes less than 1 [μm], the birds
The overhang length b of the beak increases rapidly.

FIG. 62 is a diagram similar to FIG. 40, and in such an SRAM, the area of the contact region between the active region and the first polycrystalline silicon film, that is, the area indicated by symbols 34 and 35 is Narrowed down by Bird's Beak,
This results in a situation where it is not possible to obtain good contact.

By the way, the problems described above can be almost eliminated by making improvements to the split word line type SRAM, which has been known in the past but has various drawbacks and has never been used. Therefore, the problems of the split word line type SRAM will be explained here.

FIG. 63 shows a plan view of essential parts for explaining a conventional split word line type SRAM. In the figure, 41 is an active region, 42 is a word line made of a first polycrystalline silicon film, 43 is a gate electrode of a driving transistor also made of the first polycrystalline silicon film, 44 is a buried contact region, and 45 is a contact hole,
46 and 47 are ground lines, and 48 and 49 are metal bit lines. Note that 42 and 43 are word lines for WL, and 48 for BL and /BL.
Also, numeral 49 indicates a bit line.

In this SRAM, word lines 42 and 4
As shown in Figure 3, it is called the split word line type because there are two word lines per memory cell, and the memory cell has good symmetry and the first polycrystalline type. The number of silicon films, active regions 41, and contact holes is as small as two per one memory cell. However, there are problems such as the area of the memory cell is larger than that of the other SRAMs described above, and the number of metal wirings is three per memory cell. There are very few achievements, and miniaturization and other developments have not been carried out.

The present invention utilizes a split word line type SR
By using a TFT load in AM and making simple modifications, it is attempted to solve manufacturing problems such as a large number of mask steps, or problems such as a large number of contact holes and bird's beak.

[0055]

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes: (1) a memory cell configured to include a pair of transfer transistors, a pair of driver transistors, and a pair of TFT loads; Therefore, each transfer transistor is
Two word lines extending in one direction (for example, a word line WL made of a first polycrystalline silicon film: see FIG. 14) are separately connected to each gate electrode, and each TFT load is Channel regions (for example, channel regions 67 and 70: FIG. 16) of a semiconductor film (for example, third polycrystalline silicon film: see FIGS. 8 and 16) formed on a semiconductor substrate (for example, silicon semiconductor substrate 51: see FIG. 1) A pair of impurity regions (for example, the source region 66 and the drain region 65, the source region 69 and the drain region 68: see FIG. 16) are disposed with a portion between them (see FIG. 16) and the channel region is disposed insulated and facing (For example, lower gate electrodes 60 and 61 made of a second polycrystalline silicon film: see FIGS. 6 and 15)
Each of the driver transistors has its drain connected to one impurity region (of the TFT load) through a pair of connection regions (for example, near the contact hole 59A: see FIGS. 5 and 15) having the same structure. For example, the source region 66 or 69: see FIG. 16) and the gate electrode of the other driver transistor (for example, the gate electrode 55 or 56: see FIGS. 4 and 14), or ,

[0056]
(2) In (1) above, the gate electrodes made of the conductive film of the TFT load (for example, the lower gate electrodes 60 and 61 and the upper gate electrodes 73 and 74: FIGS. 6, 10, 15, 17) An insulating film (for example, insulating films 62 and 72: see FIG. 10) is formed above and below a channel region (for example, channel regions 67 and 70: see FIG. 16) in which a channel region (see FIG.
), or

(3) In (1) or (2) above,
Upper gate electrodes (for example, upper gate electrodes 73 and 74: FIG. 6, FIG. 10,
15, 17) is formed sufficiently thicker than the lower gate electrodes (for example, gate electrodes 60 and 61: see FIGS. 6, 10, 15, and 17). , or

(4) In (1) above, the connection region is an insulating film (for example, insulating films 59 and 62, etc.: FIGS. 20 to 2
A plurality of conductive films (for example, lower gate electrodes 60 and 6 made of a second polycrystalline silicon film) are laminated via a plurality of conductive films (see 2).
1. Contact portion 6 made of third polycrystalline silicon film
3 and 64: see FIGS. 16 and 24), a contact hole penetrating at least one layer of each conductive film (for example, a contact hole 72A: see FIG. 24), and on the plurality of laminated conductive films. A top layer conductive film (for example, upper gate electrodes 73 and 74: see FIG. 25) is laminated through an insulating film (for example, an insulating film 72: see FIG. 25), and a part of the conductive film is in the contact hole. The uppermost conductive film is connected to the side surface of the conductive film penetrated by the contact hole (for example, contact portions 63 and 64, see FIG. 25) and is exposed at the bottom of the contact hole. 25. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to a surface of an underlying conductive film (for example, gate electrodes 55 and 56; see FIG. 25).

(5) In (1) above, the wiring (for example, the fifth A ground line 76 made of a polycrystalline silicon film (see FIGS. 12 and 18), and an impurity diffusion region made of the same material film as the wiring for supplying the source potential and formed in an isolated pattern on the semiconductor substrate. Connected extraction electrode (e.g. extraction electrode 7
7: see FIG. 18) and a bit line made of metal (for example, bit lines BL and /BL: see FIGS. 13 and 19) connected to the extraction electrode, or

0
(6) In (1) or (4) above, a part of the extraction electrode pattern extends above the word line (for example, word line WL: see FIGS. 18 and 19), and near the bit line. (for example, bit lines BL and /BL: see FIG. 19), or

(7) In (1) above, a portion of the periphery of the impurity diffusion region such as the source region or drain region of the driver transistor is defined by the field insulating film, and the area between adjacent memory cells is It is characterized by being located within an active region formed in a ring shape spanning over the area and having no dead end pattern.

[0062]

[Operation] As is clear from the foregoing, the present invention utilizes a simple configuration that combines a split word line type SRAM and a TFT load type SRAM, thereby reducing the masking process during manufacturing and facilitating manufacturing. It also makes it possible to improve the manufacturing yield, and is extremely effective in improving resistance to radiation such as alpha rays or eliminating the effects of bird's beak to ensure a sufficient contact area in contact holes. Can be done.

[0063]

[Embodiment] FIGS. 1 to 13 are cutaway side views of essential parts of a TFT-loaded SRAM at key process points to explain one embodiment of the present invention, and FIGS. 14 to 19 illustrate the same embodiment. The main part plan views of the TFT-loaded SRAM at important steps in the process are shown below, and detailed explanation will be given below with reference to these figures. Incidentally, the cutaway side views of the main parts in FIGS. 1 to 13 are taken along the line XX shown in FIG. 14, which is a plan view of the main parts.

Refer to FIG. 1 1-(1) SiO2 covering the active region of the silicon semiconductor substrate 51
A pad film consisting of Si3 layered on the pad film
By applying a selective thermal oxidation method using an oxidation-resistant mask film made of N4, a field insulating film 52 made of SiO2 and having a thickness of, for example, 4000 [Å] is formed. 1-(2) After removing the pad film and oxidation-resistant mask film to expose the active region, the SiO2
A gate insulating film 53 having a thickness of, for example, 100 [Å] consisting of
form.

Refer to FIG. 2 2-(1) The gate insulating film 53 is selectively etched by applying a resist process in photolithography technology and a wet etching method using hydrofluoric acid as an etchant. Contact that also serves as impurity diffusion
A hole 53A is formed.

Refer to FIG. 3 3-(1) By applying the CVD method, a thickness of, for example, 1000 [
A first polycrystalline silicon film is formed. 3-(2) By applying the vapor phase diffusion method, P is introduced with an impurity concentration of, for example, 1 × 1020 [cm-3], and n+
- forming impurity regions 54;

Refer to FIGS. 4 and 14 4-(1) Resist process in photolithography technology and RI using CCl4 + O2 as etching gas
By applying the E method, the first polycrystalline silicon film is patterned to form gate electrodes 55 and 56 and word line WL. 4-(2) By applying the ion implantation method, As ions are implanted at a dose of, for example, 1 x 1015 [cm-2] and an acceleration energy of 30 [keV].
A + -source region 57 and an n+ -drain region 58 are formed. 4-(3) Remove the photoresist film used when patterning the first polycrystalline silicon film.

Refer to FIGS. 5 and 15 5-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film 59 made of SiO2 with a thickness of 1.5 Å is formed. 5-(2) By applying the RIE method using CHF3 as the etching gas, the insulating film 59 is selectively etched to bring the first polycrystalline silicon film and the second polycrystalline silicon film into contact. A contact hole 59A is formed for this purpose.

Refer to FIGS. 6 and 15 6-(1) By applying the CVD method, a thickness of, for example, 1000 [
A second polycrystalline silicon film is formed. 6-(2) By applying a vapor phase diffusion method, P is introduced into the second polycrystalline silicon film at an impurity concentration of, for example, 1×10 20 [cm −3 ]. 6-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the second polycrystalline silicon film is patterned to form lower gate electrodes 60 and 61 of the TFT. It goes without saying that these lower gate electrodes 60 and 61 are in contact with the gate electrode 55 or 56 of the driving transistor formed of the first polycrystalline silicon film.

Refer to FIG. 7 7-(1) By applying the CVD method, the thickness can be reduced to, for example, 200 [Å].
An insulating film 62 made of SiO2 is formed. 7-(2) Resist process in photolithography technology and RIE using CHF3/He as etching gas
By applying a method, the insulating film 62 is selectively etched to form a contact hole 62A between the second polycrystalline silicon film and the third polycrystalline silicon film.

Refer to FIGS. 8 and 16 8-(1) By applying the CVD method, the thickness can be reduced to 500 Å, for example.
] A third polycrystalline silicon film is formed. 8-(2) By applying the resist process in photolithography technology and the ion implantation method, the third polycrystalline silicon film should be used as the source region and drain region of the TFT and the VCC supply line. Dose 1×101
4 [cm-2], and the acceleration energy is 10 [keV].
) and type B. 8-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the third polycrystalline silicon film is patterned to form contact portions 63 and 64, T
A drain region 65, a source region 66 and a channel region 67 of the FT, a drain region 68, a source region 69 and a channel region 70 of the TFT, and a VCC supply line 71 are formed.

Refer to FIG. 9 9-(1) By applying the CVD method, the thickness can be reduced to, for example, 500 [Å].
An insulating film 72 made of SiO2 is formed. 9-(2) Resist process in photolithography technology and RIE using CHF3/He as etching gas
By applying a method, the insulating film 72 is selectively etched to form a contact hole 72A between the third polycrystalline silicon film and the fourth polycrystalline silicon film.

Refer to FIGS. 10 and 17 10-(1) By applying the CVD method, a thickness of, for example, 1000 [
A fourth polycrystalline silicon film is formed. 10-(2) By applying a vapor phase diffusion method, P is introduced into the fourth polycrystalline silicon film at an impurity concentration of, for example, 1×10 20 [cm −3 ]. 10-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the fourth polycrystalline silicon film is patterned to form upper gate electrodes 73 and 74 of the TFT. It goes without saying that these upper gate electrodes 73 and 74 are substantially in contact with the gate electrode 55 or 56 of the driving transistor formed of the first polycrystalline silicon film.

Refer to FIG. 11 11-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film 75 made of SiO2 with a thickness of 1.5 Å is formed. 11-(2) Resist process in photolithography technology and RIE using CHF3/He as etching gas
By applying the method, an insulating film 75 made of SiO2 is formed.
, 72, 62, 59, and 53 to form a contact between the source region and the fifth polycrystalline silicon film.
A hole 75A is formed. Note that only the source area designated by symbol 57 is shown in the figure.

Refer to FIGS. 12 and 18 12-(1) By applying the CVD method, a thickness of, for example, 1000 [
A fifth polycrystalline silicon film is formed. 12-(2) By applying a vapor phase diffusion method, P is introduced into the fifth polycrystalline silicon film at an impurity concentration of, for example, 1×10 20 [cm −3 ]. 12-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the fifth polycrystalline silicon film is patterned to form a ground line 76 and an extraction electrode 77.
form.

Refer to FIGS. 13 and 19 13-(1) By applying the CVD method, the thickness can be reduced to 500 Å, for example.
) with an insulating film made of SiO2 and a thickness of, for example, 3000 mm.
[Å] BPSG (borophosphosphosphosilic
ate glass) is formed. In the figure, the two layers of insulating films are shown as one, and this is referred to as an insulating film 78. 13-(2) Heat treatment is performed to reflow and planarize the insulating film 78. 13-(3) Resist process in photolithography technology and RIE using CHF3/He as etching gas
By applying a method, the insulating film 78 and the like are selectively etched to form a bit line contact hole 78A. 13-(4) By applying the sputtering method, the thickness, for example, 1
An Al film of [μm] is formed and patterned by applying ordinary photolithography technology to form bit lines BL and /BL.

The embodiment of the present invention described with reference to FIGS. 1 to 19 is basically the same as the conventional technology described with reference to FIGS. The major difference is that in the technology, the ground line is made of a second polycrystalline silicon film, whereas in the present invention, the ground line is made of a fifth polycrystalline silicon film. It becomes.

Furthermore, as will be understood from FIG. 13, the ground line 76 and the upper gate electrode 74 of the TFT constitute a capacitor. Therefore, if this configuration is actively utilized, soft errors caused by radiation such as alpha rays can be reduced. For example, the insulating film 75 between the fourth polycrystalline silicon film and the fifth polycrystalline silicon film may be made thinner, or the fourth polycrystalline silicon film may be formed thicker so that the side surfaces also serve as part of the capacitor. Capacity can be increased by simple means such as using

FIGS. 20 to 28 are cross-sectional side views of the main parts of a TFT-loaded SRAM at key points in the process for explaining other embodiments of the present invention, and these figures will be referred to below. This will be explained in detail. Note that the same symbols as those used in FIGS. 1 to 19 represent the same parts or have the same meaning. and the steps up to forming the n+- drain region 58, that is, 1-(1)
The steps from 4-(3) to 4-(3) are the same in this example, so the next step will be explained.
The same symbols as those used in FIGS. 1 to 19 represent the same parts or have the same meaning.

Refer to FIG. 20 20-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film 59 made of SiO2 with a thickness of 1.5 Å is formed.

Refer to FIG. 21 21-(1) By applying the CVD method, a thickness of, for example, 1000 [
A second polycrystalline silicon film is formed. 21-(2) By applying a vapor phase diffusion method, P is introduced into the second polycrystalline silicon film at an impurity concentration of, for example, 1×10 20 [cm −3 ]. 21-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the second polycrystalline silicon film is patterned to form the lower gate electrode 61 of the TFT and the like.

Refer to FIG. 22 22-(1) By applying the CVD method, a thickness of, for example, 200 [Å]
An insulating film 62 made of SiO2 is formed.

Refer to FIG. 23 23-(1) By applying the CVD method, a thickness of, for example, 500 [Å]
] A third polycrystalline silicon film is formed. 23-(2) By applying the resist process in photolithography technology and the ion implantation method, the third polycrystalline silicon film should be used as the source region and drain region of the TFT and the VCC supply line. Dose 1×101
4 [cm-2], and the acceleration energy is 10 [keV].
) and type B. 23-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the third polycrystalline silicon film is patterned to form a contact portion, a drain region, a source region, a channel region of each TFT, and a VCC supply line. Although the contact portion 64 and channel region 67 are shown in the figure, it is best to refer to FIG. 16 to understand the overall pattern of the structure formed here.

Refer to FIG. 24 24-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film 72 made of SiO2 with a thickness of 1.5 Å is formed. 24-(2) CHF3/He(SiO2) resist process and etching gas in photolithography technology
By applying the RIE method using CCl4 /O2 (for polycrystalline silicon) and CCl4 /O2 (for polycrystalline silicon), the insulating film 72, the third polycrystalline silicon film, the insulating film 62, the second polycrystalline silicon film, and the insulating film 59 are formed. Selective etching is performed to form an interconnect contact hole 72A from the surface to the gate electrode of the driving transistor, which is the first polycrystalline silicon film. Note that this step is the most characteristic step in this embodiment.

Refer to FIG. 25 25-(1) By applying the CVD method, a thickness of, for example, 1000 [
A fourth polycrystalline silicon film is formed. 25-(2) By applying a vapor phase diffusion method, P is introduced into the fourth polycrystalline silicon film at an impurity concentration of, for example, 1×10 20 [cm −3 ]. 25-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the fourth polycrystalline silicon film is patterned to form the upper gate electrode 74 of the TFT and the like. As shown in the figure, the upper gate electrode 74 formed here is in direct contact with the gate electrode 56 of the drive side transistor formed of the first polycrystalline silicon film.

Refer to FIG. 26 26-(1) By applying the CVD method, a thickness of, for example, 1000 [
An insulating film 75 made of SiO2 with a thickness of 1.5 Å is formed. 26-(2) Resist process in photolithography technology and RIE using CHF3/He as etching gas
By applying the method, an insulating film 75 made of SiO2 is formed.
, 72, 62, 59, and 53 to form a contact between the source region and the fifth polycrystalline silicon film.
A hole 75A is formed. Note that only the source area designated by symbol 57 is shown in the figure.

Refer to FIG. 27 27-(1) By applying the CVD method, a thickness of, for example, 1000 [
A fifth polycrystalline silicon film is formed. 27-(2) By applying a vapor phase diffusion method, P is introduced into the fifth polycrystalline silicon film at an impurity concentration of, for example, 1×10 20 [cm −3 ]. 27-(3) Resist process in photolithography technology and RI using CCl4/O2 as etching gas
By applying the E method, the fifth polycrystalline silicon film is patterned to form the ground line 76 and the like.

Refer to FIG. 28 28-(1) By applying the CVD method, a thickness of, for example, 500 [Å]
) with an insulating film made of SiO2 and a thickness of, for example, 3000 mm.
An insulating film made of PSG of [Å] is formed. Note that the two layers of insulating film are also shown here as a single unit, and this is referred to as an insulating film 78. 28-(2) Heat treatment is performed to reflow and planarize the insulating film 78. 28-(3) Resist process in photolithography technology and RIE using CHF3/He as etching gas
By applying a method, the insulating film 78 and the like are selectively etched to form a bit line contact hole 78A. 28-(4) By applying the sputtering method, the thickness, for example, 1
An Al film of [μm] is formed and patterned by applying ordinary photolithography technology to form bit lines BL and /BL.

In the embodiment of the invention described with reference to FIGS. 20-28, step 24-(2) collectively forms the interconnect contact hole 72A, and the embodiment described with reference to FIGS. This makes it possible to reduce the mask process by two times compared to the example. This was easily achieved because there was only one type of connection contact hole, but for example, in the conventional technology described with reference to FIGS. 47 to 53, different types Since a contact hole is required to protect the material, etching and other processes must be strictly controlled.

FIG. 29 shows a plan view of a main part of a TFT-loaded SRAM at key points in the process for explaining still another embodiment of the present invention, and a detailed explanation will be given below with reference to these figures. do. Note that the same symbols as those used in FIGS. 1 to 28 represent the same parts or have the same meanings.

In this embodiment, compared to the previously described embodiments, the patterns of the bit lines BL and /BL are reversed left and right. That is, the transfer gate transistors to which bit lines BL and /BL are connected are reversed.

This is possible because the extraction electrode 77 is formed using the fifth polycrystalline silicon film.

This extraction electrode 77 is extended above the word line WL, so that the Al bit lines BL and /BL come into contact with the area above the first polycrystalline silicon film, that is, The contact hole is relatively shallow, so the depth of the contact hole can be reduced, and accidents in which the bit lines BL and /BL are disconnected due to poor coverage can be reduced. In addition to the embodiments described above, the present invention can be modified in many ways without departing from the scope of the claims.

Furthermore, as can be understood from the plan view of the main part such as FIG. 14, the active region has a ring shape when adjacent memory cells are included, and the dead-end pattern as explained with reference to FIG. 62 is not formed. Therefore, there is no risk that the required area will be occupied and reduced by bird's beaks generated when the field insulating film is formed. Incidentally, this is an extremely large advantage for ultrafine elements using patterns of 1 [μm] or less.

[0095]

Effects of the Invention In the semiconductor memory device according to the present invention, the pair of transfer transistors has two word lines extending in one direction connected to their respective gate electrodes, and a pair of TFT loads. consists of a pair of impurity regions disposed on both sides of a channel region of a semiconductor film formed on a semiconductor substrate, and a gate electrode made of a conductive film disposed opposite and insulated from the channel region. The pair of driver transistors each have a drain connected to the TFT through a pair of connection regions having the same structure.
It is connected to one impurity region of the load and to the gate electrode of the other driver transistor.

As is clear from the foregoing, the present invention utilizes a simple configuration that combines a split word line type SRAM and a TFT load type SRAM, thereby reducing the number of mask steps during manufacturing and facilitating manufacturing. It also makes it possible to improve the manufacturing yield, and is extremely effective in improving resistance to radiation such as alpha rays or eliminating the effects of bird's beak to ensure a sufficient contact area in contact holes. Can be done.

[Brief explanation of the drawing]

FIG. 1 is a cutaway side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 2 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 3 is a cutaway side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 4 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 5 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 6 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 7 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 8 is a cutaway side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 9 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 10 is a cutaway side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 11 is a cutaway side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 12 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 13 is a cutaway side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 14 is a plan view of a main part of a TFT-loaded SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 15 is a plan view of a main part of a TFT load type SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 16 is a plan view of a main part of a TFT load type SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 17 is a plan view of a main part of a TFT-loaded SRAM at key points in the process for explaining an embodiment of the present invention.

FIG. 18 is a plan view of a main part of a TFT load type SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 19 is a plan view of a main part of a TFT load type SRAM at a key point in the process for explaining an embodiment of the present invention.

FIG. 20 is a cross-sectional side view of a main part of a TFT load type SRAM at a key point in the process for explaining another embodiment of the present invention.

FIG. 21 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining another embodiment of the present invention.

FIG. 22 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining another embodiment of the present invention.

FIG. 23 is a cross-sectional side view of a main part of a TFT load type SRAM at a key point in the process for explaining another embodiment of the present invention.

FIG. 24 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining another embodiment of the present invention.

FIG. 25 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining another embodiment of the present invention.

FIG. 26 is a cross-sectional side view of a main part of a TFT load type SRAM at a key point in the process for explaining another embodiment of the present invention.

FIG. 27 is a cross-sectional side view of a main part of a TFT-loaded SRAM at a key point in the process for explaining another embodiment of the present invention.

FIG. 28 is a cross-sectional side view of a main part of a TFT load type SRAM at a key point in the process for explaining another embodiment of the present invention.

FIG. 29 is a plan view of a main part of a TFT-loaded SRAM at a key point in the process for explaining still another embodiment of the present invention.

FIG. 30 is a cutaway side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 31 is a cutaway side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 32 is a side view of a main part cut away at key points in the process for explaining a conventional method for manufacturing a high resistance load type SRAM.

FIG. 33 is a cross-sectional side view of a main part at a key point in the process for explaining a conventional method for manufacturing a high resistance load type SRAM.

FIG. 34 is a cutaway side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 35 is a cross-sectional side view of a main part at a key point in the process for explaining a conventional method for manufacturing a high resistance load type SRAM.

FIG. 36 is a cross-sectional side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 37 is a cutaway side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 38 is a cross-sectional side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 39 is a cross-sectional side view of a main part at a key point in the process for explaining a conventional method for manufacturing a high resistance load type SRAM.

FIG. 40 is a plan view of a main part at key points in the process for explaining a conventional method for manufacturing a high resistance load type SRAM.

FIG. 41 is a plan view of a main part at key points in the process for explaining a conventional method for manufacturing a high resistance load type SRAM.

FIG. 42 is a plan view of a main part at key points in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 43 is a plan view of a main part at key points in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

FIG. 44 is a plan view of a main part at key points in the process for explaining a conventional example of a method for manufacturing a high resistance load type SRAM.

45 is a plan view of a main part of a high resistance load type SRAM completed through the steps described in FIGS. 30 to 44. FIG.

FIG. 46 is an equivalent circuit diagram of a main part of the high resistance load type SRAM described with reference to FIGS. 30 to 45;

FIG. 47 is a cutaway side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a TFT-loaded SRAM.

FIG. 48 is a cutaway side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a TFT-loaded SRAM.

FIG. 49 is a cross-sectional side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a TFT-loaded SRAM.

FIG. 50 is a cutaway side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a TFT-loaded SRAM.

FIG. 51 is a plan view of a main part at key points in the process for explaining a conventional example of a method for manufacturing a TFT-loaded SRAM.

FIG. 52 is a plan view of a main part at key points in the process for explaining a conventional example of a method for manufacturing a TFT-loaded SRAM.

FIG. 53 is a plan view of a main part at key points in the process for explaining a conventional example of a method for manufacturing a TFT-loaded SRAM.

FIG. 54 is a plan view of a main part at key points in the process for explaining a conventional example of a method for manufacturing a TFT-loaded SRAM.

FIG. 55 shows an equivalent circuit diagram of a main part of the TFT load type SRAM described with reference to FIGS. 47 to 53;

FIG. 56 is a cross-sectional side view of a main part at a key point in the process for explaining a conventional example of a method for manufacturing a double-gate structure TFT-loaded SRAM.

FIG. 57 is a cross-sectional side view of a main part at a key point in the process for explaining a conventional method for manufacturing a double-gate structure TFT-loaded SRAM.

FIG. 58 is a cross-sectional side view of a main part at a key point in the process for explaining a conventional method for manufacturing a double-gate structure TFT-loaded SRAM.

FIG. 59 is a plan view of a main part at key points in the process for explaining a conventional example of a TFT-loaded SRAM.

FIG. 60 is a plan view of a main part of a semiconductor device at a key point in the process for explaining a case where a field insulating film surrounding an active region is formed by applying a selective thermal oxidation method.

FIG. 61 is a diagram for explaining the relationship between bird's beak overhang lengths a and b.

FIG. 62 is a plan view of the main part of the SRAM at key points in the process.

FIG. 63 is a plan view of essential parts for explaining a conventional split word line type SRAM.

[Explanation of symbols]

51 Silicon semiconductor substrate 52 Field insulating film 53 Gate insulating film 53A Contact hole 54 N+ - impurity region 55 Gate electrode 56 Gate electrode 57 N+ - Source region 58 N+ - Drain region 59 Insulating film 59A Contact hole 60 Lower gate electrode 61 Lower gate electrode 62 Insulating film 62A Contact hole 63 Contact portion 64 Contact portion 65 TFT drain region 66 TFT source region 67 TFT channel region 68 TFT drain region 69 TFT source region 70 TFT channel region 71 VCC supply Line 72 Insulating film 72A Contact hole 73 Upper gate electrode 74 Upper gate electrode 75 Insulating film 75A Contact hole 76 Ground line 77 Leading electrode 78 Insulating film 78A Bit line contact hole BL Bit line/BL Bit line WL Word line

Claims (7)

[Claims] 1. A memory cell configured to include a pair of transfer transistors, a pair of driver transistors, and a pair of TFT loads, each of the transfer transistors extending in one direction to a respective gate electrode. The two word lines connected to each other are separately connected, and each of the TFT loads includes a pair of impurity regions and the channel region disposed across a portion of a semiconductor film formed on a semiconductor substrate that will become a channel region. Each of the driver transistors has a gate electrode made of a conductive film that is insulated and arranged facing each other, and each of the driver transistors has a drain connected to one impurity region of the TFT load through a pair of connection regions of the same structure. A semiconductor memory device characterized in that the semiconductor memory device is connected to the gate electrode of a partner driver transistor. 2. The gate electrode of the TFT load, which is made of a conductive film, is formed above and below a channel region formed in a semiconductor film with an insulating film interposed therebetween. Semiconductor storage device. 3. The semiconductor memory device according to claim 1, wherein the upper gate electrode made of a conductive film in the TFT load is formed sufficiently thicker than the lower gate electrode. . 4. The connection region includes a plurality of conductive films laminated with an insulating film interposed therebetween, a contact hole penetrating at least one of the conductive films, and an insulating film on the plurality of laminated conductive films. an uppermost conductive film layered through the contact hole and partially located within the contact hole;
The uppermost conductive film is connected to the side surface of the conductive film penetrated by the contact hole, and is also connected to the surface of the underlying conductive film exposed at the bottom of the contact hole. 2. The semiconductor memory device according to claim 1. 5. A wiring at least partially made of a polycrystalline silicon film, extending in the same direction as the word line and supplying a source potential to the driver transistor, and a film made of the same material as the wiring supplying the source potential. Claim 1 characterized in that the bit line comprises an extraction electrode formed of and connected to an impurity diffusion region formed in a semiconductor substrate with an isolated pattern, and a bit line made of metal connected to the extraction electrode. The semiconductor storage device described above. 6. The semiconductor memory device according to claim 1, wherein a part of the pattern of the extraction electrode extends above the word line and is connected to the bit line in the vicinity thereof. 7. A part of the periphery of an impurity diffusion region such as a source region or a drain region of a driver transistor is defined by a field insulating film and is formed in a ring shape spanning between adjacent memory cells. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is located in a divided active region and has no dead end pattern.